1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "wifi.h" 27 #include "core.h" 28 #include "pci.h" 29 #include "base.h" 30 #include "ps.h" 31 #include "efuse.h" 32 #include <linux/interrupt.h> 33 #include <linux/export.h> 34 #include <linux/module.h> 35 36 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 37 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 38 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 39 MODULE_LICENSE("GPL"); 40 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 41 42 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 43 INTEL_VENDOR_ID, 44 ATI_VENDOR_ID, 45 AMD_VENDOR_ID, 46 SIS_VENDOR_ID 47 }; 48 49 static const u8 ac_to_hwq[] = { 50 VO_QUEUE, 51 VI_QUEUE, 52 BE_QUEUE, 53 BK_QUEUE 54 }; 55 56 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 57 { 58 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 59 __le16 fc = rtl_get_fc(skb); 60 u8 queue_index = skb_get_queue_mapping(skb); 61 struct ieee80211_hdr *hdr; 62 63 if (unlikely(ieee80211_is_beacon(fc))) 64 return BEACON_QUEUE; 65 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 66 return MGNT_QUEUE; 67 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 68 if (ieee80211_is_nullfunc(fc)) 69 return HIGH_QUEUE; 70 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 71 hdr = rtl_get_hdr(skb); 72 73 if (is_multicast_ether_addr(hdr->addr1) || 74 is_broadcast_ether_addr(hdr->addr1)) 75 return HIGH_QUEUE; 76 } 77 78 return ac_to_hwq[queue_index]; 79 } 80 81 /* Update PCI dependent default settings*/ 82 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 83 { 84 struct rtl_priv *rtlpriv = rtl_priv(hw); 85 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 86 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 87 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 88 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 89 u8 init_aspm; 90 91 ppsc->reg_rfps_level = 0; 92 ppsc->support_aspm = false; 93 94 /*Update PCI ASPM setting */ 95 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 96 switch (rtlpci->const_pci_aspm) { 97 case 0: 98 /*No ASPM */ 99 break; 100 101 case 1: 102 /*ASPM dynamically enabled/disable. */ 103 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 104 break; 105 106 case 2: 107 /*ASPM with Clock Req dynamically enabled/disable. */ 108 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 109 RT_RF_OFF_LEVL_CLK_REQ); 110 break; 111 112 case 3: 113 /* Always enable ASPM and Clock Req 114 * from initialization to halt. 115 */ 116 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 117 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 118 RT_RF_OFF_LEVL_CLK_REQ); 119 break; 120 121 case 4: 122 /* Always enable ASPM without Clock Req 123 * from initialization to halt. 124 */ 125 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 126 RT_RF_OFF_LEVL_CLK_REQ); 127 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 128 break; 129 } 130 131 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 132 133 /*Update Radio OFF setting */ 134 switch (rtlpci->const_hwsw_rfoff_d3) { 135 case 1: 136 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 138 break; 139 140 case 2: 141 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 142 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 144 break; 145 146 case 3: 147 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 148 break; 149 } 150 151 /*Set HW definition to determine if it supports ASPM. */ 152 switch (rtlpci->const_support_pciaspm) { 153 case 0: 154 /*Not support ASPM. */ 155 ppsc->support_aspm = false; 156 break; 157 case 1: 158 /*Support ASPM. */ 159 ppsc->support_aspm = true; 160 ppsc->support_backdoor = true; 161 break; 162 case 2: 163 /*ASPM value set by chipset. */ 164 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 165 ppsc->support_aspm = true; 166 break; 167 default: 168 pr_err("switch case %#x not processed\n", 169 rtlpci->const_support_pciaspm); 170 break; 171 } 172 173 /* toshiba aspm issue, toshiba will set aspm selfly 174 * so we should not set aspm in driver 175 */ 176 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 177 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 178 init_aspm == 0x43) 179 ppsc->support_aspm = false; 180 } 181 182 static bool _rtl_pci_platform_switch_device_pci_aspm( 183 struct ieee80211_hw *hw, 184 u8 value) 185 { 186 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 187 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 188 189 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 190 value |= 0x40; 191 192 pci_write_config_byte(rtlpci->pdev, 0x80, value); 193 194 return false; 195 } 196 197 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 198 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 199 { 200 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 201 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 202 203 pci_write_config_byte(rtlpci->pdev, 0x81, value); 204 205 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 206 udelay(100); 207 } 208 209 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 210 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 211 { 212 struct rtl_priv *rtlpriv = rtl_priv(hw); 213 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 214 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 215 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 216 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 217 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 218 /*Retrieve original configuration settings. */ 219 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 220 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 221 pcibridge_linkctrlreg; 222 u16 aspmlevel = 0; 223 u8 tmp_u1b = 0; 224 225 if (!ppsc->support_aspm) 226 return; 227 228 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 229 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 230 "PCI(Bridge) UNKNOWN\n"); 231 232 return; 233 } 234 235 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 236 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 237 _rtl_pci_switch_clk_req(hw, 0x0); 238 } 239 240 /*for promising device will in L0 state after an I/O. */ 241 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 242 243 /*Set corresponding value. */ 244 aspmlevel |= BIT(0) | BIT(1); 245 linkctrl_reg &= ~aspmlevel; 246 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 247 248 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 249 udelay(50); 250 251 /*4 Disable Pci Bridge ASPM */ 252 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 253 pcibridge_linkctrlreg); 254 255 udelay(50); 256 } 257 258 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 259 *power saving We should follow the sequence to enable 260 *RTL8192SE first then enable Pci Bridge ASPM 261 *or the system will show bluescreen. 262 */ 263 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 264 { 265 struct rtl_priv *rtlpriv = rtl_priv(hw); 266 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 267 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 268 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 269 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 270 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 271 u16 aspmlevel; 272 u8 u_pcibridge_aspmsetting; 273 u8 u_device_aspmsetting; 274 275 if (!ppsc->support_aspm) 276 return; 277 278 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 279 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 280 "PCI(Bridge) UNKNOWN\n"); 281 return; 282 } 283 284 /*4 Enable Pci Bridge ASPM */ 285 286 u_pcibridge_aspmsetting = 287 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 288 rtlpci->const_hostpci_aspm_setting; 289 290 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 291 u_pcibridge_aspmsetting &= ~BIT(0); 292 293 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 294 u_pcibridge_aspmsetting); 295 296 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 297 "PlatformEnableASPM(): Write reg[%x] = %x\n", 298 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 299 u_pcibridge_aspmsetting); 300 301 udelay(50); 302 303 /*Get ASPM level (with/without Clock Req) */ 304 aspmlevel = rtlpci->const_devicepci_aspm_setting; 305 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 306 307 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 308 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 309 310 u_device_aspmsetting |= aspmlevel; 311 312 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 313 314 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 315 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 316 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 317 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 318 } 319 udelay(100); 320 } 321 322 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 323 { 324 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 325 326 bool status = false; 327 u8 offset_e0; 328 unsigned int offset_e4; 329 330 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 331 332 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 333 334 if (offset_e0 == 0xA0) { 335 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 336 if (offset_e4 & BIT(23)) 337 status = true; 338 } 339 340 return status; 341 } 342 343 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 344 struct rtl_priv **buddy_priv) 345 { 346 struct rtl_priv *rtlpriv = rtl_priv(hw); 347 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 348 bool find_buddy_priv = false; 349 struct rtl_priv *tpriv; 350 struct rtl_pci_priv *tpcipriv = NULL; 351 352 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 353 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 354 list) { 355 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 356 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 357 "pcipriv->ndis_adapter.funcnumber %x\n", 358 pcipriv->ndis_adapter.funcnumber); 359 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 360 "tpcipriv->ndis_adapter.funcnumber %x\n", 361 tpcipriv->ndis_adapter.funcnumber); 362 363 if (pcipriv->ndis_adapter.busnumber == 364 tpcipriv->ndis_adapter.busnumber && 365 pcipriv->ndis_adapter.devnumber == 366 tpcipriv->ndis_adapter.devnumber && 367 pcipriv->ndis_adapter.funcnumber != 368 tpcipriv->ndis_adapter.funcnumber) { 369 find_buddy_priv = true; 370 break; 371 } 372 } 373 } 374 375 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 376 "find_buddy_priv %d\n", find_buddy_priv); 377 378 if (find_buddy_priv) 379 *buddy_priv = tpriv; 380 381 return find_buddy_priv; 382 } 383 384 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 385 { 386 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 387 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 388 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 389 u8 linkctrl_reg; 390 u8 num4bbytes; 391 392 num4bbytes = (capabilityoffset + 0x10) / 4; 393 394 /*Read Link Control Register */ 395 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 396 397 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 398 } 399 400 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 401 struct ieee80211_hw *hw) 402 { 403 struct rtl_priv *rtlpriv = rtl_priv(hw); 404 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 405 406 u8 tmp; 407 u16 linkctrl_reg; 408 409 /*Link Control Register */ 410 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 411 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 412 413 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 414 pcipriv->ndis_adapter.linkctrl_reg); 415 416 pci_read_config_byte(pdev, 0x98, &tmp); 417 tmp |= BIT(4); 418 pci_write_config_byte(pdev, 0x98, tmp); 419 420 tmp = 0x17; 421 pci_write_config_byte(pdev, 0x70f, tmp); 422 } 423 424 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 425 { 426 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 427 428 _rtl_pci_update_default_setting(hw); 429 430 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 431 /*Always enable ASPM & Clock Req. */ 432 rtl_pci_enable_aspm(hw); 433 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 434 } 435 } 436 437 static void _rtl_pci_io_handler_init(struct device *dev, 438 struct ieee80211_hw *hw) 439 { 440 struct rtl_priv *rtlpriv = rtl_priv(hw); 441 442 rtlpriv->io.dev = dev; 443 444 rtlpriv->io.write8_async = pci_write8_async; 445 rtlpriv->io.write16_async = pci_write16_async; 446 rtlpriv->io.write32_async = pci_write32_async; 447 448 rtlpriv->io.read8_sync = pci_read8_sync; 449 rtlpriv->io.read16_sync = pci_read16_sync; 450 rtlpriv->io.read32_sync = pci_read32_sync; 451 } 452 453 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 454 struct sk_buff *skb, 455 struct rtl_tcb_desc *tcb_desc, u8 tid) 456 { 457 struct rtl_priv *rtlpriv = rtl_priv(hw); 458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 459 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 460 struct sk_buff *next_skb; 461 u8 additionlen = FCS_LEN; 462 463 /* here open is 4, wep/tkip is 8, aes is 12*/ 464 if (info->control.hw_key) 465 additionlen += info->control.hw_key->icv_len; 466 467 /* The most skb num is 6 */ 468 tcb_desc->empkt_num = 0; 469 spin_lock_bh(&rtlpriv->locks.waitq_lock); 470 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 471 struct ieee80211_tx_info *next_info; 472 473 next_info = IEEE80211_SKB_CB(next_skb); 474 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 475 tcb_desc->empkt_len[tcb_desc->empkt_num] = 476 next_skb->len + additionlen; 477 tcb_desc->empkt_num++; 478 } else { 479 break; 480 } 481 482 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 483 next_skb)) 484 break; 485 486 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 487 break; 488 } 489 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 490 491 return true; 492 } 493 494 /* just for early mode now */ 495 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 496 { 497 struct rtl_priv *rtlpriv = rtl_priv(hw); 498 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 499 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 500 struct sk_buff *skb = NULL; 501 struct ieee80211_tx_info *info = NULL; 502 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 503 int tid; 504 505 if (!rtlpriv->rtlhal.earlymode_enable) 506 return; 507 508 if (rtlpriv->dm.supp_phymode_switch && 509 (rtlpriv->easy_concurrent_ctl.switch_in_process || 510 (rtlpriv->buddy_priv && 511 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 512 return; 513 /* we just use em for BE/BK/VI/VO */ 514 for (tid = 7; tid >= 0; tid--) { 515 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 516 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 517 518 while (!mac->act_scanning && 519 rtlpriv->psc.rfpwr_state == ERFON) { 520 struct rtl_tcb_desc tcb_desc; 521 522 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 523 524 spin_lock_bh(&rtlpriv->locks.waitq_lock); 525 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 526 (ring->entries - skb_queue_len(&ring->queue) > 527 rtlhal->max_earlymode_num)) { 528 skb = skb_dequeue(&mac->skb_waitq[tid]); 529 } else { 530 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 531 break; 532 } 533 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 534 535 /* Some macaddr can't do early mode. like 536 * multicast/broadcast/no_qos data 537 */ 538 info = IEEE80211_SKB_CB(skb); 539 if (info->flags & IEEE80211_TX_CTL_AMPDU) 540 _rtl_update_earlymode_info(hw, skb, 541 &tcb_desc, tid); 542 543 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 544 } 545 } 546 } 547 548 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 549 { 550 struct rtl_priv *rtlpriv = rtl_priv(hw); 551 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 552 553 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 554 555 while (skb_queue_len(&ring->queue)) { 556 struct sk_buff *skb; 557 struct ieee80211_tx_info *info; 558 __le16 fc; 559 u8 tid; 560 u8 *entry; 561 562 if (rtlpriv->use_new_trx_flow) 563 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 564 else 565 entry = (u8 *)(&ring->desc[ring->idx]); 566 567 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 568 return; 569 ring->idx = (ring->idx + 1) % ring->entries; 570 571 skb = __skb_dequeue(&ring->queue); 572 pci_unmap_single(rtlpci->pdev, 573 rtlpriv->cfg->ops-> 574 get_desc(hw, (u8 *)entry, true, 575 HW_DESC_TXBUFF_ADDR), 576 skb->len, PCI_DMA_TODEVICE); 577 578 /* remove early mode header */ 579 if (rtlpriv->rtlhal.earlymode_enable) 580 skb_pull(skb, EM_HDR_LEN); 581 582 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 583 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 584 ring->idx, 585 skb_queue_len(&ring->queue), 586 *(u16 *)(skb->data + 22)); 587 588 if (prio == TXCMD_QUEUE) { 589 dev_kfree_skb(skb); 590 goto tx_status_ok; 591 } 592 593 /* for sw LPS, just after NULL skb send out, we can 594 * sure AP knows we are sleeping, we should not let 595 * rf sleep 596 */ 597 fc = rtl_get_fc(skb); 598 if (ieee80211_is_nullfunc(fc)) { 599 if (ieee80211_has_pm(fc)) { 600 rtlpriv->mac80211.offchan_delay = true; 601 rtlpriv->psc.state_inap = true; 602 } else { 603 rtlpriv->psc.state_inap = false; 604 } 605 } 606 if (ieee80211_is_action(fc)) { 607 struct ieee80211_mgmt *action_frame = 608 (struct ieee80211_mgmt *)skb->data; 609 if (action_frame->u.action.u.ht_smps.action == 610 WLAN_HT_ACTION_SMPS) { 611 dev_kfree_skb(skb); 612 goto tx_status_ok; 613 } 614 } 615 616 /* update tid tx pkt num */ 617 tid = rtl_get_tid(skb); 618 if (tid <= 7) 619 rtlpriv->link_info.tidtx_inperiod[tid]++; 620 621 info = IEEE80211_SKB_CB(skb); 622 ieee80211_tx_info_clear_status(info); 623 624 info->flags |= IEEE80211_TX_STAT_ACK; 625 /*info->status.rates[0].count = 1; */ 626 627 ieee80211_tx_status_irqsafe(hw, skb); 628 629 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 630 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 631 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 632 prio, ring->idx, 633 skb_queue_len(&ring->queue)); 634 635 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 636 } 637 tx_status_ok: 638 skb = NULL; 639 } 640 641 if (((rtlpriv->link_info.num_rx_inperiod + 642 rtlpriv->link_info.num_tx_inperiod) > 8) || 643 rtlpriv->link_info.num_rx_inperiod > 2) 644 rtl_lps_leave(hw); 645 } 646 647 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 648 struct sk_buff *new_skb, u8 *entry, 649 int rxring_idx, int desc_idx) 650 { 651 struct rtl_priv *rtlpriv = rtl_priv(hw); 652 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 653 u32 bufferaddress; 654 u8 tmp_one = 1; 655 struct sk_buff *skb; 656 657 if (likely(new_skb)) { 658 skb = new_skb; 659 goto remap; 660 } 661 skb = dev_alloc_skb(rtlpci->rxbuffersize); 662 if (!skb) 663 return 0; 664 665 remap: 666 /* just set skb->cb to mapping addr for pci_unmap_single use */ 667 *((dma_addr_t *)skb->cb) = 668 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 669 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 670 bufferaddress = *((dma_addr_t *)skb->cb); 671 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 672 return 0; 673 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 674 if (rtlpriv->use_new_trx_flow) { 675 /* skb->cb may be 64 bit address */ 676 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 677 HW_DESC_RX_PREPARE, 678 (u8 *)(dma_addr_t *)skb->cb); 679 } else { 680 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 681 HW_DESC_RXBUFF_ADDR, 682 (u8 *)&bufferaddress); 683 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 684 HW_DESC_RXPKT_LEN, 685 (u8 *)&rtlpci->rxbuffersize); 686 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 687 HW_DESC_RXOWN, 688 (u8 *)&tmp_one); 689 } 690 return 1; 691 } 692 693 /* inorder to receive 8K AMSDU we have set skb to 694 * 9100bytes in init rx ring, but if this packet is 695 * not a AMSDU, this large packet will be sent to 696 * TCP/IP directly, this cause big packet ping fail 697 * like: "ping -s 65507", so here we will realloc skb 698 * based on the true size of packet, Mac80211 699 * Probably will do it better, but does not yet. 700 * 701 * Some platform will fail when alloc skb sometimes. 702 * in this condition, we will send the old skb to 703 * mac80211 directly, this will not cause any other 704 * issues, but only this packet will be lost by TCP/IP 705 */ 706 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 707 struct sk_buff *skb, 708 struct ieee80211_rx_status rx_status) 709 { 710 if (unlikely(!rtl_action_proc(hw, skb, false))) { 711 dev_kfree_skb_any(skb); 712 } else { 713 struct sk_buff *uskb = NULL; 714 715 uskb = dev_alloc_skb(skb->len + 128); 716 if (likely(uskb)) { 717 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 718 sizeof(rx_status)); 719 skb_put_data(uskb, skb->data, skb->len); 720 dev_kfree_skb_any(skb); 721 ieee80211_rx_irqsafe(hw, uskb); 722 } else { 723 ieee80211_rx_irqsafe(hw, skb); 724 } 725 } 726 } 727 728 /*hsisr interrupt handler*/ 729 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 730 { 731 struct rtl_priv *rtlpriv = rtl_priv(hw); 732 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 733 734 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 735 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 736 rtlpci->sys_irq_mask); 737 } 738 739 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 740 { 741 struct rtl_priv *rtlpriv = rtl_priv(hw); 742 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 743 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 744 struct ieee80211_rx_status rx_status = { 0 }; 745 unsigned int count = rtlpci->rxringcount; 746 u8 own; 747 u8 tmp_one; 748 bool unicast = false; 749 u8 hw_queue = 0; 750 unsigned int rx_remained_cnt = 0; 751 struct rtl_stats stats = { 752 .signal = 0, 753 .rate = 0, 754 }; 755 756 /*RX NORMAL PKT */ 757 while (count--) { 758 struct ieee80211_hdr *hdr; 759 __le16 fc; 760 u16 len; 761 /*rx buffer descriptor */ 762 struct rtl_rx_buffer_desc *buffer_desc = NULL; 763 /*if use new trx flow, it means wifi info */ 764 struct rtl_rx_desc *pdesc = NULL; 765 /*rx pkt */ 766 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 767 rtlpci->rx_ring[rxring_idx].idx]; 768 struct sk_buff *new_skb; 769 770 if (rtlpriv->use_new_trx_flow) { 771 if (rx_remained_cnt == 0) 772 rx_remained_cnt = 773 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 774 hw_queue); 775 if (rx_remained_cnt == 0) 776 return; 777 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 778 rtlpci->rx_ring[rxring_idx].idx]; 779 pdesc = (struct rtl_rx_desc *)skb->data; 780 } else { /* rx descriptor */ 781 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 782 rtlpci->rx_ring[rxring_idx].idx]; 783 784 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 785 false, 786 HW_DESC_OWN); 787 if (own) /* wait data to be filled by hardware */ 788 return; 789 } 790 791 /* Reaching this point means: data is filled already 792 * AAAAAAttention !!! 793 * We can NOT access 'skb' before 'pci_unmap_single' 794 */ 795 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 796 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 797 798 /* get a new skb - if fail, old one will be reused */ 799 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 800 if (unlikely(!new_skb)) 801 goto no_new; 802 memset(&rx_status, 0, sizeof(rx_status)); 803 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 804 &rx_status, (u8 *)pdesc, skb); 805 806 if (rtlpriv->use_new_trx_flow) 807 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 808 (u8 *)buffer_desc, 809 hw_queue); 810 811 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 812 HW_DESC_RXPKT_LEN); 813 814 if (skb->end - skb->tail > len) { 815 skb_put(skb, len); 816 if (rtlpriv->use_new_trx_flow) 817 skb_reserve(skb, stats.rx_drvinfo_size + 818 stats.rx_bufshift + 24); 819 else 820 skb_reserve(skb, stats.rx_drvinfo_size + 821 stats.rx_bufshift); 822 } else { 823 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 824 "skb->end - skb->tail = %d, len is %d\n", 825 skb->end - skb->tail, len); 826 dev_kfree_skb_any(skb); 827 goto new_trx_end; 828 } 829 /* handle command packet here */ 830 if (rtlpriv->cfg->ops->rx_command_packet && 831 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) { 832 dev_kfree_skb_any(skb); 833 goto new_trx_end; 834 } 835 836 /* NOTICE This can not be use for mac80211, 837 * this is done in mac80211 code, 838 * if done here sec DHCP will fail 839 * skb_trim(skb, skb->len - 4); 840 */ 841 842 hdr = rtl_get_hdr(skb); 843 fc = rtl_get_fc(skb); 844 845 if (!stats.crc && !stats.hwerror) { 846 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 847 sizeof(rx_status)); 848 849 if (is_broadcast_ether_addr(hdr->addr1)) { 850 ;/*TODO*/ 851 } else if (is_multicast_ether_addr(hdr->addr1)) { 852 ;/*TODO*/ 853 } else { 854 unicast = true; 855 rtlpriv->stats.rxbytesunicast += skb->len; 856 } 857 rtl_is_special_data(hw, skb, false, true); 858 859 if (ieee80211_is_data(fc)) { 860 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 861 if (unicast) 862 rtlpriv->link_info.num_rx_inperiod++; 863 } 864 865 rtl_collect_scan_list(hw, skb); 866 867 /* static bcn for roaming */ 868 rtl_beacon_statistic(hw, skb); 869 rtl_p2p_info(hw, (void *)skb->data, skb->len); 870 /* for sw lps */ 871 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 872 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 873 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 874 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 875 (ieee80211_is_beacon(fc) || 876 ieee80211_is_probe_resp(fc))) { 877 dev_kfree_skb_any(skb); 878 } else { 879 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 880 } 881 } else { 882 dev_kfree_skb_any(skb); 883 } 884 new_trx_end: 885 if (rtlpriv->use_new_trx_flow) { 886 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 887 rtlpci->rx_ring[hw_queue].next_rx_rp %= 888 RTL_PCI_MAX_RX_COUNT; 889 890 rx_remained_cnt--; 891 rtl_write_word(rtlpriv, 0x3B4, 892 rtlpci->rx_ring[hw_queue].next_rx_rp); 893 } 894 if (((rtlpriv->link_info.num_rx_inperiod + 895 rtlpriv->link_info.num_tx_inperiod) > 8) || 896 rtlpriv->link_info.num_rx_inperiod > 2) 897 rtl_lps_leave(hw); 898 skb = new_skb; 899 no_new: 900 if (rtlpriv->use_new_trx_flow) { 901 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 902 rxring_idx, 903 rtlpci->rx_ring[rxring_idx].idx); 904 } else { 905 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 906 rxring_idx, 907 rtlpci->rx_ring[rxring_idx].idx); 908 if (rtlpci->rx_ring[rxring_idx].idx == 909 rtlpci->rxringcount - 1) 910 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 911 false, 912 HW_DESC_RXERO, 913 (u8 *)&tmp_one); 914 } 915 rtlpci->rx_ring[rxring_idx].idx = 916 (rtlpci->rx_ring[rxring_idx].idx + 1) % 917 rtlpci->rxringcount; 918 } 919 } 920 921 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 922 { 923 struct ieee80211_hw *hw = dev_id; 924 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 925 struct rtl_priv *rtlpriv = rtl_priv(hw); 926 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 927 unsigned long flags; 928 struct rtl_int intvec = {0}; 929 930 irqreturn_t ret = IRQ_HANDLED; 931 932 if (rtlpci->irq_enabled == 0) 933 return ret; 934 935 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 936 rtlpriv->cfg->ops->disable_interrupt(hw); 937 938 /*read ISR: 4/8bytes */ 939 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 940 941 /*Shared IRQ or HW disappeared */ 942 if (!intvec.inta || intvec.inta == 0xffff) 943 goto done; 944 945 /*<1> beacon related */ 946 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 947 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 948 "beacon ok interrupt!\n"); 949 950 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 951 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 952 "beacon err interrupt!\n"); 953 954 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 955 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 956 957 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 958 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 959 "prepare beacon for interrupt!\n"); 960 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 961 } 962 963 /*<2> Tx related */ 964 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 965 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 966 967 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 968 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 969 "Manage ok interrupt!\n"); 970 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 971 } 972 973 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 974 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 975 "HIGH_QUEUE ok interrupt!\n"); 976 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 977 } 978 979 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 980 rtlpriv->link_info.num_tx_inperiod++; 981 982 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 983 "BK Tx OK interrupt!\n"); 984 _rtl_pci_tx_isr(hw, BK_QUEUE); 985 } 986 987 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 988 rtlpriv->link_info.num_tx_inperiod++; 989 990 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 991 "BE TX OK interrupt!\n"); 992 _rtl_pci_tx_isr(hw, BE_QUEUE); 993 } 994 995 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 996 rtlpriv->link_info.num_tx_inperiod++; 997 998 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 999 "VI TX OK interrupt!\n"); 1000 _rtl_pci_tx_isr(hw, VI_QUEUE); 1001 } 1002 1003 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 1004 rtlpriv->link_info.num_tx_inperiod++; 1005 1006 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1007 "Vo TX OK interrupt!\n"); 1008 _rtl_pci_tx_isr(hw, VO_QUEUE); 1009 } 1010 1011 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 1012 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 1013 rtlpriv->link_info.num_tx_inperiod++; 1014 1015 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1016 "H2C TX OK interrupt!\n"); 1017 _rtl_pci_tx_isr(hw, H2C_QUEUE); 1018 } 1019 } 1020 1021 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1022 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1023 rtlpriv->link_info.num_tx_inperiod++; 1024 1025 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1026 "CMD TX OK interrupt!\n"); 1027 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1028 } 1029 } 1030 1031 /*<3> Rx related */ 1032 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1033 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1034 _rtl_pci_rx_interrupt(hw); 1035 } 1036 1037 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1038 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1039 "rx descriptor unavailable!\n"); 1040 _rtl_pci_rx_interrupt(hw); 1041 } 1042 1043 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1044 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1045 _rtl_pci_rx_interrupt(hw); 1046 } 1047 1048 /*<4> fw related*/ 1049 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1050 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1051 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1052 "firmware interrupt!\n"); 1053 queue_delayed_work(rtlpriv->works.rtl_wq, 1054 &rtlpriv->works.fwevt_wq, 0); 1055 } 1056 } 1057 1058 /*<5> hsisr related*/ 1059 /* Only 8188EE & 8723BE Supported. 1060 * If Other ICs Come in, System will corrupt, 1061 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1062 * are not initialized 1063 */ 1064 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1065 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1066 if (unlikely(intvec.inta & 1067 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1068 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1069 "hsisr interrupt!\n"); 1070 _rtl_pci_hs_interrupt(hw); 1071 } 1072 } 1073 1074 if (rtlpriv->rtlhal.earlymode_enable) 1075 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1076 1077 done: 1078 rtlpriv->cfg->ops->enable_interrupt(hw); 1079 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1080 return ret; 1081 } 1082 1083 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) 1084 { 1085 _rtl_pci_tx_chk_waitq(hw); 1086 } 1087 1088 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 1089 { 1090 struct rtl_priv *rtlpriv = rtl_priv(hw); 1091 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1092 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1093 struct rtl8192_tx_ring *ring = NULL; 1094 struct ieee80211_hdr *hdr = NULL; 1095 struct ieee80211_tx_info *info = NULL; 1096 struct sk_buff *pskb = NULL; 1097 struct rtl_tx_desc *pdesc = NULL; 1098 struct rtl_tcb_desc tcb_desc; 1099 /*This is for new trx flow*/ 1100 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1101 u8 temp_one = 1; 1102 u8 *entry; 1103 1104 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1105 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1106 pskb = __skb_dequeue(&ring->queue); 1107 if (rtlpriv->use_new_trx_flow) 1108 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1109 else 1110 entry = (u8 *)(&ring->desc[ring->idx]); 1111 if (pskb) { 1112 pci_unmap_single(rtlpci->pdev, 1113 rtlpriv->cfg->ops->get_desc( 1114 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1115 pskb->len, PCI_DMA_TODEVICE); 1116 kfree_skb(pskb); 1117 } 1118 1119 /*NB: the beacon data buffer must be 32-bit aligned. */ 1120 pskb = ieee80211_beacon_get(hw, mac->vif); 1121 if (!pskb) 1122 return; 1123 hdr = rtl_get_hdr(pskb); 1124 info = IEEE80211_SKB_CB(pskb); 1125 pdesc = &ring->desc[0]; 1126 if (rtlpriv->use_new_trx_flow) 1127 pbuffer_desc = &ring->buffer_desc[0]; 1128 1129 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1130 (u8 *)pbuffer_desc, info, NULL, pskb, 1131 BEACON_QUEUE, &tcb_desc); 1132 1133 __skb_queue_tail(&ring->queue, pskb); 1134 1135 if (rtlpriv->use_new_trx_flow) { 1136 temp_one = 4; 1137 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1138 HW_DESC_OWN, (u8 *)&temp_one); 1139 } else { 1140 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1141 &temp_one); 1142 } 1143 } 1144 1145 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1146 { 1147 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1148 struct rtl_priv *rtlpriv = rtl_priv(hw); 1149 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1150 u8 i; 1151 u16 desc_num; 1152 1153 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1154 desc_num = TX_DESC_NUM_92E; 1155 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1156 desc_num = TX_DESC_NUM_8822B; 1157 else 1158 desc_num = RT_TXDESC_NUM; 1159 1160 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1161 rtlpci->txringcount[i] = desc_num; 1162 1163 /*we just alloc 2 desc for beacon queue, 1164 *because we just need first desc in hw beacon. 1165 */ 1166 rtlpci->txringcount[BEACON_QUEUE] = 2; 1167 1168 /*BE queue need more descriptor for performance 1169 *consideration or, No more tx desc will happen, 1170 *and may cause mac80211 mem leakage. 1171 */ 1172 if (!rtl_priv(hw)->use_new_trx_flow) 1173 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1174 1175 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1176 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1177 } 1178 1179 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1180 struct pci_dev *pdev) 1181 { 1182 struct rtl_priv *rtlpriv = rtl_priv(hw); 1183 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1184 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1185 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1186 1187 rtlpci->up_first_time = true; 1188 rtlpci->being_init_adapter = false; 1189 1190 rtlhal->hw = hw; 1191 rtlpci->pdev = pdev; 1192 1193 /*Tx/Rx related var */ 1194 _rtl_pci_init_trx_var(hw); 1195 1196 /*IBSS*/ 1197 mac->beacon_interval = 100; 1198 1199 /*AMPDU*/ 1200 mac->min_space_cfg = 0; 1201 mac->max_mss_density = 0; 1202 /*set sane AMPDU defaults */ 1203 mac->current_ampdu_density = 7; 1204 mac->current_ampdu_factor = 3; 1205 1206 /*Retry Limit*/ 1207 mac->retry_short = 7; 1208 mac->retry_long = 7; 1209 1210 /*QOS*/ 1211 rtlpci->acm_method = EACMWAY2_SW; 1212 1213 /*task */ 1214 tasklet_init(&rtlpriv->works.irq_tasklet, 1215 (void (*)(unsigned long))_rtl_pci_irq_tasklet, 1216 (unsigned long)hw); 1217 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1218 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1219 (unsigned long)hw); 1220 INIT_WORK(&rtlpriv->works.lps_change_work, 1221 rtl_lps_change_work_callback); 1222 } 1223 1224 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1225 unsigned int prio, unsigned int entries) 1226 { 1227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1228 struct rtl_priv *rtlpriv = rtl_priv(hw); 1229 struct rtl_tx_buffer_desc *buffer_desc; 1230 struct rtl_tx_desc *desc; 1231 dma_addr_t buffer_desc_dma, desc_dma; 1232 u32 nextdescaddress; 1233 int i; 1234 1235 /* alloc tx buffer desc for new trx flow*/ 1236 if (rtlpriv->use_new_trx_flow) { 1237 buffer_desc = 1238 pci_zalloc_consistent(rtlpci->pdev, 1239 sizeof(*buffer_desc) * entries, 1240 &buffer_desc_dma); 1241 1242 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1243 pr_err("Cannot allocate TX ring (prio = %d)\n", 1244 prio); 1245 return -ENOMEM; 1246 } 1247 1248 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1249 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1250 1251 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1252 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1253 } 1254 1255 /* alloc dma for this ring */ 1256 desc = pci_zalloc_consistent(rtlpci->pdev, 1257 sizeof(*desc) * entries, &desc_dma); 1258 1259 if (!desc || (unsigned long)desc & 0xFF) { 1260 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1261 return -ENOMEM; 1262 } 1263 1264 rtlpci->tx_ring[prio].desc = desc; 1265 rtlpci->tx_ring[prio].dma = desc_dma; 1266 1267 rtlpci->tx_ring[prio].idx = 0; 1268 rtlpci->tx_ring[prio].entries = entries; 1269 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1270 1271 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1272 prio, desc); 1273 1274 /* init every desc in this ring */ 1275 if (!rtlpriv->use_new_trx_flow) { 1276 for (i = 0; i < entries; i++) { 1277 nextdescaddress = (u32)desc_dma + 1278 ((i + 1) % entries) * 1279 sizeof(*desc); 1280 1281 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1282 true, 1283 HW_DESC_TX_NEXTDESC_ADDR, 1284 (u8 *)&nextdescaddress); 1285 } 1286 } 1287 return 0; 1288 } 1289 1290 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1291 { 1292 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1293 struct rtl_priv *rtlpriv = rtl_priv(hw); 1294 int i; 1295 1296 if (rtlpriv->use_new_trx_flow) { 1297 struct rtl_rx_buffer_desc *entry = NULL; 1298 /* alloc dma for this ring */ 1299 rtlpci->rx_ring[rxring_idx].buffer_desc = 1300 pci_zalloc_consistent(rtlpci->pdev, 1301 sizeof(*rtlpci->rx_ring[rxring_idx]. 1302 buffer_desc) * 1303 rtlpci->rxringcount, 1304 &rtlpci->rx_ring[rxring_idx].dma); 1305 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1306 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1307 pr_err("Cannot allocate RX ring\n"); 1308 return -ENOMEM; 1309 } 1310 1311 /* init every desc in this ring */ 1312 rtlpci->rx_ring[rxring_idx].idx = 0; 1313 for (i = 0; i < rtlpci->rxringcount; i++) { 1314 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1315 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1316 rxring_idx, i)) 1317 return -ENOMEM; 1318 } 1319 } else { 1320 struct rtl_rx_desc *entry = NULL; 1321 u8 tmp_one = 1; 1322 /* alloc dma for this ring */ 1323 rtlpci->rx_ring[rxring_idx].desc = 1324 pci_zalloc_consistent(rtlpci->pdev, 1325 sizeof(*rtlpci->rx_ring[rxring_idx]. 1326 desc) * rtlpci->rxringcount, 1327 &rtlpci->rx_ring[rxring_idx].dma); 1328 if (!rtlpci->rx_ring[rxring_idx].desc || 1329 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1330 pr_err("Cannot allocate RX ring\n"); 1331 return -ENOMEM; 1332 } 1333 1334 /* init every desc in this ring */ 1335 rtlpci->rx_ring[rxring_idx].idx = 0; 1336 1337 for (i = 0; i < rtlpci->rxringcount; i++) { 1338 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1339 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1340 rxring_idx, i)) 1341 return -ENOMEM; 1342 } 1343 1344 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1345 HW_DESC_RXERO, &tmp_one); 1346 } 1347 return 0; 1348 } 1349 1350 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1351 unsigned int prio) 1352 { 1353 struct rtl_priv *rtlpriv = rtl_priv(hw); 1354 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1355 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1356 1357 /* free every desc in this ring */ 1358 while (skb_queue_len(&ring->queue)) { 1359 u8 *entry; 1360 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1361 1362 if (rtlpriv->use_new_trx_flow) 1363 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1364 else 1365 entry = (u8 *)(&ring->desc[ring->idx]); 1366 1367 pci_unmap_single(rtlpci->pdev, 1368 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1369 true, 1370 HW_DESC_TXBUFF_ADDR), 1371 skb->len, PCI_DMA_TODEVICE); 1372 kfree_skb(skb); 1373 ring->idx = (ring->idx + 1) % ring->entries; 1374 } 1375 1376 /* free dma of this ring */ 1377 pci_free_consistent(rtlpci->pdev, 1378 sizeof(*ring->desc) * ring->entries, 1379 ring->desc, ring->dma); 1380 ring->desc = NULL; 1381 if (rtlpriv->use_new_trx_flow) { 1382 pci_free_consistent(rtlpci->pdev, 1383 sizeof(*ring->buffer_desc) * ring->entries, 1384 ring->buffer_desc, ring->buffer_desc_dma); 1385 ring->buffer_desc = NULL; 1386 } 1387 } 1388 1389 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1390 { 1391 struct rtl_priv *rtlpriv = rtl_priv(hw); 1392 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1393 int i; 1394 1395 /* free every desc in this ring */ 1396 for (i = 0; i < rtlpci->rxringcount; i++) { 1397 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1398 1399 if (!skb) 1400 continue; 1401 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1402 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1403 kfree_skb(skb); 1404 } 1405 1406 /* free dma of this ring */ 1407 if (rtlpriv->use_new_trx_flow) { 1408 pci_free_consistent(rtlpci->pdev, 1409 sizeof(*rtlpci->rx_ring[rxring_idx]. 1410 buffer_desc) * rtlpci->rxringcount, 1411 rtlpci->rx_ring[rxring_idx].buffer_desc, 1412 rtlpci->rx_ring[rxring_idx].dma); 1413 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1414 } else { 1415 pci_free_consistent(rtlpci->pdev, 1416 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1417 rtlpci->rxringcount, 1418 rtlpci->rx_ring[rxring_idx].desc, 1419 rtlpci->rx_ring[rxring_idx].dma); 1420 rtlpci->rx_ring[rxring_idx].desc = NULL; 1421 } 1422 } 1423 1424 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1425 { 1426 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1427 int ret; 1428 int i, rxring_idx; 1429 1430 /* rxring_idx 0:RX_MPDU_QUEUE 1431 * rxring_idx 1:RX_CMD_QUEUE 1432 */ 1433 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1434 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1435 if (ret) 1436 return ret; 1437 } 1438 1439 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1440 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1441 if (ret) 1442 goto err_free_rings; 1443 } 1444 1445 return 0; 1446 1447 err_free_rings: 1448 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1449 _rtl_pci_free_rx_ring(hw, rxring_idx); 1450 1451 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1452 if (rtlpci->tx_ring[i].desc || 1453 rtlpci->tx_ring[i].buffer_desc) 1454 _rtl_pci_free_tx_ring(hw, i); 1455 1456 return 1; 1457 } 1458 1459 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1460 { 1461 u32 i, rxring_idx; 1462 1463 /*free rx rings */ 1464 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1465 _rtl_pci_free_rx_ring(hw, rxring_idx); 1466 1467 /*free tx rings */ 1468 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1469 _rtl_pci_free_tx_ring(hw, i); 1470 1471 return 0; 1472 } 1473 1474 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1475 { 1476 struct rtl_priv *rtlpriv = rtl_priv(hw); 1477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1478 int i, rxring_idx; 1479 unsigned long flags; 1480 u8 tmp_one = 1; 1481 u32 bufferaddress; 1482 /* rxring_idx 0:RX_MPDU_QUEUE */ 1483 /* rxring_idx 1:RX_CMD_QUEUE */ 1484 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1485 /* force the rx_ring[RX_MPDU_QUEUE/ 1486 * RX_CMD_QUEUE].idx to the first one 1487 *new trx flow, do nothing 1488 */ 1489 if (!rtlpriv->use_new_trx_flow && 1490 rtlpci->rx_ring[rxring_idx].desc) { 1491 struct rtl_rx_desc *entry = NULL; 1492 1493 rtlpci->rx_ring[rxring_idx].idx = 0; 1494 for (i = 0; i < rtlpci->rxringcount; i++) { 1495 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1496 bufferaddress = 1497 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1498 false, HW_DESC_RXBUFF_ADDR); 1499 memset((u8 *)entry, 0, 1500 sizeof(*rtlpci->rx_ring 1501 [rxring_idx].desc));/*clear one entry*/ 1502 if (rtlpriv->use_new_trx_flow) { 1503 rtlpriv->cfg->ops->set_desc(hw, 1504 (u8 *)entry, false, 1505 HW_DESC_RX_PREPARE, 1506 (u8 *)&bufferaddress); 1507 } else { 1508 rtlpriv->cfg->ops->set_desc(hw, 1509 (u8 *)entry, false, 1510 HW_DESC_RXBUFF_ADDR, 1511 (u8 *)&bufferaddress); 1512 rtlpriv->cfg->ops->set_desc(hw, 1513 (u8 *)entry, false, 1514 HW_DESC_RXPKT_LEN, 1515 (u8 *)&rtlpci->rxbuffersize); 1516 rtlpriv->cfg->ops->set_desc(hw, 1517 (u8 *)entry, false, 1518 HW_DESC_RXOWN, 1519 (u8 *)&tmp_one); 1520 } 1521 } 1522 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1523 HW_DESC_RXERO, (u8 *)&tmp_one); 1524 } 1525 rtlpci->rx_ring[rxring_idx].idx = 0; 1526 } 1527 1528 /*after reset, release previous pending packet, 1529 *and force the tx idx to the first one 1530 */ 1531 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1532 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1533 if (rtlpci->tx_ring[i].desc || 1534 rtlpci->tx_ring[i].buffer_desc) { 1535 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1536 1537 while (skb_queue_len(&ring->queue)) { 1538 u8 *entry; 1539 struct sk_buff *skb = 1540 __skb_dequeue(&ring->queue); 1541 if (rtlpriv->use_new_trx_flow) 1542 entry = (u8 *)(&ring->buffer_desc 1543 [ring->idx]); 1544 else 1545 entry = (u8 *)(&ring->desc[ring->idx]); 1546 1547 pci_unmap_single(rtlpci->pdev, 1548 rtlpriv->cfg->ops-> 1549 get_desc(hw, (u8 *) 1550 entry, 1551 true, 1552 HW_DESC_TXBUFF_ADDR), 1553 skb->len, PCI_DMA_TODEVICE); 1554 dev_kfree_skb_irq(skb); 1555 ring->idx = (ring->idx + 1) % ring->entries; 1556 } 1557 1558 if (rtlpriv->use_new_trx_flow) { 1559 rtlpci->tx_ring[i].cur_tx_rp = 0; 1560 rtlpci->tx_ring[i].cur_tx_wp = 0; 1561 } 1562 1563 ring->idx = 0; 1564 ring->entries = rtlpci->txringcount[i]; 1565 } 1566 } 1567 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1568 1569 return 0; 1570 } 1571 1572 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1573 struct ieee80211_sta *sta, 1574 struct sk_buff *skb) 1575 { 1576 struct rtl_priv *rtlpriv = rtl_priv(hw); 1577 struct rtl_sta_info *sta_entry = NULL; 1578 u8 tid = rtl_get_tid(skb); 1579 __le16 fc = rtl_get_fc(skb); 1580 1581 if (!sta) 1582 return false; 1583 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1584 1585 if (!rtlpriv->rtlhal.earlymode_enable) 1586 return false; 1587 if (ieee80211_is_nullfunc(fc)) 1588 return false; 1589 if (ieee80211_is_qos_nullfunc(fc)) 1590 return false; 1591 if (ieee80211_is_pspoll(fc)) 1592 return false; 1593 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1594 return false; 1595 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1596 return false; 1597 if (tid > 7) 1598 return false; 1599 1600 /* maybe every tid should be checked */ 1601 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1602 return false; 1603 1604 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1605 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1606 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1607 1608 return true; 1609 } 1610 1611 static int rtl_pci_tx(struct ieee80211_hw *hw, 1612 struct ieee80211_sta *sta, 1613 struct sk_buff *skb, 1614 struct rtl_tcb_desc *ptcb_desc) 1615 { 1616 struct rtl_priv *rtlpriv = rtl_priv(hw); 1617 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1618 struct rtl8192_tx_ring *ring; 1619 struct rtl_tx_desc *pdesc; 1620 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1621 u16 idx; 1622 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1623 unsigned long flags; 1624 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1625 __le16 fc = rtl_get_fc(skb); 1626 u8 *pda_addr = hdr->addr1; 1627 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1628 u8 own; 1629 u8 temp_one = 1; 1630 1631 if (ieee80211_is_mgmt(fc)) 1632 rtl_tx_mgmt_proc(hw, skb); 1633 1634 if (rtlpriv->psc.sw_ps_enabled) { 1635 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1636 !ieee80211_has_pm(fc)) 1637 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1638 } 1639 1640 rtl_action_proc(hw, skb, true); 1641 1642 if (is_multicast_ether_addr(pda_addr)) 1643 rtlpriv->stats.txbytesmulticast += skb->len; 1644 else if (is_broadcast_ether_addr(pda_addr)) 1645 rtlpriv->stats.txbytesbroadcast += skb->len; 1646 else 1647 rtlpriv->stats.txbytesunicast += skb->len; 1648 1649 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1650 ring = &rtlpci->tx_ring[hw_queue]; 1651 if (hw_queue != BEACON_QUEUE) { 1652 if (rtlpriv->use_new_trx_flow) 1653 idx = ring->cur_tx_wp; 1654 else 1655 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1656 ring->entries; 1657 } else { 1658 idx = 0; 1659 } 1660 1661 pdesc = &ring->desc[idx]; 1662 if (rtlpriv->use_new_trx_flow) { 1663 ptx_bd_desc = &ring->buffer_desc[idx]; 1664 } else { 1665 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1666 true, HW_DESC_OWN); 1667 1668 if (own == 1 && hw_queue != BEACON_QUEUE) { 1669 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1670 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1671 hw_queue, ring->idx, idx, 1672 skb_queue_len(&ring->queue)); 1673 1674 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1675 flags); 1676 return skb->len; 1677 } 1678 } 1679 1680 if (rtlpriv->cfg->ops->get_available_desc && 1681 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1682 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1683 "get_available_desc fail\n"); 1684 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1685 return skb->len; 1686 } 1687 1688 if (ieee80211_is_data(fc)) 1689 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1690 1691 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1692 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1693 1694 __skb_queue_tail(&ring->queue, skb); 1695 1696 if (rtlpriv->use_new_trx_flow) { 1697 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1698 HW_DESC_OWN, &hw_queue); 1699 } else { 1700 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1701 HW_DESC_OWN, &temp_one); 1702 } 1703 1704 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1705 hw_queue != BEACON_QUEUE) { 1706 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1707 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1708 hw_queue, ring->idx, idx, 1709 skb_queue_len(&ring->queue)); 1710 1711 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1712 } 1713 1714 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1715 1716 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1717 1718 return 0; 1719 } 1720 1721 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1722 { 1723 struct rtl_priv *rtlpriv = rtl_priv(hw); 1724 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1725 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1726 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1727 u16 i = 0; 1728 int queue_id; 1729 struct rtl8192_tx_ring *ring; 1730 1731 if (mac->skip_scan) 1732 return; 1733 1734 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1735 u32 queue_len; 1736 1737 if (((queues >> queue_id) & 0x1) == 0) { 1738 queue_id--; 1739 continue; 1740 } 1741 ring = &pcipriv->dev.tx_ring[queue_id]; 1742 queue_len = skb_queue_len(&ring->queue); 1743 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1744 queue_id == TXCMD_QUEUE) { 1745 queue_id--; 1746 continue; 1747 } else { 1748 msleep(20); 1749 i++; 1750 } 1751 1752 /* we just wait 1s for all queues */ 1753 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1754 is_hal_stop(rtlhal) || i >= 200) 1755 return; 1756 } 1757 } 1758 1759 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1760 { 1761 struct rtl_priv *rtlpriv = rtl_priv(hw); 1762 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1763 1764 _rtl_pci_deinit_trx_ring(hw); 1765 1766 synchronize_irq(rtlpci->pdev->irq); 1767 tasklet_kill(&rtlpriv->works.irq_tasklet); 1768 cancel_work_sync(&rtlpriv->works.lps_change_work); 1769 1770 flush_workqueue(rtlpriv->works.rtl_wq); 1771 destroy_workqueue(rtlpriv->works.rtl_wq); 1772 } 1773 1774 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1775 { 1776 int err; 1777 1778 _rtl_pci_init_struct(hw, pdev); 1779 1780 err = _rtl_pci_init_trx_ring(hw); 1781 if (err) { 1782 pr_err("tx ring initialization failed\n"); 1783 return err; 1784 } 1785 1786 return 0; 1787 } 1788 1789 static int rtl_pci_start(struct ieee80211_hw *hw) 1790 { 1791 struct rtl_priv *rtlpriv = rtl_priv(hw); 1792 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1793 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1794 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1795 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1796 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1797 1798 int err; 1799 1800 rtl_pci_reset_trx_ring(hw); 1801 1802 rtlpci->driver_is_goingto_unload = false; 1803 if (rtlpriv->cfg->ops->get_btc_status && 1804 rtlpriv->cfg->ops->get_btc_status()) { 1805 rtlpriv->btcoexist.btc_info.ap_num = 36; 1806 btc_ops->btc_init_variables(rtlpriv); 1807 btc_ops->btc_init_hal_vars(rtlpriv); 1808 } else if (btc_ops) { 1809 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1810 } 1811 1812 err = rtlpriv->cfg->ops->hw_init(hw); 1813 if (err) { 1814 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1815 "Failed to config hardware!\n"); 1816 return err; 1817 } 1818 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1819 &rtlmac->retry_long); 1820 1821 rtlpriv->cfg->ops->enable_interrupt(hw); 1822 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1823 1824 rtl_init_rx_config(hw); 1825 1826 /*should be after adapter start and interrupt enable. */ 1827 set_hal_start(rtlhal); 1828 1829 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1830 1831 rtlpci->up_first_time = false; 1832 1833 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1834 return 0; 1835 } 1836 1837 static void rtl_pci_stop(struct ieee80211_hw *hw) 1838 { 1839 struct rtl_priv *rtlpriv = rtl_priv(hw); 1840 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1841 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1842 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1843 unsigned long flags; 1844 u8 rf_timeout = 0; 1845 1846 if (rtlpriv->cfg->ops->get_btc_status()) 1847 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1848 1849 if (rtlpriv->btcoexist.btc_ops) 1850 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1851 1852 /*should be before disable interrupt&adapter 1853 *and will do it immediately. 1854 */ 1855 set_hal_stop(rtlhal); 1856 1857 rtlpci->driver_is_goingto_unload = true; 1858 rtlpriv->cfg->ops->disable_interrupt(hw); 1859 cancel_work_sync(&rtlpriv->works.lps_change_work); 1860 1861 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1862 while (ppsc->rfchange_inprogress) { 1863 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1864 if (rf_timeout > 100) { 1865 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1866 break; 1867 } 1868 mdelay(1); 1869 rf_timeout++; 1870 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1871 } 1872 ppsc->rfchange_inprogress = true; 1873 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1874 1875 rtlpriv->cfg->ops->hw_disable(hw); 1876 /* some things are not needed if firmware not available */ 1877 if (!rtlpriv->max_fw_size) 1878 return; 1879 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1880 1881 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1882 ppsc->rfchange_inprogress = false; 1883 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1884 1885 rtl_pci_enable_aspm(hw); 1886 } 1887 1888 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1889 struct ieee80211_hw *hw) 1890 { 1891 struct rtl_priv *rtlpriv = rtl_priv(hw); 1892 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1893 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1894 struct pci_dev *bridge_pdev = pdev->bus->self; 1895 u16 venderid; 1896 u16 deviceid; 1897 u8 revisionid; 1898 u16 irqline; 1899 u8 tmp; 1900 1901 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1902 venderid = pdev->vendor; 1903 deviceid = pdev->device; 1904 pci_read_config_byte(pdev, 0x8, &revisionid); 1905 pci_read_config_word(pdev, 0x3C, &irqline); 1906 1907 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1908 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1909 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1910 * the correct driver is r8192e_pci, thus this routine should 1911 * return false. 1912 */ 1913 if (deviceid == RTL_PCI_8192SE_DID && 1914 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1915 return false; 1916 1917 if (deviceid == RTL_PCI_8192_DID || 1918 deviceid == RTL_PCI_0044_DID || 1919 deviceid == RTL_PCI_0047_DID || 1920 deviceid == RTL_PCI_8192SE_DID || 1921 deviceid == RTL_PCI_8174_DID || 1922 deviceid == RTL_PCI_8173_DID || 1923 deviceid == RTL_PCI_8172_DID || 1924 deviceid == RTL_PCI_8171_DID) { 1925 switch (revisionid) { 1926 case RTL_PCI_REVISION_ID_8192PCIE: 1927 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1928 "8192 PCI-E is found - vid/did=%x/%x\n", 1929 venderid, deviceid); 1930 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1931 return false; 1932 case RTL_PCI_REVISION_ID_8192SE: 1933 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1934 "8192SE is found - vid/did=%x/%x\n", 1935 venderid, deviceid); 1936 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1937 break; 1938 default: 1939 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1940 "Err: Unknown device - vid/did=%x/%x\n", 1941 venderid, deviceid); 1942 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1943 break; 1944 } 1945 } else if (deviceid == RTL_PCI_8723AE_DID) { 1946 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1947 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1948 "8723AE PCI-E is found - vid/did=%x/%x\n", 1949 venderid, deviceid); 1950 } else if (deviceid == RTL_PCI_8192CET_DID || 1951 deviceid == RTL_PCI_8192CE_DID || 1952 deviceid == RTL_PCI_8191CE_DID || 1953 deviceid == RTL_PCI_8188CE_DID) { 1954 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1955 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1956 "8192C PCI-E is found - vid/did=%x/%x\n", 1957 venderid, deviceid); 1958 } else if (deviceid == RTL_PCI_8192DE_DID || 1959 deviceid == RTL_PCI_8192DE_DID2) { 1960 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1961 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1962 "8192D PCI-E is found - vid/did=%x/%x\n", 1963 venderid, deviceid); 1964 } else if (deviceid == RTL_PCI_8188EE_DID) { 1965 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1966 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1967 "Find adapter, Hardware type is 8188EE\n"); 1968 } else if (deviceid == RTL_PCI_8723BE_DID) { 1969 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1970 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1971 "Find adapter, Hardware type is 8723BE\n"); 1972 } else if (deviceid == RTL_PCI_8192EE_DID) { 1973 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1974 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1975 "Find adapter, Hardware type is 8192EE\n"); 1976 } else if (deviceid == RTL_PCI_8821AE_DID) { 1977 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1978 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1979 "Find adapter, Hardware type is 8821AE\n"); 1980 } else if (deviceid == RTL_PCI_8812AE_DID) { 1981 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1982 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1983 "Find adapter, Hardware type is 8812AE\n"); 1984 } else if (deviceid == RTL_PCI_8822BE_DID) { 1985 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1986 rtlhal->bandset = BAND_ON_BOTH; 1987 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1988 "Find adapter, Hardware type is 8822BE\n"); 1989 } else { 1990 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1991 "Err: Unknown device - vid/did=%x/%x\n", 1992 venderid, deviceid); 1993 1994 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1995 } 1996 1997 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1998 if (revisionid == 0 || revisionid == 1) { 1999 if (revisionid == 0) { 2000 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2001 "Find 92DE MAC0\n"); 2002 rtlhal->interfaceindex = 0; 2003 } else if (revisionid == 1) { 2004 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2005 "Find 92DE MAC1\n"); 2006 rtlhal->interfaceindex = 1; 2007 } 2008 } else { 2009 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2010 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 2011 venderid, deviceid, revisionid); 2012 rtlhal->interfaceindex = 0; 2013 } 2014 } 2015 2016 switch (rtlhal->hw_type) { 2017 case HARDWARE_TYPE_RTL8192EE: 2018 case HARDWARE_TYPE_RTL8822BE: 2019 /* use new trx flow */ 2020 rtlpriv->use_new_trx_flow = true; 2021 break; 2022 2023 default: 2024 rtlpriv->use_new_trx_flow = false; 2025 break; 2026 } 2027 2028 /*find bus info */ 2029 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2030 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2031 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2032 2033 /*find bridge info */ 2034 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2035 /* some ARM have no bridge_pdev and will crash here 2036 * so we should check if bridge_pdev is NULL 2037 */ 2038 if (bridge_pdev) { 2039 /*find bridge info if available */ 2040 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2041 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2042 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2043 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2044 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2045 "Pci Bridge Vendor is found index: %d\n", 2046 tmp); 2047 break; 2048 } 2049 } 2050 } 2051 2052 if (pcipriv->ndis_adapter.pcibridge_vendor != 2053 PCI_BRIDGE_VENDOR_UNKNOWN) { 2054 pcipriv->ndis_adapter.pcibridge_busnum = 2055 bridge_pdev->bus->number; 2056 pcipriv->ndis_adapter.pcibridge_devnum = 2057 PCI_SLOT(bridge_pdev->devfn); 2058 pcipriv->ndis_adapter.pcibridge_funcnum = 2059 PCI_FUNC(bridge_pdev->devfn); 2060 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2061 pci_pcie_cap(bridge_pdev); 2062 pcipriv->ndis_adapter.num4bytes = 2063 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2064 2065 rtl_pci_get_linkcontrol_field(hw); 2066 2067 if (pcipriv->ndis_adapter.pcibridge_vendor == 2068 PCI_BRIDGE_VENDOR_AMD) { 2069 pcipriv->ndis_adapter.amd_l1_patch = 2070 rtl_pci_get_amd_l1_patch(hw); 2071 } 2072 } 2073 2074 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2075 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2076 pcipriv->ndis_adapter.busnumber, 2077 pcipriv->ndis_adapter.devnumber, 2078 pcipriv->ndis_adapter.funcnumber, 2079 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2080 2081 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2082 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2083 pcipriv->ndis_adapter.pcibridge_busnum, 2084 pcipriv->ndis_adapter.pcibridge_devnum, 2085 pcipriv->ndis_adapter.pcibridge_funcnum, 2086 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2087 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2088 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2089 pcipriv->ndis_adapter.amd_l1_patch); 2090 2091 rtl_pci_parse_configuration(pdev, hw); 2092 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2093 2094 return true; 2095 } 2096 2097 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2098 { 2099 struct rtl_priv *rtlpriv = rtl_priv(hw); 2100 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2101 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2102 int ret; 2103 2104 ret = pci_enable_msi(rtlpci->pdev); 2105 if (ret < 0) 2106 return ret; 2107 2108 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2109 IRQF_SHARED, KBUILD_MODNAME, hw); 2110 if (ret < 0) { 2111 pci_disable_msi(rtlpci->pdev); 2112 return ret; 2113 } 2114 2115 rtlpci->using_msi = true; 2116 2117 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2118 "MSI Interrupt Mode!\n"); 2119 return 0; 2120 } 2121 2122 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2123 { 2124 struct rtl_priv *rtlpriv = rtl_priv(hw); 2125 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2126 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2127 int ret; 2128 2129 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2130 IRQF_SHARED, KBUILD_MODNAME, hw); 2131 if (ret < 0) 2132 return ret; 2133 2134 rtlpci->using_msi = false; 2135 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2136 "Pin-based Interrupt Mode!\n"); 2137 return 0; 2138 } 2139 2140 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2141 { 2142 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2143 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2144 int ret; 2145 2146 if (rtlpci->msi_support) { 2147 ret = rtl_pci_intr_mode_msi(hw); 2148 if (ret < 0) 2149 ret = rtl_pci_intr_mode_legacy(hw); 2150 } else { 2151 ret = rtl_pci_intr_mode_legacy(hw); 2152 } 2153 return ret; 2154 } 2155 2156 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2157 { 2158 u8 value; 2159 2160 pci_read_config_byte(pdev, 0x719, &value); 2161 2162 /* 0x719 Bit5 is DMA64 bit fetch. */ 2163 if (dma64) 2164 value |= BIT(5); 2165 else 2166 value &= ~BIT(5); 2167 2168 pci_write_config_byte(pdev, 0x719, value); 2169 } 2170 2171 int rtl_pci_probe(struct pci_dev *pdev, 2172 const struct pci_device_id *id) 2173 { 2174 struct ieee80211_hw *hw = NULL; 2175 2176 struct rtl_priv *rtlpriv = NULL; 2177 struct rtl_pci_priv *pcipriv = NULL; 2178 struct rtl_pci *rtlpci; 2179 unsigned long pmem_start, pmem_len, pmem_flags; 2180 int err; 2181 2182 err = pci_enable_device(pdev); 2183 if (err) { 2184 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2185 pci_name(pdev)); 2186 return err; 2187 } 2188 2189 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2190 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2191 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 2192 WARN_ONCE(true, 2193 "Unable to obtain 64bit DMA for consistent allocations\n"); 2194 err = -ENOMEM; 2195 goto fail1; 2196 } 2197 2198 platform_enable_dma64(pdev, true); 2199 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2200 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2201 WARN_ONCE(true, 2202 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2203 err = -ENOMEM; 2204 goto fail1; 2205 } 2206 2207 platform_enable_dma64(pdev, false); 2208 } 2209 2210 pci_set_master(pdev); 2211 2212 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2213 sizeof(struct rtl_priv), &rtl_ops); 2214 if (!hw) { 2215 WARN_ONCE(true, 2216 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2217 err = -ENOMEM; 2218 goto fail1; 2219 } 2220 2221 SET_IEEE80211_DEV(hw, &pdev->dev); 2222 pci_set_drvdata(pdev, hw); 2223 2224 rtlpriv = hw->priv; 2225 rtlpriv->hw = hw; 2226 pcipriv = (void *)rtlpriv->priv; 2227 pcipriv->dev.pdev = pdev; 2228 init_completion(&rtlpriv->firmware_loading_complete); 2229 /*proximity init here*/ 2230 rtlpriv->proximity.proxim_on = false; 2231 2232 pcipriv = (void *)rtlpriv->priv; 2233 pcipriv->dev.pdev = pdev; 2234 2235 /* init cfg & intf_ops */ 2236 rtlpriv->rtlhal.interface = INTF_PCI; 2237 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2238 rtlpriv->intf_ops = &rtl_pci_ops; 2239 rtlpriv->glb_var = &rtl_global_var; 2240 rtl_efuse_ops_init(hw); 2241 2242 /* MEM map */ 2243 err = pci_request_regions(pdev, KBUILD_MODNAME); 2244 if (err) { 2245 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2246 goto fail1; 2247 } 2248 2249 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2250 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2251 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2252 2253 /*shared mem start */ 2254 rtlpriv->io.pci_mem_start = 2255 (unsigned long)pci_iomap(pdev, 2256 rtlpriv->cfg->bar_id, pmem_len); 2257 if (rtlpriv->io.pci_mem_start == 0) { 2258 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2259 err = -ENOMEM; 2260 goto fail2; 2261 } 2262 2263 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2264 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2265 pmem_start, pmem_len, pmem_flags, 2266 rtlpriv->io.pci_mem_start); 2267 2268 /* Disable Clk Request */ 2269 pci_write_config_byte(pdev, 0x81, 0); 2270 /* leave D3 mode */ 2271 pci_write_config_byte(pdev, 0x44, 0); 2272 pci_write_config_byte(pdev, 0x04, 0x06); 2273 pci_write_config_byte(pdev, 0x04, 0x07); 2274 2275 /* find adapter */ 2276 if (!_rtl_pci_find_adapter(pdev, hw)) { 2277 err = -ENODEV; 2278 goto fail2; 2279 } 2280 2281 /* Init IO handler */ 2282 _rtl_pci_io_handler_init(&pdev->dev, hw); 2283 2284 /*like read eeprom and so on */ 2285 rtlpriv->cfg->ops->read_eeprom_info(hw); 2286 2287 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2288 pr_err("Can't init_sw_vars\n"); 2289 err = -ENODEV; 2290 goto fail3; 2291 } 2292 rtlpriv->cfg->ops->init_sw_leds(hw); 2293 2294 /*aspm */ 2295 rtl_pci_init_aspm(hw); 2296 2297 /* Init mac80211 sw */ 2298 err = rtl_init_core(hw); 2299 if (err) { 2300 pr_err("Can't allocate sw for mac80211\n"); 2301 goto fail3; 2302 } 2303 2304 /* Init PCI sw */ 2305 err = rtl_pci_init(hw, pdev); 2306 if (err) { 2307 pr_err("Failed to init PCI\n"); 2308 goto fail3; 2309 } 2310 2311 err = ieee80211_register_hw(hw); 2312 if (err) { 2313 pr_err("Can't register mac80211 hw.\n"); 2314 err = -ENODEV; 2315 goto fail3; 2316 } 2317 rtlpriv->mac80211.mac80211_registered = 1; 2318 2319 /* add for debug */ 2320 rtl_debug_add_one(hw); 2321 2322 /*init rfkill */ 2323 rtl_init_rfkill(hw); /* Init PCI sw */ 2324 2325 rtlpci = rtl_pcidev(pcipriv); 2326 err = rtl_pci_intr_mode_decide(hw); 2327 if (err) { 2328 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2329 "%s: failed to register IRQ handler\n", 2330 wiphy_name(hw->wiphy)); 2331 goto fail3; 2332 } 2333 rtlpci->irq_alloc = 1; 2334 2335 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2336 return 0; 2337 2338 fail3: 2339 pci_set_drvdata(pdev, NULL); 2340 rtl_deinit_core(hw); 2341 2342 fail2: 2343 if (rtlpriv->io.pci_mem_start != 0) 2344 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2345 2346 pci_release_regions(pdev); 2347 complete(&rtlpriv->firmware_loading_complete); 2348 2349 fail1: 2350 if (hw) 2351 ieee80211_free_hw(hw); 2352 pci_disable_device(pdev); 2353 2354 return err; 2355 } 2356 EXPORT_SYMBOL(rtl_pci_probe); 2357 2358 void rtl_pci_disconnect(struct pci_dev *pdev) 2359 { 2360 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2361 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2362 struct rtl_priv *rtlpriv = rtl_priv(hw); 2363 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2364 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2365 2366 /* just in case driver is removed before firmware callback */ 2367 wait_for_completion(&rtlpriv->firmware_loading_complete); 2368 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2369 2370 /* remove form debug */ 2371 rtl_debug_remove_one(hw); 2372 2373 /*ieee80211_unregister_hw will call ops_stop */ 2374 if (rtlmac->mac80211_registered == 1) { 2375 ieee80211_unregister_hw(hw); 2376 rtlmac->mac80211_registered = 0; 2377 } else { 2378 rtl_deinit_deferred_work(hw); 2379 rtlpriv->intf_ops->adapter_stop(hw); 2380 } 2381 rtlpriv->cfg->ops->disable_interrupt(hw); 2382 2383 /*deinit rfkill */ 2384 rtl_deinit_rfkill(hw); 2385 2386 rtl_pci_deinit(hw); 2387 rtl_deinit_core(hw); 2388 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2389 2390 if (rtlpci->irq_alloc) { 2391 free_irq(rtlpci->pdev->irq, hw); 2392 rtlpci->irq_alloc = 0; 2393 } 2394 2395 if (rtlpci->using_msi) 2396 pci_disable_msi(rtlpci->pdev); 2397 2398 list_del(&rtlpriv->list); 2399 if (rtlpriv->io.pci_mem_start != 0) { 2400 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2401 pci_release_regions(pdev); 2402 } 2403 2404 pci_disable_device(pdev); 2405 2406 rtl_pci_disable_aspm(hw); 2407 2408 pci_set_drvdata(pdev, NULL); 2409 2410 ieee80211_free_hw(hw); 2411 } 2412 EXPORT_SYMBOL(rtl_pci_disconnect); 2413 2414 #ifdef CONFIG_PM_SLEEP 2415 /*************************************** 2416 * kernel pci power state define: 2417 * PCI_D0 ((pci_power_t __force) 0) 2418 * PCI_D1 ((pci_power_t __force) 1) 2419 * PCI_D2 ((pci_power_t __force) 2) 2420 * PCI_D3hot ((pci_power_t __force) 3) 2421 * PCI_D3cold ((pci_power_t __force) 4) 2422 * PCI_UNKNOWN ((pci_power_t __force) 5) 2423 2424 * This function is called when system 2425 * goes into suspend state mac80211 will 2426 * call rtl_mac_stop() from the mac80211 2427 * suspend function first, So there is 2428 * no need to call hw_disable here. 2429 ****************************************/ 2430 int rtl_pci_suspend(struct device *dev) 2431 { 2432 struct pci_dev *pdev = to_pci_dev(dev); 2433 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2434 struct rtl_priv *rtlpriv = rtl_priv(hw); 2435 2436 rtlpriv->cfg->ops->hw_suspend(hw); 2437 rtl_deinit_rfkill(hw); 2438 2439 return 0; 2440 } 2441 EXPORT_SYMBOL(rtl_pci_suspend); 2442 2443 int rtl_pci_resume(struct device *dev) 2444 { 2445 struct pci_dev *pdev = to_pci_dev(dev); 2446 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2447 struct rtl_priv *rtlpriv = rtl_priv(hw); 2448 2449 rtlpriv->cfg->ops->hw_resume(hw); 2450 rtl_init_rfkill(hw); 2451 return 0; 2452 } 2453 EXPORT_SYMBOL(rtl_pci_resume); 2454 #endif /* CONFIG_PM_SLEEP */ 2455 2456 const struct rtl_intf_ops rtl_pci_ops = { 2457 .read_efuse_byte = read_efuse_byte, 2458 .adapter_start = rtl_pci_start, 2459 .adapter_stop = rtl_pci_stop, 2460 .check_buddy_priv = rtl_pci_check_buddy_priv, 2461 .adapter_tx = rtl_pci_tx, 2462 .flush = rtl_pci_flush, 2463 .reset_trx_ring = rtl_pci_reset_trx_ring, 2464 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2465 2466 .disable_aspm = rtl_pci_disable_aspm, 2467 .enable_aspm = rtl_pci_enable_aspm, 2468 }; 2469