1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 40 static bool amdgpu_need_backup(struct amdgpu_device *adev) 41 { 42 if (adev->flags & AMD_IS_APU) 43 return false; 44 45 if (amdgpu_gpu_recovery == 0 || 46 (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev))) 47 return false; 48 49 return true; 50 } 51 52 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 53 { 54 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 55 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 56 57 amdgpu_bo_kunmap(bo); 58 59 drm_gem_object_release(&bo->gem_base); 60 amdgpu_bo_unref(&bo->parent); 61 if (!list_empty(&bo->shadow_list)) { 62 mutex_lock(&adev->shadow_list_lock); 63 list_del_init(&bo->shadow_list); 64 mutex_unlock(&adev->shadow_list_lock); 65 } 66 kfree(bo->metadata); 67 kfree(bo); 68 } 69 70 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 71 { 72 if (bo->destroy == &amdgpu_ttm_bo_destroy) 73 return true; 74 return false; 75 } 76 77 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 78 { 79 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 80 struct ttm_placement *placement = &abo->placement; 81 struct ttm_place *places = abo->placements; 82 u64 flags = abo->flags; 83 u32 c = 0; 84 85 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 86 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 87 88 places[c].fpfn = 0; 89 places[c].lpfn = 0; 90 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 91 TTM_PL_FLAG_VRAM; 92 93 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 94 places[c].lpfn = visible_pfn; 95 else 96 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 97 98 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 99 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 100 c++; 101 } 102 103 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 104 places[c].fpfn = 0; 105 if (flags & AMDGPU_GEM_CREATE_SHADOW) 106 places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT; 107 else 108 places[c].lpfn = 0; 109 places[c].flags = TTM_PL_FLAG_TT; 110 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 111 places[c].flags |= TTM_PL_FLAG_WC | 112 TTM_PL_FLAG_UNCACHED; 113 else 114 places[c].flags |= TTM_PL_FLAG_CACHED; 115 c++; 116 } 117 118 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 119 places[c].fpfn = 0; 120 places[c].lpfn = 0; 121 places[c].flags = TTM_PL_FLAG_SYSTEM; 122 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 123 places[c].flags |= TTM_PL_FLAG_WC | 124 TTM_PL_FLAG_UNCACHED; 125 else 126 places[c].flags |= TTM_PL_FLAG_CACHED; 127 c++; 128 } 129 130 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 131 places[c].fpfn = 0; 132 places[c].lpfn = 0; 133 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 134 c++; 135 } 136 137 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 138 places[c].fpfn = 0; 139 places[c].lpfn = 0; 140 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 141 c++; 142 } 143 144 if (domain & AMDGPU_GEM_DOMAIN_OA) { 145 places[c].fpfn = 0; 146 places[c].lpfn = 0; 147 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 148 c++; 149 } 150 151 if (!c) { 152 places[c].fpfn = 0; 153 places[c].lpfn = 0; 154 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 155 c++; 156 } 157 158 placement->num_placement = c; 159 placement->placement = places; 160 161 placement->num_busy_placement = c; 162 placement->busy_placement = places; 163 } 164 165 /** 166 * amdgpu_bo_create_reserved - create reserved BO for kernel use 167 * 168 * @adev: amdgpu device object 169 * @size: size for the new BO 170 * @align: alignment for the new BO 171 * @domain: where to place it 172 * @bo_ptr: resulting BO 173 * @gpu_addr: GPU addr of the pinned BO 174 * @cpu_addr: optional CPU address mapping 175 * 176 * Allocates and pins a BO for kernel internal use, and returns it still 177 * reserved. 178 * 179 * Returns 0 on success, negative error code otherwise. 180 */ 181 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 182 unsigned long size, int align, 183 u32 domain, struct amdgpu_bo **bo_ptr, 184 u64 *gpu_addr, void **cpu_addr) 185 { 186 bool free = false; 187 int r; 188 189 if (!*bo_ptr) { 190 r = amdgpu_bo_create(adev, size, align, true, domain, 191 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 192 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 193 NULL, NULL, 0, bo_ptr); 194 if (r) { 195 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 196 r); 197 return r; 198 } 199 free = true; 200 } 201 202 r = amdgpu_bo_reserve(*bo_ptr, false); 203 if (r) { 204 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 205 goto error_free; 206 } 207 208 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr); 209 if (r) { 210 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 211 goto error_unreserve; 212 } 213 214 if (cpu_addr) { 215 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 216 if (r) { 217 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 218 goto error_unreserve; 219 } 220 } 221 222 return 0; 223 224 error_unreserve: 225 amdgpu_bo_unreserve(*bo_ptr); 226 227 error_free: 228 if (free) 229 amdgpu_bo_unref(bo_ptr); 230 231 return r; 232 } 233 234 /** 235 * amdgpu_bo_create_kernel - create BO for kernel use 236 * 237 * @adev: amdgpu device object 238 * @size: size for the new BO 239 * @align: alignment for the new BO 240 * @domain: where to place it 241 * @bo_ptr: resulting BO 242 * @gpu_addr: GPU addr of the pinned BO 243 * @cpu_addr: optional CPU address mapping 244 * 245 * Allocates and pins a BO for kernel internal use. 246 * 247 * Returns 0 on success, negative error code otherwise. 248 */ 249 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 250 unsigned long size, int align, 251 u32 domain, struct amdgpu_bo **bo_ptr, 252 u64 *gpu_addr, void **cpu_addr) 253 { 254 int r; 255 256 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 257 gpu_addr, cpu_addr); 258 259 if (r) 260 return r; 261 262 amdgpu_bo_unreserve(*bo_ptr); 263 264 return 0; 265 } 266 267 /** 268 * amdgpu_bo_free_kernel - free BO for kernel use 269 * 270 * @bo: amdgpu BO to free 271 * 272 * unmaps and unpin a BO for kernel internal use. 273 */ 274 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 275 void **cpu_addr) 276 { 277 if (*bo == NULL) 278 return; 279 280 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 281 if (cpu_addr) 282 amdgpu_bo_kunmap(*bo); 283 284 amdgpu_bo_unpin(*bo); 285 amdgpu_bo_unreserve(*bo); 286 } 287 amdgpu_bo_unref(bo); 288 289 if (gpu_addr) 290 *gpu_addr = 0; 291 292 if (cpu_addr) 293 *cpu_addr = NULL; 294 } 295 296 /* Validate bo size is bit bigger then the request domain */ 297 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 298 unsigned long size, u32 domain) 299 { 300 struct ttm_mem_type_manager *man = NULL; 301 302 /* 303 * If GTT is part of requested domains the check must succeed to 304 * allow fall back to GTT 305 */ 306 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 307 man = &adev->mman.bdev.man[TTM_PL_TT]; 308 309 if (size < (man->size << PAGE_SHIFT)) 310 return true; 311 else 312 goto fail; 313 } 314 315 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 316 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 317 318 if (size < (man->size << PAGE_SHIFT)) 319 return true; 320 else 321 goto fail; 322 } 323 324 325 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 326 return true; 327 328 fail: 329 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 330 man->size << PAGE_SHIFT); 331 return false; 332 } 333 334 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 335 unsigned long size, int byte_align, 336 bool kernel, u32 domain, u64 flags, 337 struct sg_table *sg, 338 struct reservation_object *resv, 339 uint64_t init_value, 340 struct amdgpu_bo **bo_ptr) 341 { 342 struct ttm_operation_ctx ctx = { 343 .interruptible = !kernel, 344 .no_wait_gpu = false, 345 .allow_reserved_eviction = true, 346 .resv = resv 347 }; 348 struct amdgpu_bo *bo; 349 enum ttm_bo_type type; 350 unsigned long page_align; 351 size_t acc_size; 352 int r; 353 354 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 355 size = ALIGN(size, PAGE_SIZE); 356 357 if (!amdgpu_bo_validate_size(adev, size, domain)) 358 return -ENOMEM; 359 360 if (kernel) { 361 type = ttm_bo_type_kernel; 362 } else if (sg) { 363 type = ttm_bo_type_sg; 364 } else { 365 type = ttm_bo_type_device; 366 } 367 *bo_ptr = NULL; 368 369 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 370 sizeof(struct amdgpu_bo)); 371 372 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 373 if (bo == NULL) 374 return -ENOMEM; 375 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 376 if (unlikely(r)) { 377 kfree(bo); 378 return r; 379 } 380 INIT_LIST_HEAD(&bo->shadow_list); 381 INIT_LIST_HEAD(&bo->va); 382 bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | 383 AMDGPU_GEM_DOMAIN_GTT | 384 AMDGPU_GEM_DOMAIN_CPU | 385 AMDGPU_GEM_DOMAIN_GDS | 386 AMDGPU_GEM_DOMAIN_GWS | 387 AMDGPU_GEM_DOMAIN_OA); 388 bo->allowed_domains = bo->preferred_domains; 389 if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 390 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 391 392 bo->flags = flags; 393 394 #ifdef CONFIG_X86_32 395 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 396 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 397 */ 398 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 399 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 400 /* Don't try to enable write-combining when it can't work, or things 401 * may be slow 402 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 403 */ 404 405 #ifndef CONFIG_COMPILE_TEST 406 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 407 thanks to write-combining 408 #endif 409 410 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 411 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 412 "better performance thanks to write-combining\n"); 413 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 414 #else 415 /* For architectures that don't support WC memory, 416 * mask out the WC flag from the BO 417 */ 418 if (!drm_arch_can_wc_memory()) 419 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 420 #endif 421 422 bo->tbo.bdev = &adev->mman.bdev; 423 amdgpu_ttm_placement_from_domain(bo, domain); 424 425 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, 426 &bo->placement, page_align, &ctx, NULL, 427 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 428 if (unlikely(r != 0)) 429 return r; 430 431 if (adev->mc.visible_vram_size < adev->mc.real_vram_size && 432 bo->tbo.mem.mem_type == TTM_PL_VRAM && 433 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) 434 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 435 ctx.bytes_moved); 436 else 437 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 438 439 if (kernel) 440 bo->tbo.priority = 1; 441 442 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 443 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 444 struct dma_fence *fence; 445 446 r = amdgpu_fill_buffer(bo, init_value, bo->tbo.resv, &fence); 447 if (unlikely(r)) 448 goto fail_unreserve; 449 450 amdgpu_bo_fence(bo, fence, false); 451 dma_fence_put(bo->tbo.moving); 452 bo->tbo.moving = dma_fence_get(fence); 453 dma_fence_put(fence); 454 } 455 if (!resv) 456 amdgpu_bo_unreserve(bo); 457 *bo_ptr = bo; 458 459 trace_amdgpu_bo_create(bo); 460 461 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 462 if (type == ttm_bo_type_device) 463 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 464 465 return 0; 466 467 fail_unreserve: 468 if (!resv) 469 ww_mutex_unlock(&bo->tbo.resv->lock); 470 amdgpu_bo_unref(&bo); 471 return r; 472 } 473 474 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 475 unsigned long size, int byte_align, 476 struct amdgpu_bo *bo) 477 { 478 int r; 479 480 if (bo->shadow) 481 return 0; 482 483 r = amdgpu_bo_do_create(adev, size, byte_align, true, 484 AMDGPU_GEM_DOMAIN_GTT, 485 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 486 AMDGPU_GEM_CREATE_SHADOW, 487 NULL, bo->tbo.resv, 0, 488 &bo->shadow); 489 if (!r) { 490 bo->shadow->parent = amdgpu_bo_ref(bo); 491 mutex_lock(&adev->shadow_list_lock); 492 list_add_tail(&bo->shadow_list, &adev->shadow_list); 493 mutex_unlock(&adev->shadow_list_lock); 494 } 495 496 return r; 497 } 498 499 /* init_value will only take effect when flags contains 500 * AMDGPU_GEM_CREATE_VRAM_CLEARED. 501 */ 502 int amdgpu_bo_create(struct amdgpu_device *adev, 503 unsigned long size, int byte_align, 504 bool kernel, u32 domain, u64 flags, 505 struct sg_table *sg, 506 struct reservation_object *resv, 507 uint64_t init_value, 508 struct amdgpu_bo **bo_ptr) 509 { 510 uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW; 511 int r; 512 513 r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain, 514 parent_flags, sg, resv, init_value, bo_ptr); 515 if (r) 516 return r; 517 518 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) { 519 if (!resv) 520 WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv, 521 NULL)); 522 523 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr)); 524 525 if (!resv) 526 reservation_object_unlock((*bo_ptr)->tbo.resv); 527 528 if (r) 529 amdgpu_bo_unref(bo_ptr); 530 } 531 532 return r; 533 } 534 535 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 536 struct amdgpu_ring *ring, 537 struct amdgpu_bo *bo, 538 struct reservation_object *resv, 539 struct dma_fence **fence, 540 bool direct) 541 542 { 543 struct amdgpu_bo *shadow = bo->shadow; 544 uint64_t bo_addr, shadow_addr; 545 int r; 546 547 if (!shadow) 548 return -EINVAL; 549 550 bo_addr = amdgpu_bo_gpu_offset(bo); 551 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 552 553 r = reservation_object_reserve_shared(bo->tbo.resv); 554 if (r) 555 goto err; 556 557 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr, 558 amdgpu_bo_size(bo), resv, fence, 559 direct, false); 560 if (!r) 561 amdgpu_bo_fence(bo, *fence, true); 562 563 err: 564 return r; 565 } 566 567 int amdgpu_bo_validate(struct amdgpu_bo *bo) 568 { 569 struct ttm_operation_ctx ctx = { false, false }; 570 uint32_t domain; 571 int r; 572 573 if (bo->pin_count) 574 return 0; 575 576 domain = bo->preferred_domains; 577 578 retry: 579 amdgpu_ttm_placement_from_domain(bo, domain); 580 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 581 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 582 domain = bo->allowed_domains; 583 goto retry; 584 } 585 586 return r; 587 } 588 589 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 590 struct amdgpu_ring *ring, 591 struct amdgpu_bo *bo, 592 struct reservation_object *resv, 593 struct dma_fence **fence, 594 bool direct) 595 596 { 597 struct amdgpu_bo *shadow = bo->shadow; 598 uint64_t bo_addr, shadow_addr; 599 int r; 600 601 if (!shadow) 602 return -EINVAL; 603 604 bo_addr = amdgpu_bo_gpu_offset(bo); 605 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 606 607 r = reservation_object_reserve_shared(bo->tbo.resv); 608 if (r) 609 goto err; 610 611 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr, 612 amdgpu_bo_size(bo), resv, fence, 613 direct, false); 614 if (!r) 615 amdgpu_bo_fence(bo, *fence, true); 616 617 err: 618 return r; 619 } 620 621 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 622 { 623 void *kptr; 624 long r; 625 626 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 627 return -EPERM; 628 629 kptr = amdgpu_bo_kptr(bo); 630 if (kptr) { 631 if (ptr) 632 *ptr = kptr; 633 return 0; 634 } 635 636 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 637 MAX_SCHEDULE_TIMEOUT); 638 if (r < 0) 639 return r; 640 641 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 642 if (r) 643 return r; 644 645 if (ptr) 646 *ptr = amdgpu_bo_kptr(bo); 647 648 return 0; 649 } 650 651 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 652 { 653 bool is_iomem; 654 655 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 656 } 657 658 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 659 { 660 if (bo->kmap.bo) 661 ttm_bo_kunmap(&bo->kmap); 662 } 663 664 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 665 { 666 if (bo == NULL) 667 return NULL; 668 669 ttm_bo_reference(&bo->tbo); 670 return bo; 671 } 672 673 void amdgpu_bo_unref(struct amdgpu_bo **bo) 674 { 675 struct ttm_buffer_object *tbo; 676 677 if ((*bo) == NULL) 678 return; 679 680 tbo = &((*bo)->tbo); 681 ttm_bo_unref(&tbo); 682 if (tbo == NULL) 683 *bo = NULL; 684 } 685 686 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 687 u64 min_offset, u64 max_offset, 688 u64 *gpu_addr) 689 { 690 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 691 struct ttm_operation_ctx ctx = { false, false }; 692 int r, i; 693 694 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 695 return -EPERM; 696 697 if (WARN_ON_ONCE(min_offset > max_offset)) 698 return -EINVAL; 699 700 /* A shared bo cannot be migrated to VRAM */ 701 if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM)) 702 return -EINVAL; 703 704 if (bo->pin_count) { 705 uint32_t mem_type = bo->tbo.mem.mem_type; 706 707 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 708 return -EINVAL; 709 710 bo->pin_count++; 711 if (gpu_addr) 712 *gpu_addr = amdgpu_bo_gpu_offset(bo); 713 714 if (max_offset != 0) { 715 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 716 WARN_ON_ONCE(max_offset < 717 (amdgpu_bo_gpu_offset(bo) - domain_start)); 718 } 719 720 return 0; 721 } 722 723 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 724 /* force to pin into visible video ram */ 725 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 726 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 727 amdgpu_ttm_placement_from_domain(bo, domain); 728 for (i = 0; i < bo->placement.num_placement; i++) { 729 unsigned fpfn, lpfn; 730 731 fpfn = min_offset >> PAGE_SHIFT; 732 lpfn = max_offset >> PAGE_SHIFT; 733 734 if (fpfn > bo->placements[i].fpfn) 735 bo->placements[i].fpfn = fpfn; 736 if (!bo->placements[i].lpfn || 737 (lpfn && lpfn < bo->placements[i].lpfn)) 738 bo->placements[i].lpfn = lpfn; 739 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 740 } 741 742 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 743 if (unlikely(r)) { 744 dev_err(adev->dev, "%p pin failed\n", bo); 745 goto error; 746 } 747 748 r = amdgpu_ttm_alloc_gart(&bo->tbo); 749 if (unlikely(r)) { 750 dev_err(adev->dev, "%p bind failed\n", bo); 751 goto error; 752 } 753 754 bo->pin_count = 1; 755 if (gpu_addr != NULL) 756 *gpu_addr = amdgpu_bo_gpu_offset(bo); 757 758 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 759 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 760 adev->vram_pin_size += amdgpu_bo_size(bo); 761 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 762 adev->invisible_pin_size += amdgpu_bo_size(bo); 763 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 764 adev->gart_pin_size += amdgpu_bo_size(bo); 765 } 766 767 error: 768 return r; 769 } 770 771 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 772 { 773 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 774 } 775 776 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 777 { 778 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 779 struct ttm_operation_ctx ctx = { false, false }; 780 int r, i; 781 782 if (!bo->pin_count) { 783 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 784 return 0; 785 } 786 bo->pin_count--; 787 if (bo->pin_count) 788 return 0; 789 for (i = 0; i < bo->placement.num_placement; i++) { 790 bo->placements[i].lpfn = 0; 791 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 792 } 793 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 794 if (unlikely(r)) { 795 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 796 goto error; 797 } 798 799 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 800 adev->vram_pin_size -= amdgpu_bo_size(bo); 801 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 802 adev->invisible_pin_size -= amdgpu_bo_size(bo); 803 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 804 adev->gart_pin_size -= amdgpu_bo_size(bo); 805 } 806 807 error: 808 return r; 809 } 810 811 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 812 { 813 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 814 if (0 && (adev->flags & AMD_IS_APU)) { 815 /* Useless to evict on IGP chips */ 816 return 0; 817 } 818 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 819 } 820 821 static const char *amdgpu_vram_names[] = { 822 "UNKNOWN", 823 "GDDR1", 824 "DDR2", 825 "GDDR3", 826 "GDDR4", 827 "GDDR5", 828 "HBM", 829 "DDR3" 830 }; 831 832 int amdgpu_bo_init(struct amdgpu_device *adev) 833 { 834 /* reserve PAT memory space to WC for VRAM */ 835 arch_io_reserve_memtype_wc(adev->mc.aper_base, 836 adev->mc.aper_size); 837 838 /* Add an MTRR for the VRAM */ 839 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 840 adev->mc.aper_size); 841 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 842 adev->mc.mc_vram_size >> 20, 843 (unsigned long long)adev->mc.aper_size >> 20); 844 DRM_INFO("RAM width %dbits %s\n", 845 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); 846 return amdgpu_ttm_init(adev); 847 } 848 849 void amdgpu_bo_fini(struct amdgpu_device *adev) 850 { 851 amdgpu_ttm_fini(adev); 852 arch_phys_wc_del(adev->mc.vram_mtrr); 853 arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size); 854 } 855 856 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 857 struct vm_area_struct *vma) 858 { 859 return ttm_fbdev_mmap(vma, &bo->tbo); 860 } 861 862 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 863 { 864 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 865 866 if (adev->family <= AMDGPU_FAMILY_CZ && 867 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 868 return -EINVAL; 869 870 bo->tiling_flags = tiling_flags; 871 return 0; 872 } 873 874 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 875 { 876 lockdep_assert_held(&bo->tbo.resv->lock.base); 877 878 if (tiling_flags) 879 *tiling_flags = bo->tiling_flags; 880 } 881 882 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 883 uint32_t metadata_size, uint64_t flags) 884 { 885 void *buffer; 886 887 if (!metadata_size) { 888 if (bo->metadata_size) { 889 kfree(bo->metadata); 890 bo->metadata = NULL; 891 bo->metadata_size = 0; 892 } 893 return 0; 894 } 895 896 if (metadata == NULL) 897 return -EINVAL; 898 899 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 900 if (buffer == NULL) 901 return -ENOMEM; 902 903 kfree(bo->metadata); 904 bo->metadata_flags = flags; 905 bo->metadata = buffer; 906 bo->metadata_size = metadata_size; 907 908 return 0; 909 } 910 911 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 912 size_t buffer_size, uint32_t *metadata_size, 913 uint64_t *flags) 914 { 915 if (!buffer && !metadata_size) 916 return -EINVAL; 917 918 if (buffer) { 919 if (buffer_size < bo->metadata_size) 920 return -EINVAL; 921 922 if (bo->metadata_size) 923 memcpy(buffer, bo->metadata, bo->metadata_size); 924 } 925 926 if (metadata_size) 927 *metadata_size = bo->metadata_size; 928 if (flags) 929 *flags = bo->metadata_flags; 930 931 return 0; 932 } 933 934 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 935 bool evict, 936 struct ttm_mem_reg *new_mem) 937 { 938 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 939 struct amdgpu_bo *abo; 940 struct ttm_mem_reg *old_mem = &bo->mem; 941 942 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 943 return; 944 945 abo = ttm_to_amdgpu_bo(bo); 946 amdgpu_vm_bo_invalidate(adev, abo, evict); 947 948 amdgpu_bo_kunmap(abo); 949 950 /* remember the eviction */ 951 if (evict) 952 atomic64_inc(&adev->num_evictions); 953 954 /* update statistics */ 955 if (!new_mem) 956 return; 957 958 /* move_notify is called before move happens */ 959 trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 960 } 961 962 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 963 { 964 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 965 struct ttm_operation_ctx ctx = { false, false }; 966 struct amdgpu_bo *abo; 967 unsigned long offset, size; 968 int r; 969 970 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 971 return 0; 972 973 abo = ttm_to_amdgpu_bo(bo); 974 975 /* Remember that this BO was accessed by the CPU */ 976 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 977 978 if (bo->mem.mem_type != TTM_PL_VRAM) 979 return 0; 980 981 size = bo->mem.num_pages << PAGE_SHIFT; 982 offset = bo->mem.start << PAGE_SHIFT; 983 if ((offset + size) <= adev->mc.visible_vram_size) 984 return 0; 985 986 /* Can't move a pinned BO to visible VRAM */ 987 if (abo->pin_count > 0) 988 return -EINVAL; 989 990 /* hurrah the memory is not visible ! */ 991 atomic64_inc(&adev->num_vram_cpu_page_faults); 992 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 993 AMDGPU_GEM_DOMAIN_GTT); 994 995 /* Avoid costly evictions; only set GTT as a busy placement */ 996 abo->placement.num_busy_placement = 1; 997 abo->placement.busy_placement = &abo->placements[1]; 998 999 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1000 if (unlikely(r != 0)) 1001 return r; 1002 1003 offset = bo->mem.start << PAGE_SHIFT; 1004 /* this should never happen */ 1005 if (bo->mem.mem_type == TTM_PL_VRAM && 1006 (offset + size) > adev->mc.visible_vram_size) 1007 return -EINVAL; 1008 1009 return 0; 1010 } 1011 1012 /** 1013 * amdgpu_bo_fence - add fence to buffer object 1014 * 1015 * @bo: buffer object in question 1016 * @fence: fence to add 1017 * @shared: true if fence should be added shared 1018 * 1019 */ 1020 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1021 bool shared) 1022 { 1023 struct reservation_object *resv = bo->tbo.resv; 1024 1025 if (shared) 1026 reservation_object_add_shared_fence(resv, fence); 1027 else 1028 reservation_object_add_excl_fence(resv, fence); 1029 } 1030 1031 /** 1032 * amdgpu_bo_gpu_offset - return GPU offset of bo 1033 * @bo: amdgpu object for which we query the offset 1034 * 1035 * Returns current GPU offset of the object. 1036 * 1037 * Note: object should either be pinned or reserved when calling this 1038 * function, it might be useful to add check for this for debugging. 1039 */ 1040 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1041 { 1042 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1043 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && 1044 !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem)); 1045 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 1046 !bo->pin_count); 1047 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1048 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1049 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1050 1051 return bo->tbo.offset; 1052 } 1053