1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/mlx5/fs.h> 54 #include <linux/list.h> 55 #include <rdma/ib_smi.h> 56 #include <rdma/ib_umem.h> 57 #include <linux/in.h> 58 #include <linux/etherdevice.h> 59 #include "mlx5_ib.h" 60 #include "ib_rep.h" 61 #include "cmd.h" 62 #include <linux/mlx5/fs_helpers.h> 63 64 #define DRIVER_NAME "mlx5_ib" 65 #define DRIVER_VERSION "5.0-0" 66 67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 69 MODULE_LICENSE("Dual BSD/GPL"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION "\n"; 74 75 struct mlx5_ib_event_work { 76 struct work_struct work; 77 struct mlx5_core_dev *dev; 78 void *context; 79 enum mlx5_dev_event event; 80 unsigned long param; 81 }; 82 83 enum { 84 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 85 }; 86 87 static struct workqueue_struct *mlx5_ib_event_wq; 88 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 89 static LIST_HEAD(mlx5_ib_dev_list); 90 /* 91 * This mutex should be held when accessing either of the above lists 92 */ 93 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 94 95 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 96 { 97 struct mlx5_ib_dev *dev; 98 99 mutex_lock(&mlx5_ib_multiport_mutex); 100 dev = mpi->ibdev; 101 mutex_unlock(&mlx5_ib_multiport_mutex); 102 return dev; 103 } 104 105 static enum rdma_link_layer 106 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 107 { 108 switch (port_type_cap) { 109 case MLX5_CAP_PORT_TYPE_IB: 110 return IB_LINK_LAYER_INFINIBAND; 111 case MLX5_CAP_PORT_TYPE_ETH: 112 return IB_LINK_LAYER_ETHERNET; 113 default: 114 return IB_LINK_LAYER_UNSPECIFIED; 115 } 116 } 117 118 static enum rdma_link_layer 119 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 120 { 121 struct mlx5_ib_dev *dev = to_mdev(device); 122 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 123 124 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 125 } 126 127 static int get_port_state(struct ib_device *ibdev, 128 u8 port_num, 129 enum ib_port_state *state) 130 { 131 struct ib_port_attr attr; 132 int ret; 133 134 memset(&attr, 0, sizeof(attr)); 135 ret = ibdev->query_port(ibdev, port_num, &attr); 136 if (!ret) 137 *state = attr.state; 138 return ret; 139 } 140 141 static int mlx5_netdev_event(struct notifier_block *this, 142 unsigned long event, void *ptr) 143 { 144 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 145 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 146 u8 port_num = roce->native_port_num; 147 struct mlx5_core_dev *mdev; 148 struct mlx5_ib_dev *ibdev; 149 150 ibdev = roce->dev; 151 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 152 if (!mdev) 153 return NOTIFY_DONE; 154 155 switch (event) { 156 case NETDEV_REGISTER: 157 case NETDEV_UNREGISTER: 158 write_lock(&roce->netdev_lock); 159 if (ibdev->rep) { 160 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 161 struct net_device *rep_ndev; 162 163 rep_ndev = mlx5_ib_get_rep_netdev(esw, 164 ibdev->rep->vport); 165 if (rep_ndev == ndev) 166 roce->netdev = (event == NETDEV_UNREGISTER) ? 167 NULL : ndev; 168 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) { 169 roce->netdev = (event == NETDEV_UNREGISTER) ? 170 NULL : ndev; 171 } 172 write_unlock(&roce->netdev_lock); 173 break; 174 175 case NETDEV_CHANGE: 176 case NETDEV_UP: 177 case NETDEV_DOWN: { 178 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 179 struct net_device *upper = NULL; 180 181 if (lag_ndev) { 182 upper = netdev_master_upper_dev_get(lag_ndev); 183 dev_put(lag_ndev); 184 } 185 186 if ((upper == ndev || (!upper && ndev == roce->netdev)) 187 && ibdev->ib_active) { 188 struct ib_event ibev = { }; 189 enum ib_port_state port_state; 190 191 if (get_port_state(&ibdev->ib_dev, port_num, 192 &port_state)) 193 goto done; 194 195 if (roce->last_port_state == port_state) 196 goto done; 197 198 roce->last_port_state = port_state; 199 ibev.device = &ibdev->ib_dev; 200 if (port_state == IB_PORT_DOWN) 201 ibev.event = IB_EVENT_PORT_ERR; 202 else if (port_state == IB_PORT_ACTIVE) 203 ibev.event = IB_EVENT_PORT_ACTIVE; 204 else 205 goto done; 206 207 ibev.element.port_num = port_num; 208 ib_dispatch_event(&ibev); 209 } 210 break; 211 } 212 213 default: 214 break; 215 } 216 done: 217 mlx5_ib_put_native_port_mdev(ibdev, port_num); 218 return NOTIFY_DONE; 219 } 220 221 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 222 u8 port_num) 223 { 224 struct mlx5_ib_dev *ibdev = to_mdev(device); 225 struct net_device *ndev; 226 struct mlx5_core_dev *mdev; 227 228 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 229 if (!mdev) 230 return NULL; 231 232 ndev = mlx5_lag_get_roce_netdev(mdev); 233 if (ndev) 234 goto out; 235 236 /* Ensure ndev does not disappear before we invoke dev_hold() 237 */ 238 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 239 ndev = ibdev->roce[port_num - 1].netdev; 240 if (ndev) 241 dev_hold(ndev); 242 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 243 244 out: 245 mlx5_ib_put_native_port_mdev(ibdev, port_num); 246 return ndev; 247 } 248 249 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 250 u8 ib_port_num, 251 u8 *native_port_num) 252 { 253 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 254 ib_port_num); 255 struct mlx5_core_dev *mdev = NULL; 256 struct mlx5_ib_multiport_info *mpi; 257 struct mlx5_ib_port *port; 258 259 if (!mlx5_core_mp_enabled(ibdev->mdev) || 260 ll != IB_LINK_LAYER_ETHERNET) { 261 if (native_port_num) 262 *native_port_num = ib_port_num; 263 return ibdev->mdev; 264 } 265 266 if (native_port_num) 267 *native_port_num = 1; 268 269 port = &ibdev->port[ib_port_num - 1]; 270 if (!port) 271 return NULL; 272 273 spin_lock(&port->mp.mpi_lock); 274 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 275 if (mpi && !mpi->unaffiliate) { 276 mdev = mpi->mdev; 277 /* If it's the master no need to refcount, it'll exist 278 * as long as the ib_dev exists. 279 */ 280 if (!mpi->is_master) 281 mpi->mdev_refcnt++; 282 } 283 spin_unlock(&port->mp.mpi_lock); 284 285 return mdev; 286 } 287 288 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 289 { 290 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 291 port_num); 292 struct mlx5_ib_multiport_info *mpi; 293 struct mlx5_ib_port *port; 294 295 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 296 return; 297 298 port = &ibdev->port[port_num - 1]; 299 300 spin_lock(&port->mp.mpi_lock); 301 mpi = ibdev->port[port_num - 1].mp.mpi; 302 if (mpi->is_master) 303 goto out; 304 305 mpi->mdev_refcnt--; 306 if (mpi->unaffiliate) 307 complete(&mpi->unref_comp); 308 out: 309 spin_unlock(&port->mp.mpi_lock); 310 } 311 312 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 313 u8 *active_width) 314 { 315 switch (eth_proto_oper) { 316 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 317 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 318 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 319 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 320 *active_width = IB_WIDTH_1X; 321 *active_speed = IB_SPEED_SDR; 322 break; 323 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 324 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 325 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 326 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 327 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 328 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 329 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 330 *active_width = IB_WIDTH_1X; 331 *active_speed = IB_SPEED_QDR; 332 break; 333 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 334 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 335 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 336 *active_width = IB_WIDTH_1X; 337 *active_speed = IB_SPEED_EDR; 338 break; 339 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 340 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 341 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 342 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 343 *active_width = IB_WIDTH_4X; 344 *active_speed = IB_SPEED_QDR; 345 break; 346 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 347 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 348 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 349 *active_width = IB_WIDTH_1X; 350 *active_speed = IB_SPEED_HDR; 351 break; 352 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 353 *active_width = IB_WIDTH_4X; 354 *active_speed = IB_SPEED_FDR; 355 break; 356 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 357 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 358 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 359 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 360 *active_width = IB_WIDTH_4X; 361 *active_speed = IB_SPEED_EDR; 362 break; 363 default: 364 return -EINVAL; 365 } 366 367 return 0; 368 } 369 370 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 371 struct ib_port_attr *props) 372 { 373 struct mlx5_ib_dev *dev = to_mdev(device); 374 struct mlx5_core_dev *mdev; 375 struct net_device *ndev, *upper; 376 enum ib_mtu ndev_ib_mtu; 377 bool put_mdev = true; 378 u16 qkey_viol_cntr; 379 u32 eth_prot_oper; 380 u8 mdev_port_num; 381 int err; 382 383 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 384 if (!mdev) { 385 /* This means the port isn't affiliated yet. Get the 386 * info for the master port instead. 387 */ 388 put_mdev = false; 389 mdev = dev->mdev; 390 mdev_port_num = 1; 391 port_num = 1; 392 } 393 394 /* Possible bad flows are checked before filling out props so in case 395 * of an error it will still be zeroed out. 396 */ 397 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 398 mdev_port_num); 399 if (err) 400 goto out; 401 402 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 403 &props->active_width); 404 405 props->port_cap_flags |= IB_PORT_CM_SUP; 406 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 407 408 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 409 roce_address_table_size); 410 props->max_mtu = IB_MTU_4096; 411 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 412 props->pkey_tbl_len = 1; 413 props->state = IB_PORT_DOWN; 414 props->phys_state = 3; 415 416 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 417 props->qkey_viol_cntr = qkey_viol_cntr; 418 419 /* If this is a stub query for an unaffiliated port stop here */ 420 if (!put_mdev) 421 goto out; 422 423 ndev = mlx5_ib_get_netdev(device, port_num); 424 if (!ndev) 425 goto out; 426 427 if (mlx5_lag_is_active(dev->mdev)) { 428 rcu_read_lock(); 429 upper = netdev_master_upper_dev_get_rcu(ndev); 430 if (upper) { 431 dev_put(ndev); 432 ndev = upper; 433 dev_hold(ndev); 434 } 435 rcu_read_unlock(); 436 } 437 438 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 439 props->state = IB_PORT_ACTIVE; 440 props->phys_state = 5; 441 } 442 443 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 444 445 dev_put(ndev); 446 447 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 448 out: 449 if (put_mdev) 450 mlx5_ib_put_native_port_mdev(dev, port_num); 451 return err; 452 } 453 454 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 455 unsigned int index, const union ib_gid *gid, 456 const struct ib_gid_attr *attr) 457 { 458 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 459 u8 roce_version = 0; 460 u8 roce_l3_type = 0; 461 bool vlan = false; 462 u8 mac[ETH_ALEN]; 463 u16 vlan_id = 0; 464 465 if (gid) { 466 gid_type = attr->gid_type; 467 ether_addr_copy(mac, attr->ndev->dev_addr); 468 469 if (is_vlan_dev(attr->ndev)) { 470 vlan = true; 471 vlan_id = vlan_dev_vlan_id(attr->ndev); 472 } 473 } 474 475 switch (gid_type) { 476 case IB_GID_TYPE_IB: 477 roce_version = MLX5_ROCE_VERSION_1; 478 break; 479 case IB_GID_TYPE_ROCE_UDP_ENCAP: 480 roce_version = MLX5_ROCE_VERSION_2; 481 if (ipv6_addr_v4mapped((void *)gid)) 482 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 483 else 484 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 485 break; 486 487 default: 488 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 489 } 490 491 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 492 roce_l3_type, gid->raw, mac, vlan, 493 vlan_id, port_num); 494 } 495 496 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 497 unsigned int index, const union ib_gid *gid, 498 const struct ib_gid_attr *attr, 499 __always_unused void **context) 500 { 501 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 502 } 503 504 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 505 unsigned int index, __always_unused void **context) 506 { 507 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 508 } 509 510 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 511 int index) 512 { 513 struct ib_gid_attr attr; 514 union ib_gid gid; 515 516 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 517 return 0; 518 519 if (!attr.ndev) 520 return 0; 521 522 dev_put(attr.ndev); 523 524 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 525 return 0; 526 527 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 528 } 529 530 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 531 int index, enum ib_gid_type *gid_type) 532 { 533 struct ib_gid_attr attr; 534 union ib_gid gid; 535 int ret; 536 537 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 538 if (ret) 539 return ret; 540 541 if (!attr.ndev) 542 return -ENODEV; 543 544 dev_put(attr.ndev); 545 546 *gid_type = attr.gid_type; 547 548 return 0; 549 } 550 551 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 552 { 553 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 554 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 555 return 0; 556 } 557 558 enum { 559 MLX5_VPORT_ACCESS_METHOD_MAD, 560 MLX5_VPORT_ACCESS_METHOD_HCA, 561 MLX5_VPORT_ACCESS_METHOD_NIC, 562 }; 563 564 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 565 { 566 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 567 return MLX5_VPORT_ACCESS_METHOD_MAD; 568 569 if (mlx5_ib_port_link_layer(ibdev, 1) == 570 IB_LINK_LAYER_ETHERNET) 571 return MLX5_VPORT_ACCESS_METHOD_NIC; 572 573 return MLX5_VPORT_ACCESS_METHOD_HCA; 574 } 575 576 static void get_atomic_caps(struct mlx5_ib_dev *dev, 577 u8 atomic_size_qp, 578 struct ib_device_attr *props) 579 { 580 u8 tmp; 581 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 582 u8 atomic_req_8B_endianness_mode = 583 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 584 585 /* Check if HW supports 8 bytes standard atomic operations and capable 586 * of host endianness respond 587 */ 588 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 589 if (((atomic_operations & tmp) == tmp) && 590 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 591 (atomic_req_8B_endianness_mode)) { 592 props->atomic_cap = IB_ATOMIC_HCA; 593 } else { 594 props->atomic_cap = IB_ATOMIC_NONE; 595 } 596 } 597 598 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 599 struct ib_device_attr *props) 600 { 601 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 602 603 get_atomic_caps(dev, atomic_size_qp, props); 604 } 605 606 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 607 struct ib_device_attr *props) 608 { 609 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 610 611 get_atomic_caps(dev, atomic_size_qp, props); 612 } 613 614 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 615 { 616 struct ib_device_attr props = {}; 617 618 get_atomic_caps_dc(dev, &props); 619 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 620 } 621 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 622 __be64 *sys_image_guid) 623 { 624 struct mlx5_ib_dev *dev = to_mdev(ibdev); 625 struct mlx5_core_dev *mdev = dev->mdev; 626 u64 tmp; 627 int err; 628 629 switch (mlx5_get_vport_access_method(ibdev)) { 630 case MLX5_VPORT_ACCESS_METHOD_MAD: 631 return mlx5_query_mad_ifc_system_image_guid(ibdev, 632 sys_image_guid); 633 634 case MLX5_VPORT_ACCESS_METHOD_HCA: 635 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 636 break; 637 638 case MLX5_VPORT_ACCESS_METHOD_NIC: 639 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 640 break; 641 642 default: 643 return -EINVAL; 644 } 645 646 if (!err) 647 *sys_image_guid = cpu_to_be64(tmp); 648 649 return err; 650 651 } 652 653 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 654 u16 *max_pkeys) 655 { 656 struct mlx5_ib_dev *dev = to_mdev(ibdev); 657 struct mlx5_core_dev *mdev = dev->mdev; 658 659 switch (mlx5_get_vport_access_method(ibdev)) { 660 case MLX5_VPORT_ACCESS_METHOD_MAD: 661 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 662 663 case MLX5_VPORT_ACCESS_METHOD_HCA: 664 case MLX5_VPORT_ACCESS_METHOD_NIC: 665 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 666 pkey_table_size)); 667 return 0; 668 669 default: 670 return -EINVAL; 671 } 672 } 673 674 static int mlx5_query_vendor_id(struct ib_device *ibdev, 675 u32 *vendor_id) 676 { 677 struct mlx5_ib_dev *dev = to_mdev(ibdev); 678 679 switch (mlx5_get_vport_access_method(ibdev)) { 680 case MLX5_VPORT_ACCESS_METHOD_MAD: 681 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 682 683 case MLX5_VPORT_ACCESS_METHOD_HCA: 684 case MLX5_VPORT_ACCESS_METHOD_NIC: 685 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 686 687 default: 688 return -EINVAL; 689 } 690 } 691 692 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 693 __be64 *node_guid) 694 { 695 u64 tmp; 696 int err; 697 698 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 699 case MLX5_VPORT_ACCESS_METHOD_MAD: 700 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 701 702 case MLX5_VPORT_ACCESS_METHOD_HCA: 703 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 704 break; 705 706 case MLX5_VPORT_ACCESS_METHOD_NIC: 707 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 708 break; 709 710 default: 711 return -EINVAL; 712 } 713 714 if (!err) 715 *node_guid = cpu_to_be64(tmp); 716 717 return err; 718 } 719 720 struct mlx5_reg_node_desc { 721 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 722 }; 723 724 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 725 { 726 struct mlx5_reg_node_desc in; 727 728 if (mlx5_use_mad_ifc(dev)) 729 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 730 731 memset(&in, 0, sizeof(in)); 732 733 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 734 sizeof(struct mlx5_reg_node_desc), 735 MLX5_REG_NODE_DESC, 0, 0); 736 } 737 738 static int mlx5_ib_query_device(struct ib_device *ibdev, 739 struct ib_device_attr *props, 740 struct ib_udata *uhw) 741 { 742 struct mlx5_ib_dev *dev = to_mdev(ibdev); 743 struct mlx5_core_dev *mdev = dev->mdev; 744 int err = -ENOMEM; 745 int max_sq_desc; 746 int max_rq_sg; 747 int max_sq_sg; 748 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 749 bool raw_support = !mlx5_core_mp_enabled(mdev); 750 struct mlx5_ib_query_device_resp resp = {}; 751 size_t resp_len; 752 u64 max_tso; 753 754 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 755 if (uhw->outlen && uhw->outlen < resp_len) 756 return -EINVAL; 757 else 758 resp.response_length = resp_len; 759 760 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 761 return -EINVAL; 762 763 memset(props, 0, sizeof(*props)); 764 err = mlx5_query_system_image_guid(ibdev, 765 &props->sys_image_guid); 766 if (err) 767 return err; 768 769 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 770 if (err) 771 return err; 772 773 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 774 if (err) 775 return err; 776 777 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 778 (fw_rev_min(dev->mdev) << 16) | 779 fw_rev_sub(dev->mdev); 780 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 781 IB_DEVICE_PORT_ACTIVE_EVENT | 782 IB_DEVICE_SYS_IMAGE_GUID | 783 IB_DEVICE_RC_RNR_NAK_GEN; 784 785 if (MLX5_CAP_GEN(mdev, pkv)) 786 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 787 if (MLX5_CAP_GEN(mdev, qkv)) 788 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 789 if (MLX5_CAP_GEN(mdev, apm)) 790 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 791 if (MLX5_CAP_GEN(mdev, xrc)) 792 props->device_cap_flags |= IB_DEVICE_XRC; 793 if (MLX5_CAP_GEN(mdev, imaicl)) { 794 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 795 IB_DEVICE_MEM_WINDOW_TYPE_2B; 796 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 797 /* We support 'Gappy' memory registration too */ 798 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 799 } 800 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 801 if (MLX5_CAP_GEN(mdev, sho)) { 802 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 803 /* At this stage no support for signature handover */ 804 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 805 IB_PROT_T10DIF_TYPE_2 | 806 IB_PROT_T10DIF_TYPE_3; 807 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 808 IB_GUARD_T10DIF_CSUM; 809 } 810 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 811 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 812 813 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 814 if (MLX5_CAP_ETH(mdev, csum_cap)) { 815 /* Legacy bit to support old userspace libraries */ 816 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 817 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 818 } 819 820 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 821 props->raw_packet_caps |= 822 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 823 824 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 825 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 826 if (max_tso) { 827 resp.tso_caps.max_tso = 1 << max_tso; 828 resp.tso_caps.supported_qpts |= 829 1 << IB_QPT_RAW_PACKET; 830 resp.response_length += sizeof(resp.tso_caps); 831 } 832 } 833 834 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 835 resp.rss_caps.rx_hash_function = 836 MLX5_RX_HASH_FUNC_TOEPLITZ; 837 resp.rss_caps.rx_hash_fields_mask = 838 MLX5_RX_HASH_SRC_IPV4 | 839 MLX5_RX_HASH_DST_IPV4 | 840 MLX5_RX_HASH_SRC_IPV6 | 841 MLX5_RX_HASH_DST_IPV6 | 842 MLX5_RX_HASH_SRC_PORT_TCP | 843 MLX5_RX_HASH_DST_PORT_TCP | 844 MLX5_RX_HASH_SRC_PORT_UDP | 845 MLX5_RX_HASH_DST_PORT_UDP | 846 MLX5_RX_HASH_INNER; 847 resp.response_length += sizeof(resp.rss_caps); 848 } 849 } else { 850 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 851 resp.response_length += sizeof(resp.tso_caps); 852 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 853 resp.response_length += sizeof(resp.rss_caps); 854 } 855 856 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 858 props->device_cap_flags |= IB_DEVICE_UD_TSO; 859 } 860 861 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 862 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 863 raw_support) 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 865 866 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 867 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 868 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 869 870 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 871 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 872 raw_support) { 873 /* Legacy bit to support old userspace libraries */ 874 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 875 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 876 } 877 878 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 879 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 880 881 if (MLX5_CAP_GEN(mdev, end_pad)) 882 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 883 884 props->vendor_part_id = mdev->pdev->device; 885 props->hw_ver = mdev->pdev->revision; 886 887 props->max_mr_size = ~0ull; 888 props->page_size_cap = ~(min_page_size - 1); 889 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 890 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 891 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 892 sizeof(struct mlx5_wqe_data_seg); 893 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 894 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 895 sizeof(struct mlx5_wqe_raddr_seg)) / 896 sizeof(struct mlx5_wqe_data_seg); 897 props->max_sge = min(max_rq_sg, max_sq_sg); 898 props->max_sge_rd = MLX5_MAX_SGE_RD; 899 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 900 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 901 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 902 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 903 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 904 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 905 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 906 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 907 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 908 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 909 props->max_srq_sge = max_rq_sg - 1; 910 props->max_fast_reg_page_list_len = 911 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 912 get_atomic_caps_qp(dev, props); 913 props->masked_atomic_cap = IB_ATOMIC_NONE; 914 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 915 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 916 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 917 props->max_mcast_grp; 918 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 919 props->max_ah = INT_MAX; 920 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 921 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 922 923 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 924 if (MLX5_CAP_GEN(mdev, pg)) 925 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 926 props->odp_caps = dev->odp_caps; 927 #endif 928 929 if (MLX5_CAP_GEN(mdev, cd)) 930 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 931 932 if (!mlx5_core_is_pf(mdev)) 933 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 934 935 if (mlx5_ib_port_link_layer(ibdev, 1) == 936 IB_LINK_LAYER_ETHERNET && raw_support) { 937 props->rss_caps.max_rwq_indirection_tables = 938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 939 props->rss_caps.max_rwq_indirection_table_size = 940 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 941 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 942 props->max_wq_type_rq = 943 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 944 } 945 946 if (MLX5_CAP_GEN(mdev, tag_matching)) { 947 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 948 props->tm_caps.max_num_tags = 949 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 950 props->tm_caps.flags = IB_TM_CAP_RC; 951 props->tm_caps.max_ops = 952 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 953 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 954 } 955 956 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 957 props->cq_caps.max_cq_moderation_count = 958 MLX5_MAX_CQ_COUNT; 959 props->cq_caps.max_cq_moderation_period = 960 MLX5_MAX_CQ_PERIOD; 961 } 962 963 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 964 resp.cqe_comp_caps.max_num = 965 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 966 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 967 resp.cqe_comp_caps.supported_format = 968 MLX5_IB_CQE_RES_FORMAT_HASH | 969 MLX5_IB_CQE_RES_FORMAT_CSUM; 970 resp.response_length += sizeof(resp.cqe_comp_caps); 971 } 972 973 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 974 raw_support) { 975 if (MLX5_CAP_QOS(mdev, packet_pacing) && 976 MLX5_CAP_GEN(mdev, qos)) { 977 resp.packet_pacing_caps.qp_rate_limit_max = 978 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 979 resp.packet_pacing_caps.qp_rate_limit_min = 980 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 981 resp.packet_pacing_caps.supported_qpts |= 982 1 << IB_QPT_RAW_PACKET; 983 } 984 resp.response_length += sizeof(resp.packet_pacing_caps); 985 } 986 987 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 988 uhw->outlen)) { 989 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 990 resp.mlx5_ib_support_multi_pkt_send_wqes = 991 MLX5_IB_ALLOW_MPW; 992 993 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 994 resp.mlx5_ib_support_multi_pkt_send_wqes |= 995 MLX5_IB_SUPPORT_EMPW; 996 997 resp.response_length += 998 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 999 } 1000 1001 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1002 resp.response_length += sizeof(resp.flags); 1003 1004 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1005 resp.flags |= 1006 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1007 1008 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1009 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1010 } 1011 1012 if (field_avail(typeof(resp), sw_parsing_caps, 1013 uhw->outlen)) { 1014 resp.response_length += sizeof(resp.sw_parsing_caps); 1015 if (MLX5_CAP_ETH(mdev, swp)) { 1016 resp.sw_parsing_caps.sw_parsing_offloads |= 1017 MLX5_IB_SW_PARSING; 1018 1019 if (MLX5_CAP_ETH(mdev, swp_csum)) 1020 resp.sw_parsing_caps.sw_parsing_offloads |= 1021 MLX5_IB_SW_PARSING_CSUM; 1022 1023 if (MLX5_CAP_ETH(mdev, swp_lso)) 1024 resp.sw_parsing_caps.sw_parsing_offloads |= 1025 MLX5_IB_SW_PARSING_LSO; 1026 1027 if (resp.sw_parsing_caps.sw_parsing_offloads) 1028 resp.sw_parsing_caps.supported_qpts = 1029 BIT(IB_QPT_RAW_PACKET); 1030 } 1031 } 1032 1033 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1034 raw_support) { 1035 resp.response_length += sizeof(resp.striding_rq_caps); 1036 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1037 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1038 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1039 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1040 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1041 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1042 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1043 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1044 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1045 resp.striding_rq_caps.supported_qpts = 1046 BIT(IB_QPT_RAW_PACKET); 1047 } 1048 } 1049 1050 if (field_avail(typeof(resp), tunnel_offloads_caps, 1051 uhw->outlen)) { 1052 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1053 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1054 resp.tunnel_offloads_caps |= 1055 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1056 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1057 resp.tunnel_offloads_caps |= 1058 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1059 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1060 resp.tunnel_offloads_caps |= 1061 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1062 } 1063 1064 if (uhw->outlen) { 1065 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1066 1067 if (err) 1068 return err; 1069 } 1070 1071 return 0; 1072 } 1073 1074 enum mlx5_ib_width { 1075 MLX5_IB_WIDTH_1X = 1 << 0, 1076 MLX5_IB_WIDTH_2X = 1 << 1, 1077 MLX5_IB_WIDTH_4X = 1 << 2, 1078 MLX5_IB_WIDTH_8X = 1 << 3, 1079 MLX5_IB_WIDTH_12X = 1 << 4 1080 }; 1081 1082 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1083 u8 *ib_width) 1084 { 1085 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1086 int err = 0; 1087 1088 if (active_width & MLX5_IB_WIDTH_1X) { 1089 *ib_width = IB_WIDTH_1X; 1090 } else if (active_width & MLX5_IB_WIDTH_2X) { 1091 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1092 (int)active_width); 1093 err = -EINVAL; 1094 } else if (active_width & MLX5_IB_WIDTH_4X) { 1095 *ib_width = IB_WIDTH_4X; 1096 } else if (active_width & MLX5_IB_WIDTH_8X) { 1097 *ib_width = IB_WIDTH_8X; 1098 } else if (active_width & MLX5_IB_WIDTH_12X) { 1099 *ib_width = IB_WIDTH_12X; 1100 } else { 1101 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1102 (int)active_width); 1103 err = -EINVAL; 1104 } 1105 1106 return err; 1107 } 1108 1109 static int mlx5_mtu_to_ib_mtu(int mtu) 1110 { 1111 switch (mtu) { 1112 case 256: return 1; 1113 case 512: return 2; 1114 case 1024: return 3; 1115 case 2048: return 4; 1116 case 4096: return 5; 1117 default: 1118 pr_warn("invalid mtu\n"); 1119 return -1; 1120 } 1121 } 1122 1123 enum ib_max_vl_num { 1124 __IB_MAX_VL_0 = 1, 1125 __IB_MAX_VL_0_1 = 2, 1126 __IB_MAX_VL_0_3 = 3, 1127 __IB_MAX_VL_0_7 = 4, 1128 __IB_MAX_VL_0_14 = 5, 1129 }; 1130 1131 enum mlx5_vl_hw_cap { 1132 MLX5_VL_HW_0 = 1, 1133 MLX5_VL_HW_0_1 = 2, 1134 MLX5_VL_HW_0_2 = 3, 1135 MLX5_VL_HW_0_3 = 4, 1136 MLX5_VL_HW_0_4 = 5, 1137 MLX5_VL_HW_0_5 = 6, 1138 MLX5_VL_HW_0_6 = 7, 1139 MLX5_VL_HW_0_7 = 8, 1140 MLX5_VL_HW_0_14 = 15 1141 }; 1142 1143 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1144 u8 *max_vl_num) 1145 { 1146 switch (vl_hw_cap) { 1147 case MLX5_VL_HW_0: 1148 *max_vl_num = __IB_MAX_VL_0; 1149 break; 1150 case MLX5_VL_HW_0_1: 1151 *max_vl_num = __IB_MAX_VL_0_1; 1152 break; 1153 case MLX5_VL_HW_0_3: 1154 *max_vl_num = __IB_MAX_VL_0_3; 1155 break; 1156 case MLX5_VL_HW_0_7: 1157 *max_vl_num = __IB_MAX_VL_0_7; 1158 break; 1159 case MLX5_VL_HW_0_14: 1160 *max_vl_num = __IB_MAX_VL_0_14; 1161 break; 1162 1163 default: 1164 return -EINVAL; 1165 } 1166 1167 return 0; 1168 } 1169 1170 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1171 struct ib_port_attr *props) 1172 { 1173 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1174 struct mlx5_core_dev *mdev = dev->mdev; 1175 struct mlx5_hca_vport_context *rep; 1176 u16 max_mtu; 1177 u16 oper_mtu; 1178 int err; 1179 u8 ib_link_width_oper; 1180 u8 vl_hw_cap; 1181 1182 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1183 if (!rep) { 1184 err = -ENOMEM; 1185 goto out; 1186 } 1187 1188 /* props being zeroed by the caller, avoid zeroing it here */ 1189 1190 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1191 if (err) 1192 goto out; 1193 1194 props->lid = rep->lid; 1195 props->lmc = rep->lmc; 1196 props->sm_lid = rep->sm_lid; 1197 props->sm_sl = rep->sm_sl; 1198 props->state = rep->vport_state; 1199 props->phys_state = rep->port_physical_state; 1200 props->port_cap_flags = rep->cap_mask1; 1201 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1202 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1203 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1204 props->bad_pkey_cntr = rep->pkey_violation_counter; 1205 props->qkey_viol_cntr = rep->qkey_violation_counter; 1206 props->subnet_timeout = rep->subnet_timeout; 1207 props->init_type_reply = rep->init_type_reply; 1208 props->grh_required = rep->grh_required; 1209 1210 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1211 if (err) 1212 goto out; 1213 1214 err = translate_active_width(ibdev, ib_link_width_oper, 1215 &props->active_width); 1216 if (err) 1217 goto out; 1218 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1219 if (err) 1220 goto out; 1221 1222 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1223 1224 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1225 1226 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1227 1228 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1229 1230 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1231 if (err) 1232 goto out; 1233 1234 err = translate_max_vl_num(ibdev, vl_hw_cap, 1235 &props->max_vl_num); 1236 out: 1237 kfree(rep); 1238 return err; 1239 } 1240 1241 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1242 struct ib_port_attr *props) 1243 { 1244 unsigned int count; 1245 int ret; 1246 1247 switch (mlx5_get_vport_access_method(ibdev)) { 1248 case MLX5_VPORT_ACCESS_METHOD_MAD: 1249 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1250 break; 1251 1252 case MLX5_VPORT_ACCESS_METHOD_HCA: 1253 ret = mlx5_query_hca_port(ibdev, port, props); 1254 break; 1255 1256 case MLX5_VPORT_ACCESS_METHOD_NIC: 1257 ret = mlx5_query_port_roce(ibdev, port, props); 1258 break; 1259 1260 default: 1261 ret = -EINVAL; 1262 } 1263 1264 if (!ret && props) { 1265 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1266 struct mlx5_core_dev *mdev; 1267 bool put_mdev = true; 1268 1269 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1270 if (!mdev) { 1271 /* If the port isn't affiliated yet query the master. 1272 * The master and slave will have the same values. 1273 */ 1274 mdev = dev->mdev; 1275 port = 1; 1276 put_mdev = false; 1277 } 1278 count = mlx5_core_reserved_gids_count(mdev); 1279 if (put_mdev) 1280 mlx5_ib_put_native_port_mdev(dev, port); 1281 props->gid_tbl_len -= count; 1282 } 1283 return ret; 1284 } 1285 1286 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1287 struct ib_port_attr *props) 1288 { 1289 int ret; 1290 1291 /* Only link layer == ethernet is valid for representors */ 1292 ret = mlx5_query_port_roce(ibdev, port, props); 1293 if (ret || !props) 1294 return ret; 1295 1296 /* We don't support GIDS */ 1297 props->gid_tbl_len = 0; 1298 1299 return ret; 1300 } 1301 1302 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1303 union ib_gid *gid) 1304 { 1305 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1306 struct mlx5_core_dev *mdev = dev->mdev; 1307 1308 switch (mlx5_get_vport_access_method(ibdev)) { 1309 case MLX5_VPORT_ACCESS_METHOD_MAD: 1310 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1311 1312 case MLX5_VPORT_ACCESS_METHOD_HCA: 1313 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1314 1315 default: 1316 return -EINVAL; 1317 } 1318 1319 } 1320 1321 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1322 u16 index, u16 *pkey) 1323 { 1324 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1325 struct mlx5_core_dev *mdev; 1326 bool put_mdev = true; 1327 u8 mdev_port_num; 1328 int err; 1329 1330 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1331 if (!mdev) { 1332 /* The port isn't affiliated yet, get the PKey from the master 1333 * port. For RoCE the PKey tables will be the same. 1334 */ 1335 put_mdev = false; 1336 mdev = dev->mdev; 1337 mdev_port_num = 1; 1338 } 1339 1340 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1341 index, pkey); 1342 if (put_mdev) 1343 mlx5_ib_put_native_port_mdev(dev, port); 1344 1345 return err; 1346 } 1347 1348 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1349 u16 *pkey) 1350 { 1351 switch (mlx5_get_vport_access_method(ibdev)) { 1352 case MLX5_VPORT_ACCESS_METHOD_MAD: 1353 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1354 1355 case MLX5_VPORT_ACCESS_METHOD_HCA: 1356 case MLX5_VPORT_ACCESS_METHOD_NIC: 1357 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1358 default: 1359 return -EINVAL; 1360 } 1361 } 1362 1363 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1364 struct ib_device_modify *props) 1365 { 1366 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1367 struct mlx5_reg_node_desc in; 1368 struct mlx5_reg_node_desc out; 1369 int err; 1370 1371 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1372 return -EOPNOTSUPP; 1373 1374 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1375 return 0; 1376 1377 /* 1378 * If possible, pass node desc to FW, so it can generate 1379 * a 144 trap. If cmd fails, just ignore. 1380 */ 1381 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1382 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1383 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1384 if (err) 1385 return err; 1386 1387 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1388 1389 return err; 1390 } 1391 1392 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1393 u32 value) 1394 { 1395 struct mlx5_hca_vport_context ctx = {}; 1396 struct mlx5_core_dev *mdev; 1397 u8 mdev_port_num; 1398 int err; 1399 1400 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1401 if (!mdev) 1402 return -ENODEV; 1403 1404 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1405 if (err) 1406 goto out; 1407 1408 if (~ctx.cap_mask1_perm & mask) { 1409 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1410 mask, ctx.cap_mask1_perm); 1411 err = -EINVAL; 1412 goto out; 1413 } 1414 1415 ctx.cap_mask1 = value; 1416 ctx.cap_mask1_perm = mask; 1417 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1418 0, &ctx); 1419 1420 out: 1421 mlx5_ib_put_native_port_mdev(dev, port_num); 1422 1423 return err; 1424 } 1425 1426 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1427 struct ib_port_modify *props) 1428 { 1429 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1430 struct ib_port_attr attr; 1431 u32 tmp; 1432 int err; 1433 u32 change_mask; 1434 u32 value; 1435 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1436 IB_LINK_LAYER_INFINIBAND); 1437 1438 /* CM layer calls ib_modify_port() regardless of the link layer. For 1439 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1440 */ 1441 if (!is_ib) 1442 return 0; 1443 1444 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1445 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1446 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1447 return set_port_caps_atomic(dev, port, change_mask, value); 1448 } 1449 1450 mutex_lock(&dev->cap_mask_mutex); 1451 1452 err = ib_query_port(ibdev, port, &attr); 1453 if (err) 1454 goto out; 1455 1456 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1457 ~props->clr_port_cap_mask; 1458 1459 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1460 1461 out: 1462 mutex_unlock(&dev->cap_mask_mutex); 1463 return err; 1464 } 1465 1466 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1467 { 1468 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1469 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1470 } 1471 1472 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1473 { 1474 /* Large page with non 4k uar support might limit the dynamic size */ 1475 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1476 return MLX5_MIN_DYN_BFREGS; 1477 1478 return MLX5_MAX_DYN_BFREGS; 1479 } 1480 1481 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1482 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1483 struct mlx5_bfreg_info *bfregi) 1484 { 1485 int uars_per_sys_page; 1486 int bfregs_per_sys_page; 1487 int ref_bfregs = req->total_num_bfregs; 1488 1489 if (req->total_num_bfregs == 0) 1490 return -EINVAL; 1491 1492 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1493 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1494 1495 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1496 return -ENOMEM; 1497 1498 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1499 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1500 /* This holds the required static allocation asked by the user */ 1501 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1502 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1503 return -EINVAL; 1504 1505 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1506 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1507 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1508 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1509 1510 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1511 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1512 lib_uar_4k ? "yes" : "no", ref_bfregs, 1513 req->total_num_bfregs, bfregi->total_num_bfregs, 1514 bfregi->num_sys_pages); 1515 1516 return 0; 1517 } 1518 1519 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1520 { 1521 struct mlx5_bfreg_info *bfregi; 1522 int err; 1523 int i; 1524 1525 bfregi = &context->bfregi; 1526 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1527 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1528 if (err) 1529 goto error; 1530 1531 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1532 } 1533 1534 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1535 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1536 1537 return 0; 1538 1539 error: 1540 for (--i; i >= 0; i--) 1541 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1542 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1543 1544 return err; 1545 } 1546 1547 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1548 { 1549 struct mlx5_bfreg_info *bfregi; 1550 int err; 1551 int i; 1552 1553 bfregi = &context->bfregi; 1554 for (i = 0; i < bfregi->num_sys_pages; i++) { 1555 if (i < bfregi->num_static_sys_pages || 1556 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) { 1557 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1558 if (err) { 1559 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err); 1560 return err; 1561 } 1562 } 1563 } 1564 1565 return 0; 1566 } 1567 1568 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1569 { 1570 int err; 1571 1572 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1573 if (err) 1574 return err; 1575 1576 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1577 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1578 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1579 return err; 1580 1581 mutex_lock(&dev->lb_mutex); 1582 dev->user_td++; 1583 1584 if (dev->user_td == 2) 1585 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1586 1587 mutex_unlock(&dev->lb_mutex); 1588 return err; 1589 } 1590 1591 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1592 { 1593 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1594 1595 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1596 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1597 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1598 return; 1599 1600 mutex_lock(&dev->lb_mutex); 1601 dev->user_td--; 1602 1603 if (dev->user_td < 2) 1604 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1605 1606 mutex_unlock(&dev->lb_mutex); 1607 } 1608 1609 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1610 struct ib_udata *udata) 1611 { 1612 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1613 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1614 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1615 struct mlx5_core_dev *mdev = dev->mdev; 1616 struct mlx5_ib_ucontext *context; 1617 struct mlx5_bfreg_info *bfregi; 1618 int ver; 1619 int err; 1620 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1621 max_cqe_version); 1622 bool lib_uar_4k; 1623 1624 if (!dev->ib_active) 1625 return ERR_PTR(-EAGAIN); 1626 1627 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1628 ver = 0; 1629 else if (udata->inlen >= min_req_v2) 1630 ver = 2; 1631 else 1632 return ERR_PTR(-EINVAL); 1633 1634 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1635 if (err) 1636 return ERR_PTR(err); 1637 1638 if (req.flags) 1639 return ERR_PTR(-EINVAL); 1640 1641 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1642 return ERR_PTR(-EOPNOTSUPP); 1643 1644 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1645 MLX5_NON_FP_BFREGS_PER_UAR); 1646 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1647 return ERR_PTR(-EINVAL); 1648 1649 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1650 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1651 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1652 resp.cache_line_size = cache_line_size(); 1653 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1654 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1655 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1656 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1657 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1658 resp.cqe_version = min_t(__u8, 1659 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1660 req.max_cqe_version); 1661 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1662 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1663 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1664 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1665 resp.response_length = min(offsetof(typeof(resp), response_length) + 1666 sizeof(resp.response_length), udata->outlen); 1667 1668 context = kzalloc(sizeof(*context), GFP_KERNEL); 1669 if (!context) 1670 return ERR_PTR(-ENOMEM); 1671 1672 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1673 bfregi = &context->bfregi; 1674 1675 /* updates req->total_num_bfregs */ 1676 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1677 if (err) 1678 goto out_ctx; 1679 1680 mutex_init(&bfregi->lock); 1681 bfregi->lib_uar_4k = lib_uar_4k; 1682 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1683 GFP_KERNEL); 1684 if (!bfregi->count) { 1685 err = -ENOMEM; 1686 goto out_ctx; 1687 } 1688 1689 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1690 sizeof(*bfregi->sys_pages), 1691 GFP_KERNEL); 1692 if (!bfregi->sys_pages) { 1693 err = -ENOMEM; 1694 goto out_count; 1695 } 1696 1697 err = allocate_uars(dev, context); 1698 if (err) 1699 goto out_sys_pages; 1700 1701 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1702 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1703 #endif 1704 1705 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1706 if (!context->upd_xlt_page) { 1707 err = -ENOMEM; 1708 goto out_uars; 1709 } 1710 mutex_init(&context->upd_xlt_page_mutex); 1711 1712 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1713 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1714 if (err) 1715 goto out_page; 1716 } 1717 1718 INIT_LIST_HEAD(&context->vma_private_list); 1719 mutex_init(&context->vma_private_list_mutex); 1720 INIT_LIST_HEAD(&context->db_page_list); 1721 mutex_init(&context->db_page_mutex); 1722 1723 resp.tot_bfregs = req.total_num_bfregs; 1724 resp.num_ports = dev->num_ports; 1725 1726 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1727 resp.response_length += sizeof(resp.cqe_version); 1728 1729 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1730 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1731 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1732 resp.response_length += sizeof(resp.cmds_supp_uhw); 1733 } 1734 1735 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1736 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1737 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1738 resp.eth_min_inline++; 1739 } 1740 resp.response_length += sizeof(resp.eth_min_inline); 1741 } 1742 1743 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1744 if (mdev->clock_info) 1745 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1746 resp.response_length += sizeof(resp.clock_info_versions); 1747 } 1748 1749 /* 1750 * We don't want to expose information from the PCI bar that is located 1751 * after 4096 bytes, so if the arch only supports larger pages, let's 1752 * pretend we don't support reading the HCA's core clock. This is also 1753 * forced by mmap function. 1754 */ 1755 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1756 if (PAGE_SIZE <= 4096) { 1757 resp.comp_mask |= 1758 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1759 resp.hca_core_clock_offset = 1760 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1761 } 1762 resp.response_length += sizeof(resp.hca_core_clock_offset); 1763 } 1764 1765 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1766 resp.response_length += sizeof(resp.log_uar_size); 1767 1768 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1769 resp.response_length += sizeof(resp.num_uars_per_page); 1770 1771 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1772 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1773 resp.response_length += sizeof(resp.num_dyn_bfregs); 1774 } 1775 1776 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1777 if (err) 1778 goto out_td; 1779 1780 bfregi->ver = ver; 1781 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1782 context->cqe_version = resp.cqe_version; 1783 context->lib_caps = req.lib_caps; 1784 print_lib_caps(dev, context->lib_caps); 1785 1786 return &context->ibucontext; 1787 1788 out_td: 1789 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1790 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1791 1792 out_page: 1793 free_page(context->upd_xlt_page); 1794 1795 out_uars: 1796 deallocate_uars(dev, context); 1797 1798 out_sys_pages: 1799 kfree(bfregi->sys_pages); 1800 1801 out_count: 1802 kfree(bfregi->count); 1803 1804 out_ctx: 1805 kfree(context); 1806 1807 return ERR_PTR(err); 1808 } 1809 1810 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1811 { 1812 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1813 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1814 struct mlx5_bfreg_info *bfregi; 1815 1816 bfregi = &context->bfregi; 1817 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1818 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1819 1820 free_page(context->upd_xlt_page); 1821 deallocate_uars(dev, context); 1822 kfree(bfregi->sys_pages); 1823 kfree(bfregi->count); 1824 kfree(context); 1825 1826 return 0; 1827 } 1828 1829 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1830 int uar_idx) 1831 { 1832 int fw_uars_per_page; 1833 1834 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1835 1836 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1837 } 1838 1839 static int get_command(unsigned long offset) 1840 { 1841 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1842 } 1843 1844 static int get_arg(unsigned long offset) 1845 { 1846 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1847 } 1848 1849 static int get_index(unsigned long offset) 1850 { 1851 return get_arg(offset); 1852 } 1853 1854 /* Index resides in an extra byte to enable larger values than 255 */ 1855 static int get_extended_index(unsigned long offset) 1856 { 1857 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1858 } 1859 1860 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1861 { 1862 /* vma_open is called when a new VMA is created on top of our VMA. This 1863 * is done through either mremap flow or split_vma (usually due to 1864 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1865 * as this VMA is strongly hardware related. Therefore we set the 1866 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1867 * calling us again and trying to do incorrect actions. We assume that 1868 * the original VMA size is exactly a single page, and therefore all 1869 * "splitting" operation will not happen to it. 1870 */ 1871 area->vm_ops = NULL; 1872 } 1873 1874 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1875 { 1876 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1877 1878 /* It's guaranteed that all VMAs opened on a FD are closed before the 1879 * file itself is closed, therefore no sync is needed with the regular 1880 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1881 * However need a sync with accessing the vma as part of 1882 * mlx5_ib_disassociate_ucontext. 1883 * The close operation is usually called under mm->mmap_sem except when 1884 * process is exiting. 1885 * The exiting case is handled explicitly as part of 1886 * mlx5_ib_disassociate_ucontext. 1887 */ 1888 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1889 1890 /* setting the vma context pointer to null in the mlx5_ib driver's 1891 * private data, to protect a race condition in 1892 * mlx5_ib_disassociate_ucontext(). 1893 */ 1894 mlx5_ib_vma_priv_data->vma = NULL; 1895 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1896 list_del(&mlx5_ib_vma_priv_data->list); 1897 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1898 kfree(mlx5_ib_vma_priv_data); 1899 } 1900 1901 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1902 .open = mlx5_ib_vma_open, 1903 .close = mlx5_ib_vma_close 1904 }; 1905 1906 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1907 struct mlx5_ib_ucontext *ctx) 1908 { 1909 struct mlx5_ib_vma_private_data *vma_prv; 1910 struct list_head *vma_head = &ctx->vma_private_list; 1911 1912 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1913 if (!vma_prv) 1914 return -ENOMEM; 1915 1916 vma_prv->vma = vma; 1917 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex; 1918 vma->vm_private_data = vma_prv; 1919 vma->vm_ops = &mlx5_ib_vm_ops; 1920 1921 mutex_lock(&ctx->vma_private_list_mutex); 1922 list_add(&vma_prv->list, vma_head); 1923 mutex_unlock(&ctx->vma_private_list_mutex); 1924 1925 return 0; 1926 } 1927 1928 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1929 { 1930 int ret; 1931 struct vm_area_struct *vma; 1932 struct mlx5_ib_vma_private_data *vma_private, *n; 1933 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1934 struct task_struct *owning_process = NULL; 1935 struct mm_struct *owning_mm = NULL; 1936 1937 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1938 if (!owning_process) 1939 return; 1940 1941 owning_mm = get_task_mm(owning_process); 1942 if (!owning_mm) { 1943 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1944 while (1) { 1945 put_task_struct(owning_process); 1946 usleep_range(1000, 2000); 1947 owning_process = get_pid_task(ibcontext->tgid, 1948 PIDTYPE_PID); 1949 if (!owning_process || 1950 owning_process->state == TASK_DEAD) { 1951 pr_info("disassociate ucontext done, task was terminated\n"); 1952 /* in case task was dead need to release the 1953 * task struct. 1954 */ 1955 if (owning_process) 1956 put_task_struct(owning_process); 1957 return; 1958 } 1959 } 1960 } 1961 1962 /* need to protect from a race on closing the vma as part of 1963 * mlx5_ib_vma_close. 1964 */ 1965 down_write(&owning_mm->mmap_sem); 1966 mutex_lock(&context->vma_private_list_mutex); 1967 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1968 list) { 1969 vma = vma_private->vma; 1970 ret = zap_vma_ptes(vma, vma->vm_start, 1971 PAGE_SIZE); 1972 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1973 /* context going to be destroyed, should 1974 * not access ops any more. 1975 */ 1976 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1977 vma->vm_ops = NULL; 1978 list_del(&vma_private->list); 1979 kfree(vma_private); 1980 } 1981 mutex_unlock(&context->vma_private_list_mutex); 1982 up_write(&owning_mm->mmap_sem); 1983 mmput(owning_mm); 1984 put_task_struct(owning_process); 1985 } 1986 1987 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1988 { 1989 switch (cmd) { 1990 case MLX5_IB_MMAP_WC_PAGE: 1991 return "WC"; 1992 case MLX5_IB_MMAP_REGULAR_PAGE: 1993 return "best effort WC"; 1994 case MLX5_IB_MMAP_NC_PAGE: 1995 return "NC"; 1996 default: 1997 return NULL; 1998 } 1999 } 2000 2001 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2002 struct vm_area_struct *vma, 2003 struct mlx5_ib_ucontext *context) 2004 { 2005 phys_addr_t pfn; 2006 int err; 2007 2008 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2009 return -EINVAL; 2010 2011 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2012 return -EOPNOTSUPP; 2013 2014 if (vma->vm_flags & VM_WRITE) 2015 return -EPERM; 2016 2017 if (!dev->mdev->clock_info_page) 2018 return -EOPNOTSUPP; 2019 2020 pfn = page_to_pfn(dev->mdev->clock_info_page); 2021 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE, 2022 vma->vm_page_prot); 2023 if (err) 2024 return err; 2025 2026 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n", 2027 vma->vm_start, 2028 (unsigned long long)pfn << PAGE_SHIFT); 2029 2030 return mlx5_ib_set_vma_data(vma, context); 2031 } 2032 2033 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2034 struct vm_area_struct *vma, 2035 struct mlx5_ib_ucontext *context) 2036 { 2037 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2038 int err; 2039 unsigned long idx; 2040 phys_addr_t pfn, pa; 2041 pgprot_t prot; 2042 u32 bfreg_dyn_idx = 0; 2043 u32 uar_index; 2044 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2045 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2046 bfregi->num_static_sys_pages; 2047 2048 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2049 return -EINVAL; 2050 2051 if (dyn_uar) 2052 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2053 else 2054 idx = get_index(vma->vm_pgoff); 2055 2056 if (idx >= max_valid_idx) { 2057 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2058 idx, max_valid_idx); 2059 return -EINVAL; 2060 } 2061 2062 switch (cmd) { 2063 case MLX5_IB_MMAP_WC_PAGE: 2064 case MLX5_IB_MMAP_ALLOC_WC: 2065 /* Some architectures don't support WC memory */ 2066 #if defined(CONFIG_X86) 2067 if (!pat_enabled()) 2068 return -EPERM; 2069 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2070 return -EPERM; 2071 #endif 2072 /* fall through */ 2073 case MLX5_IB_MMAP_REGULAR_PAGE: 2074 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2075 prot = pgprot_writecombine(vma->vm_page_prot); 2076 break; 2077 case MLX5_IB_MMAP_NC_PAGE: 2078 prot = pgprot_noncached(vma->vm_page_prot); 2079 break; 2080 default: 2081 return -EINVAL; 2082 } 2083 2084 if (dyn_uar) { 2085 int uars_per_page; 2086 2087 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2088 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2089 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2090 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2091 bfreg_dyn_idx, bfregi->total_num_bfregs); 2092 return -EINVAL; 2093 } 2094 2095 mutex_lock(&bfregi->lock); 2096 /* Fail if uar already allocated, first bfreg index of each 2097 * page holds its count. 2098 */ 2099 if (bfregi->count[bfreg_dyn_idx]) { 2100 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2101 mutex_unlock(&bfregi->lock); 2102 return -EINVAL; 2103 } 2104 2105 bfregi->count[bfreg_dyn_idx]++; 2106 mutex_unlock(&bfregi->lock); 2107 2108 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2109 if (err) { 2110 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2111 goto free_bfreg; 2112 } 2113 } else { 2114 uar_index = bfregi->sys_pages[idx]; 2115 } 2116 2117 pfn = uar_index2pfn(dev, uar_index); 2118 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2119 2120 vma->vm_page_prot = prot; 2121 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 2122 PAGE_SIZE, vma->vm_page_prot); 2123 if (err) { 2124 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 2125 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 2126 err = -EAGAIN; 2127 goto err; 2128 } 2129 2130 pa = pfn << PAGE_SHIFT; 2131 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 2132 vma->vm_start, &pa); 2133 2134 err = mlx5_ib_set_vma_data(vma, context); 2135 if (err) 2136 goto err; 2137 2138 if (dyn_uar) 2139 bfregi->sys_pages[idx] = uar_index; 2140 return 0; 2141 2142 err: 2143 if (!dyn_uar) 2144 return err; 2145 2146 mlx5_cmd_free_uar(dev->mdev, idx); 2147 2148 free_bfreg: 2149 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2150 2151 return err; 2152 } 2153 2154 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2155 { 2156 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2157 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2158 unsigned long command; 2159 phys_addr_t pfn; 2160 2161 command = get_command(vma->vm_pgoff); 2162 switch (command) { 2163 case MLX5_IB_MMAP_WC_PAGE: 2164 case MLX5_IB_MMAP_NC_PAGE: 2165 case MLX5_IB_MMAP_REGULAR_PAGE: 2166 case MLX5_IB_MMAP_ALLOC_WC: 2167 return uar_mmap(dev, command, vma, context); 2168 2169 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2170 return -ENOSYS; 2171 2172 case MLX5_IB_MMAP_CORE_CLOCK: 2173 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2174 return -EINVAL; 2175 2176 if (vma->vm_flags & VM_WRITE) 2177 return -EPERM; 2178 2179 /* Don't expose to user-space information it shouldn't have */ 2180 if (PAGE_SIZE > 4096) 2181 return -EOPNOTSUPP; 2182 2183 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2184 pfn = (dev->mdev->iseg_base + 2185 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2186 PAGE_SHIFT; 2187 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2188 PAGE_SIZE, vma->vm_page_prot)) 2189 return -EAGAIN; 2190 2191 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 2192 vma->vm_start, 2193 (unsigned long long)pfn << PAGE_SHIFT); 2194 break; 2195 case MLX5_IB_MMAP_CLOCK_INFO: 2196 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2197 2198 default: 2199 return -EINVAL; 2200 } 2201 2202 return 0; 2203 } 2204 2205 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2206 struct ib_ucontext *context, 2207 struct ib_udata *udata) 2208 { 2209 struct mlx5_ib_alloc_pd_resp resp; 2210 struct mlx5_ib_pd *pd; 2211 int err; 2212 2213 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2214 if (!pd) 2215 return ERR_PTR(-ENOMEM); 2216 2217 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 2218 if (err) { 2219 kfree(pd); 2220 return ERR_PTR(err); 2221 } 2222 2223 if (context) { 2224 resp.pdn = pd->pdn; 2225 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2226 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 2227 kfree(pd); 2228 return ERR_PTR(-EFAULT); 2229 } 2230 } 2231 2232 return &pd->ibpd; 2233 } 2234 2235 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2236 { 2237 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2238 struct mlx5_ib_pd *mpd = to_mpd(pd); 2239 2240 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 2241 kfree(mpd); 2242 2243 return 0; 2244 } 2245 2246 enum { 2247 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2248 MATCH_CRITERIA_ENABLE_MISC_BIT, 2249 MATCH_CRITERIA_ENABLE_INNER_BIT 2250 }; 2251 2252 #define HEADER_IS_ZERO(match_criteria, headers) \ 2253 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2254 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2255 2256 static u8 get_match_criteria_enable(u32 *match_criteria) 2257 { 2258 u8 match_criteria_enable; 2259 2260 match_criteria_enable = 2261 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2262 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2263 match_criteria_enable |= 2264 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2265 MATCH_CRITERIA_ENABLE_MISC_BIT; 2266 match_criteria_enable |= 2267 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2268 MATCH_CRITERIA_ENABLE_INNER_BIT; 2269 2270 return match_criteria_enable; 2271 } 2272 2273 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2274 { 2275 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2276 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2277 } 2278 2279 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 2280 bool inner) 2281 { 2282 if (inner) { 2283 MLX5_SET(fte_match_set_misc, 2284 misc_c, inner_ipv6_flow_label, mask); 2285 MLX5_SET(fte_match_set_misc, 2286 misc_v, inner_ipv6_flow_label, val); 2287 } else { 2288 MLX5_SET(fte_match_set_misc, 2289 misc_c, outer_ipv6_flow_label, mask); 2290 MLX5_SET(fte_match_set_misc, 2291 misc_v, outer_ipv6_flow_label, val); 2292 } 2293 } 2294 2295 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2296 { 2297 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2298 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2299 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2300 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2301 } 2302 2303 #define LAST_ETH_FIELD vlan_tag 2304 #define LAST_IB_FIELD sl 2305 #define LAST_IPV4_FIELD tos 2306 #define LAST_IPV6_FIELD traffic_class 2307 #define LAST_TCP_UDP_FIELD src_port 2308 #define LAST_TUNNEL_FIELD tunnel_id 2309 #define LAST_FLOW_TAG_FIELD tag_id 2310 #define LAST_DROP_FIELD size 2311 2312 /* Field is the last supported field */ 2313 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2314 memchr_inv((void *)&filter.field +\ 2315 sizeof(filter.field), 0,\ 2316 sizeof(filter) -\ 2317 offsetof(typeof(filter), field) -\ 2318 sizeof(filter.field)) 2319 2320 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2321 u32 *match_v, const union ib_flow_spec *ib_spec, 2322 struct mlx5_flow_act *action) 2323 { 2324 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2325 misc_parameters); 2326 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2327 misc_parameters); 2328 void *headers_c; 2329 void *headers_v; 2330 int match_ipv; 2331 2332 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2333 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2334 inner_headers); 2335 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2336 inner_headers); 2337 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2338 ft_field_support.inner_ip_version); 2339 } else { 2340 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2341 outer_headers); 2342 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2343 outer_headers); 2344 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2345 ft_field_support.outer_ip_version); 2346 } 2347 2348 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2349 case IB_FLOW_SPEC_ETH: 2350 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2351 return -EOPNOTSUPP; 2352 2353 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2354 dmac_47_16), 2355 ib_spec->eth.mask.dst_mac); 2356 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2357 dmac_47_16), 2358 ib_spec->eth.val.dst_mac); 2359 2360 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2361 smac_47_16), 2362 ib_spec->eth.mask.src_mac); 2363 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2364 smac_47_16), 2365 ib_spec->eth.val.src_mac); 2366 2367 if (ib_spec->eth.mask.vlan_tag) { 2368 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2369 cvlan_tag, 1); 2370 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2371 cvlan_tag, 1); 2372 2373 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2374 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2375 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2376 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2377 2378 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2379 first_cfi, 2380 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2381 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2382 first_cfi, 2383 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2384 2385 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2386 first_prio, 2387 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2388 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2389 first_prio, 2390 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2391 } 2392 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2393 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2394 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2395 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2396 break; 2397 case IB_FLOW_SPEC_IPV4: 2398 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2399 return -EOPNOTSUPP; 2400 2401 if (match_ipv) { 2402 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2403 ip_version, 0xf); 2404 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2405 ip_version, MLX5_FS_IPV4_VERSION); 2406 } else { 2407 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2408 ethertype, 0xffff); 2409 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2410 ethertype, ETH_P_IP); 2411 } 2412 2413 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2414 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2415 &ib_spec->ipv4.mask.src_ip, 2416 sizeof(ib_spec->ipv4.mask.src_ip)); 2417 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2418 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2419 &ib_spec->ipv4.val.src_ip, 2420 sizeof(ib_spec->ipv4.val.src_ip)); 2421 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2422 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2423 &ib_spec->ipv4.mask.dst_ip, 2424 sizeof(ib_spec->ipv4.mask.dst_ip)); 2425 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2426 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2427 &ib_spec->ipv4.val.dst_ip, 2428 sizeof(ib_spec->ipv4.val.dst_ip)); 2429 2430 set_tos(headers_c, headers_v, 2431 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2432 2433 set_proto(headers_c, headers_v, 2434 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2435 break; 2436 case IB_FLOW_SPEC_IPV6: 2437 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2438 return -EOPNOTSUPP; 2439 2440 if (match_ipv) { 2441 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2442 ip_version, 0xf); 2443 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2444 ip_version, MLX5_FS_IPV6_VERSION); 2445 } else { 2446 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2447 ethertype, 0xffff); 2448 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2449 ethertype, ETH_P_IPV6); 2450 } 2451 2452 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2453 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2454 &ib_spec->ipv6.mask.src_ip, 2455 sizeof(ib_spec->ipv6.mask.src_ip)); 2456 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2457 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2458 &ib_spec->ipv6.val.src_ip, 2459 sizeof(ib_spec->ipv6.val.src_ip)); 2460 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2461 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2462 &ib_spec->ipv6.mask.dst_ip, 2463 sizeof(ib_spec->ipv6.mask.dst_ip)); 2464 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2465 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2466 &ib_spec->ipv6.val.dst_ip, 2467 sizeof(ib_spec->ipv6.val.dst_ip)); 2468 2469 set_tos(headers_c, headers_v, 2470 ib_spec->ipv6.mask.traffic_class, 2471 ib_spec->ipv6.val.traffic_class); 2472 2473 set_proto(headers_c, headers_v, 2474 ib_spec->ipv6.mask.next_hdr, 2475 ib_spec->ipv6.val.next_hdr); 2476 2477 set_flow_label(misc_params_c, misc_params_v, 2478 ntohl(ib_spec->ipv6.mask.flow_label), 2479 ntohl(ib_spec->ipv6.val.flow_label), 2480 ib_spec->type & IB_FLOW_SPEC_INNER); 2481 2482 break; 2483 case IB_FLOW_SPEC_TCP: 2484 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2485 LAST_TCP_UDP_FIELD)) 2486 return -EOPNOTSUPP; 2487 2488 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2489 0xff); 2490 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2491 IPPROTO_TCP); 2492 2493 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2494 ntohs(ib_spec->tcp_udp.mask.src_port)); 2495 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2496 ntohs(ib_spec->tcp_udp.val.src_port)); 2497 2498 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2499 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2501 ntohs(ib_spec->tcp_udp.val.dst_port)); 2502 break; 2503 case IB_FLOW_SPEC_UDP: 2504 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2505 LAST_TCP_UDP_FIELD)) 2506 return -EOPNOTSUPP; 2507 2508 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2509 0xff); 2510 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2511 IPPROTO_UDP); 2512 2513 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2514 ntohs(ib_spec->tcp_udp.mask.src_port)); 2515 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2516 ntohs(ib_spec->tcp_udp.val.src_port)); 2517 2518 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2519 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2521 ntohs(ib_spec->tcp_udp.val.dst_port)); 2522 break; 2523 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2524 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2525 LAST_TUNNEL_FIELD)) 2526 return -EOPNOTSUPP; 2527 2528 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2529 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2530 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2531 ntohl(ib_spec->tunnel.val.tunnel_id)); 2532 break; 2533 case IB_FLOW_SPEC_ACTION_TAG: 2534 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2535 LAST_FLOW_TAG_FIELD)) 2536 return -EOPNOTSUPP; 2537 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2538 return -EINVAL; 2539 2540 action->flow_tag = ib_spec->flow_tag.tag_id; 2541 action->has_flow_tag = true; 2542 break; 2543 case IB_FLOW_SPEC_ACTION_DROP: 2544 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2545 LAST_DROP_FIELD)) 2546 return -EOPNOTSUPP; 2547 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2548 break; 2549 default: 2550 return -EINVAL; 2551 } 2552 2553 return 0; 2554 } 2555 2556 /* If a flow could catch both multicast and unicast packets, 2557 * it won't fall into the multicast flow steering table and this rule 2558 * could steal other multicast packets. 2559 */ 2560 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2561 { 2562 union ib_flow_spec *flow_spec; 2563 2564 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2565 ib_attr->num_of_specs < 1) 2566 return false; 2567 2568 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2569 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2570 struct ib_flow_spec_ipv4 *ipv4_spec; 2571 2572 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2573 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2574 return true; 2575 2576 return false; 2577 } 2578 2579 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2580 struct ib_flow_spec_eth *eth_spec; 2581 2582 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2583 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2584 is_multicast_ether_addr(eth_spec->val.dst_mac); 2585 } 2586 2587 return false; 2588 } 2589 2590 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2591 const struct ib_flow_attr *flow_attr, 2592 bool check_inner) 2593 { 2594 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2595 int match_ipv = check_inner ? 2596 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2597 ft_field_support.inner_ip_version) : 2598 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2599 ft_field_support.outer_ip_version); 2600 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2601 bool ipv4_spec_valid, ipv6_spec_valid; 2602 unsigned int ip_spec_type = 0; 2603 bool has_ethertype = false; 2604 unsigned int spec_index; 2605 bool mask_valid = true; 2606 u16 eth_type = 0; 2607 bool type_valid; 2608 2609 /* Validate that ethertype is correct */ 2610 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2611 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2612 ib_spec->eth.mask.ether_type) { 2613 mask_valid = (ib_spec->eth.mask.ether_type == 2614 htons(0xffff)); 2615 has_ethertype = true; 2616 eth_type = ntohs(ib_spec->eth.val.ether_type); 2617 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2618 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2619 ip_spec_type = ib_spec->type; 2620 } 2621 ib_spec = (void *)ib_spec + ib_spec->size; 2622 } 2623 2624 type_valid = (!has_ethertype) || (!ip_spec_type); 2625 if (!type_valid && mask_valid) { 2626 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2627 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2628 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2629 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2630 2631 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2632 (((eth_type == ETH_P_MPLS_UC) || 2633 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2634 } 2635 2636 return type_valid; 2637 } 2638 2639 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2640 const struct ib_flow_attr *flow_attr) 2641 { 2642 return is_valid_ethertype(mdev, flow_attr, false) && 2643 is_valid_ethertype(mdev, flow_attr, true); 2644 } 2645 2646 static void put_flow_table(struct mlx5_ib_dev *dev, 2647 struct mlx5_ib_flow_prio *prio, bool ft_added) 2648 { 2649 prio->refcount -= !!ft_added; 2650 if (!prio->refcount) { 2651 mlx5_destroy_flow_table(prio->flow_table); 2652 prio->flow_table = NULL; 2653 } 2654 } 2655 2656 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2657 { 2658 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2659 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2660 struct mlx5_ib_flow_handler, 2661 ibflow); 2662 struct mlx5_ib_flow_handler *iter, *tmp; 2663 2664 mutex_lock(&dev->flow_db->lock); 2665 2666 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2667 mlx5_del_flow_rules(iter->rule); 2668 put_flow_table(dev, iter->prio, true); 2669 list_del(&iter->list); 2670 kfree(iter); 2671 } 2672 2673 mlx5_del_flow_rules(handler->rule); 2674 put_flow_table(dev, handler->prio, true); 2675 mutex_unlock(&dev->flow_db->lock); 2676 2677 kfree(handler); 2678 2679 return 0; 2680 } 2681 2682 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2683 { 2684 priority *= 2; 2685 if (!dont_trap) 2686 priority++; 2687 return priority; 2688 } 2689 2690 enum flow_table_type { 2691 MLX5_IB_FT_RX, 2692 MLX5_IB_FT_TX 2693 }; 2694 2695 #define MLX5_FS_MAX_TYPES 6 2696 #define MLX5_FS_MAX_ENTRIES BIT(16) 2697 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2698 struct ib_flow_attr *flow_attr, 2699 enum flow_table_type ft_type) 2700 { 2701 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2702 struct mlx5_flow_namespace *ns = NULL; 2703 struct mlx5_ib_flow_prio *prio; 2704 struct mlx5_flow_table *ft; 2705 int max_table_size; 2706 int num_entries; 2707 int num_groups; 2708 int priority; 2709 int err = 0; 2710 2711 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2712 log_max_ft_size)); 2713 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2714 if (flow_is_multicast_only(flow_attr) && 2715 !dont_trap) 2716 priority = MLX5_IB_FLOW_MCAST_PRIO; 2717 else 2718 priority = ib_prio_to_core_prio(flow_attr->priority, 2719 dont_trap); 2720 ns = mlx5_get_flow_namespace(dev->mdev, 2721 MLX5_FLOW_NAMESPACE_BYPASS); 2722 num_entries = MLX5_FS_MAX_ENTRIES; 2723 num_groups = MLX5_FS_MAX_TYPES; 2724 prio = &dev->flow_db->prios[priority]; 2725 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2726 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2727 ns = mlx5_get_flow_namespace(dev->mdev, 2728 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2729 build_leftovers_ft_param(&priority, 2730 &num_entries, 2731 &num_groups); 2732 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2733 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2734 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2735 allow_sniffer_and_nic_rx_shared_tir)) 2736 return ERR_PTR(-ENOTSUPP); 2737 2738 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2739 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2740 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2741 2742 prio = &dev->flow_db->sniffer[ft_type]; 2743 priority = 0; 2744 num_entries = 1; 2745 num_groups = 1; 2746 } 2747 2748 if (!ns) 2749 return ERR_PTR(-ENOTSUPP); 2750 2751 if (num_entries > max_table_size) 2752 return ERR_PTR(-ENOMEM); 2753 2754 ft = prio->flow_table; 2755 if (!ft) { 2756 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2757 num_entries, 2758 num_groups, 2759 0, 0); 2760 2761 if (!IS_ERR(ft)) { 2762 prio->refcount = 0; 2763 prio->flow_table = ft; 2764 } else { 2765 err = PTR_ERR(ft); 2766 } 2767 } 2768 2769 return err ? ERR_PTR(err) : prio; 2770 } 2771 2772 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2773 struct mlx5_flow_spec *spec, 2774 u32 underlay_qpn) 2775 { 2776 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2777 spec->match_criteria, 2778 misc_parameters); 2779 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2780 misc_parameters); 2781 2782 if (underlay_qpn && 2783 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2784 ft_field_support.bth_dst_qp)) { 2785 MLX5_SET(fte_match_set_misc, 2786 misc_params_v, bth_dst_qp, underlay_qpn); 2787 MLX5_SET(fte_match_set_misc, 2788 misc_params_c, bth_dst_qp, 0xffffff); 2789 } 2790 } 2791 2792 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 2793 struct mlx5_ib_flow_prio *ft_prio, 2794 const struct ib_flow_attr *flow_attr, 2795 struct mlx5_flow_destination *dst, 2796 u32 underlay_qpn) 2797 { 2798 struct mlx5_flow_table *ft = ft_prio->flow_table; 2799 struct mlx5_ib_flow_handler *handler; 2800 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 2801 struct mlx5_flow_spec *spec; 2802 struct mlx5_flow_destination *rule_dst = dst; 2803 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2804 unsigned int spec_index; 2805 int err = 0; 2806 int dest_num = 1; 2807 2808 if (!is_valid_attr(dev->mdev, flow_attr)) 2809 return ERR_PTR(-EINVAL); 2810 2811 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2812 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2813 if (!handler || !spec) { 2814 err = -ENOMEM; 2815 goto free; 2816 } 2817 2818 INIT_LIST_HEAD(&handler->list); 2819 2820 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2821 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2822 spec->match_value, 2823 ib_flow, &flow_act); 2824 if (err < 0) 2825 goto free; 2826 2827 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2828 } 2829 2830 if (!flow_is_multicast_only(flow_attr)) 2831 set_underlay_qp(dev, spec, underlay_qpn); 2832 2833 if (dev->rep) { 2834 void *misc; 2835 2836 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2837 misc_parameters); 2838 MLX5_SET(fte_match_set_misc, misc, source_port, 2839 dev->rep->vport); 2840 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 2841 misc_parameters); 2842 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 2843 } 2844 2845 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2846 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 2847 rule_dst = NULL; 2848 dest_num = 0; 2849 } else { 2850 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2851 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2852 } 2853 2854 if (flow_act.has_flow_tag && 2855 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2856 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2857 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2858 flow_act.flow_tag, flow_attr->type); 2859 err = -EINVAL; 2860 goto free; 2861 } 2862 handler->rule = mlx5_add_flow_rules(ft, spec, 2863 &flow_act, 2864 rule_dst, dest_num); 2865 2866 if (IS_ERR(handler->rule)) { 2867 err = PTR_ERR(handler->rule); 2868 goto free; 2869 } 2870 2871 ft_prio->refcount++; 2872 handler->prio = ft_prio; 2873 2874 ft_prio->flow_table = ft; 2875 free: 2876 if (err) 2877 kfree(handler); 2878 kvfree(spec); 2879 return err ? ERR_PTR(err) : handler; 2880 } 2881 2882 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2883 struct mlx5_ib_flow_prio *ft_prio, 2884 const struct ib_flow_attr *flow_attr, 2885 struct mlx5_flow_destination *dst) 2886 { 2887 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 2888 } 2889 2890 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2891 struct mlx5_ib_flow_prio *ft_prio, 2892 struct ib_flow_attr *flow_attr, 2893 struct mlx5_flow_destination *dst) 2894 { 2895 struct mlx5_ib_flow_handler *handler_dst = NULL; 2896 struct mlx5_ib_flow_handler *handler = NULL; 2897 2898 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2899 if (!IS_ERR(handler)) { 2900 handler_dst = create_flow_rule(dev, ft_prio, 2901 flow_attr, dst); 2902 if (IS_ERR(handler_dst)) { 2903 mlx5_del_flow_rules(handler->rule); 2904 ft_prio->refcount--; 2905 kfree(handler); 2906 handler = handler_dst; 2907 } else { 2908 list_add(&handler_dst->list, &handler->list); 2909 } 2910 } 2911 2912 return handler; 2913 } 2914 enum { 2915 LEFTOVERS_MC, 2916 LEFTOVERS_UC, 2917 }; 2918 2919 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2920 struct mlx5_ib_flow_prio *ft_prio, 2921 struct ib_flow_attr *flow_attr, 2922 struct mlx5_flow_destination *dst) 2923 { 2924 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2925 struct mlx5_ib_flow_handler *handler = NULL; 2926 2927 static struct { 2928 struct ib_flow_attr flow_attr; 2929 struct ib_flow_spec_eth eth_flow; 2930 } leftovers_specs[] = { 2931 [LEFTOVERS_MC] = { 2932 .flow_attr = { 2933 .num_of_specs = 1, 2934 .size = sizeof(leftovers_specs[0]) 2935 }, 2936 .eth_flow = { 2937 .type = IB_FLOW_SPEC_ETH, 2938 .size = sizeof(struct ib_flow_spec_eth), 2939 .mask = {.dst_mac = {0x1} }, 2940 .val = {.dst_mac = {0x1} } 2941 } 2942 }, 2943 [LEFTOVERS_UC] = { 2944 .flow_attr = { 2945 .num_of_specs = 1, 2946 .size = sizeof(leftovers_specs[0]) 2947 }, 2948 .eth_flow = { 2949 .type = IB_FLOW_SPEC_ETH, 2950 .size = sizeof(struct ib_flow_spec_eth), 2951 .mask = {.dst_mac = {0x1} }, 2952 .val = {.dst_mac = {} } 2953 } 2954 } 2955 }; 2956 2957 handler = create_flow_rule(dev, ft_prio, 2958 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2959 dst); 2960 if (!IS_ERR(handler) && 2961 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2962 handler_ucast = create_flow_rule(dev, ft_prio, 2963 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2964 dst); 2965 if (IS_ERR(handler_ucast)) { 2966 mlx5_del_flow_rules(handler->rule); 2967 ft_prio->refcount--; 2968 kfree(handler); 2969 handler = handler_ucast; 2970 } else { 2971 list_add(&handler_ucast->list, &handler->list); 2972 } 2973 } 2974 2975 return handler; 2976 } 2977 2978 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2979 struct mlx5_ib_flow_prio *ft_rx, 2980 struct mlx5_ib_flow_prio *ft_tx, 2981 struct mlx5_flow_destination *dst) 2982 { 2983 struct mlx5_ib_flow_handler *handler_rx; 2984 struct mlx5_ib_flow_handler *handler_tx; 2985 int err; 2986 static const struct ib_flow_attr flow_attr = { 2987 .num_of_specs = 0, 2988 .size = sizeof(flow_attr) 2989 }; 2990 2991 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2992 if (IS_ERR(handler_rx)) { 2993 err = PTR_ERR(handler_rx); 2994 goto err; 2995 } 2996 2997 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2998 if (IS_ERR(handler_tx)) { 2999 err = PTR_ERR(handler_tx); 3000 goto err_tx; 3001 } 3002 3003 list_add(&handler_tx->list, &handler_rx->list); 3004 3005 return handler_rx; 3006 3007 err_tx: 3008 mlx5_del_flow_rules(handler_rx->rule); 3009 ft_rx->refcount--; 3010 kfree(handler_rx); 3011 err: 3012 return ERR_PTR(err); 3013 } 3014 3015 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3016 struct ib_flow_attr *flow_attr, 3017 int domain) 3018 { 3019 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3020 struct mlx5_ib_qp *mqp = to_mqp(qp); 3021 struct mlx5_ib_flow_handler *handler = NULL; 3022 struct mlx5_flow_destination *dst = NULL; 3023 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3024 struct mlx5_ib_flow_prio *ft_prio; 3025 int err; 3026 int underlay_qpn; 3027 3028 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 3029 return ERR_PTR(-ENOMEM); 3030 3031 if (domain != IB_FLOW_DOMAIN_USER || 3032 flow_attr->port > dev->num_ports || 3033 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 3034 return ERR_PTR(-EINVAL); 3035 3036 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3037 if (!dst) 3038 return ERR_PTR(-ENOMEM); 3039 3040 mutex_lock(&dev->flow_db->lock); 3041 3042 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 3043 if (IS_ERR(ft_prio)) { 3044 err = PTR_ERR(ft_prio); 3045 goto unlock; 3046 } 3047 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3048 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3049 if (IS_ERR(ft_prio_tx)) { 3050 err = PTR_ERR(ft_prio_tx); 3051 ft_prio_tx = NULL; 3052 goto destroy_ft; 3053 } 3054 } 3055 3056 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3057 if (mqp->flags & MLX5_IB_QP_RSS) 3058 dst->tir_num = mqp->rss_qp.tirn; 3059 else 3060 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3061 3062 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3063 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3064 handler = create_dont_trap_rule(dev, ft_prio, 3065 flow_attr, dst); 3066 } else { 3067 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3068 mqp->underlay_qpn : 0; 3069 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3070 dst, underlay_qpn); 3071 } 3072 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3073 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3074 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3075 dst); 3076 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3077 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3078 } else { 3079 err = -EINVAL; 3080 goto destroy_ft; 3081 } 3082 3083 if (IS_ERR(handler)) { 3084 err = PTR_ERR(handler); 3085 handler = NULL; 3086 goto destroy_ft; 3087 } 3088 3089 mutex_unlock(&dev->flow_db->lock); 3090 kfree(dst); 3091 3092 return &handler->ibflow; 3093 3094 destroy_ft: 3095 put_flow_table(dev, ft_prio, false); 3096 if (ft_prio_tx) 3097 put_flow_table(dev, ft_prio_tx, false); 3098 unlock: 3099 mutex_unlock(&dev->flow_db->lock); 3100 kfree(dst); 3101 kfree(handler); 3102 return ERR_PTR(err); 3103 } 3104 3105 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3106 { 3107 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3108 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 3109 int err; 3110 3111 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 3112 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 3113 return -EOPNOTSUPP; 3114 } 3115 3116 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 3117 if (err) 3118 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 3119 ibqp->qp_num, gid->raw); 3120 3121 return err; 3122 } 3123 3124 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3125 { 3126 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3127 int err; 3128 3129 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 3130 if (err) 3131 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 3132 ibqp->qp_num, gid->raw); 3133 3134 return err; 3135 } 3136 3137 static int init_node_data(struct mlx5_ib_dev *dev) 3138 { 3139 int err; 3140 3141 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 3142 if (err) 3143 return err; 3144 3145 dev->mdev->rev_id = dev->mdev->pdev->revision; 3146 3147 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 3148 } 3149 3150 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 3151 char *buf) 3152 { 3153 struct mlx5_ib_dev *dev = 3154 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3155 3156 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 3157 } 3158 3159 static ssize_t show_reg_pages(struct device *device, 3160 struct device_attribute *attr, char *buf) 3161 { 3162 struct mlx5_ib_dev *dev = 3163 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3164 3165 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 3166 } 3167 3168 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 3169 char *buf) 3170 { 3171 struct mlx5_ib_dev *dev = 3172 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3173 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 3174 } 3175 3176 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 3177 char *buf) 3178 { 3179 struct mlx5_ib_dev *dev = 3180 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3181 return sprintf(buf, "%x\n", dev->mdev->rev_id); 3182 } 3183 3184 static ssize_t show_board(struct device *device, struct device_attribute *attr, 3185 char *buf) 3186 { 3187 struct mlx5_ib_dev *dev = 3188 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3189 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 3190 dev->mdev->board_id); 3191 } 3192 3193 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 3194 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 3195 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 3196 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 3197 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 3198 3199 static struct device_attribute *mlx5_class_attributes[] = { 3200 &dev_attr_hw_rev, 3201 &dev_attr_hca_type, 3202 &dev_attr_board_id, 3203 &dev_attr_fw_pages, 3204 &dev_attr_reg_pages, 3205 }; 3206 3207 static void pkey_change_handler(struct work_struct *work) 3208 { 3209 struct mlx5_ib_port_resources *ports = 3210 container_of(work, struct mlx5_ib_port_resources, 3211 pkey_change_work); 3212 3213 mutex_lock(&ports->devr->mutex); 3214 mlx5_ib_gsi_pkey_change(ports->gsi); 3215 mutex_unlock(&ports->devr->mutex); 3216 } 3217 3218 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 3219 { 3220 struct mlx5_ib_qp *mqp; 3221 struct mlx5_ib_cq *send_mcq, *recv_mcq; 3222 struct mlx5_core_cq *mcq; 3223 struct list_head cq_armed_list; 3224 unsigned long flags_qp; 3225 unsigned long flags_cq; 3226 unsigned long flags; 3227 3228 INIT_LIST_HEAD(&cq_armed_list); 3229 3230 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3231 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3232 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3233 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3234 if (mqp->sq.tail != mqp->sq.head) { 3235 send_mcq = to_mcq(mqp->ibqp.send_cq); 3236 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3237 if (send_mcq->mcq.comp && 3238 mqp->ibqp.send_cq->comp_handler) { 3239 if (!send_mcq->mcq.reset_notify_added) { 3240 send_mcq->mcq.reset_notify_added = 1; 3241 list_add_tail(&send_mcq->mcq.reset_notify, 3242 &cq_armed_list); 3243 } 3244 } 3245 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3246 } 3247 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3248 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3249 /* no handling is needed for SRQ */ 3250 if (!mqp->ibqp.srq) { 3251 if (mqp->rq.tail != mqp->rq.head) { 3252 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3253 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3254 if (recv_mcq->mcq.comp && 3255 mqp->ibqp.recv_cq->comp_handler) { 3256 if (!recv_mcq->mcq.reset_notify_added) { 3257 recv_mcq->mcq.reset_notify_added = 1; 3258 list_add_tail(&recv_mcq->mcq.reset_notify, 3259 &cq_armed_list); 3260 } 3261 } 3262 spin_unlock_irqrestore(&recv_mcq->lock, 3263 flags_cq); 3264 } 3265 } 3266 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3267 } 3268 /*At that point all inflight post send were put to be executed as of we 3269 * lock/unlock above locks Now need to arm all involved CQs. 3270 */ 3271 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3272 mcq->comp(mcq); 3273 } 3274 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3275 } 3276 3277 static void delay_drop_handler(struct work_struct *work) 3278 { 3279 int err; 3280 struct mlx5_ib_delay_drop *delay_drop = 3281 container_of(work, struct mlx5_ib_delay_drop, 3282 delay_drop_work); 3283 3284 atomic_inc(&delay_drop->events_cnt); 3285 3286 mutex_lock(&delay_drop->lock); 3287 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 3288 delay_drop->timeout); 3289 if (err) { 3290 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3291 delay_drop->timeout); 3292 delay_drop->activate = false; 3293 } 3294 mutex_unlock(&delay_drop->lock); 3295 } 3296 3297 static void mlx5_ib_handle_event(struct work_struct *_work) 3298 { 3299 struct mlx5_ib_event_work *work = 3300 container_of(_work, struct mlx5_ib_event_work, work); 3301 struct mlx5_ib_dev *ibdev; 3302 struct ib_event ibev; 3303 bool fatal = false; 3304 u8 port = (u8)work->param; 3305 3306 if (mlx5_core_is_mp_slave(work->dev)) { 3307 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 3308 if (!ibdev) 3309 goto out; 3310 } else { 3311 ibdev = work->context; 3312 } 3313 3314 switch (work->event) { 3315 case MLX5_DEV_EVENT_SYS_ERROR: 3316 ibev.event = IB_EVENT_DEVICE_FATAL; 3317 mlx5_ib_handle_internal_error(ibdev); 3318 fatal = true; 3319 break; 3320 3321 case MLX5_DEV_EVENT_PORT_UP: 3322 case MLX5_DEV_EVENT_PORT_DOWN: 3323 case MLX5_DEV_EVENT_PORT_INITIALIZED: 3324 /* In RoCE, port up/down events are handled in 3325 * mlx5_netdev_event(). 3326 */ 3327 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3328 IB_LINK_LAYER_ETHERNET) 3329 goto out; 3330 3331 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 3332 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3333 break; 3334 3335 case MLX5_DEV_EVENT_LID_CHANGE: 3336 ibev.event = IB_EVENT_LID_CHANGE; 3337 break; 3338 3339 case MLX5_DEV_EVENT_PKEY_CHANGE: 3340 ibev.event = IB_EVENT_PKEY_CHANGE; 3341 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3342 break; 3343 3344 case MLX5_DEV_EVENT_GUID_CHANGE: 3345 ibev.event = IB_EVENT_GID_CHANGE; 3346 break; 3347 3348 case MLX5_DEV_EVENT_CLIENT_REREG: 3349 ibev.event = IB_EVENT_CLIENT_REREGISTER; 3350 break; 3351 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 3352 schedule_work(&ibdev->delay_drop.delay_drop_work); 3353 goto out; 3354 default: 3355 goto out; 3356 } 3357 3358 ibev.device = &ibdev->ib_dev; 3359 ibev.element.port_num = port; 3360 3361 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 3362 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 3363 goto out; 3364 } 3365 3366 if (ibdev->ib_active) 3367 ib_dispatch_event(&ibev); 3368 3369 if (fatal) 3370 ibdev->ib_active = false; 3371 out: 3372 kfree(work); 3373 } 3374 3375 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 3376 enum mlx5_dev_event event, unsigned long param) 3377 { 3378 struct mlx5_ib_event_work *work; 3379 3380 work = kmalloc(sizeof(*work), GFP_ATOMIC); 3381 if (!work) 3382 return; 3383 3384 INIT_WORK(&work->work, mlx5_ib_handle_event); 3385 work->dev = dev; 3386 work->param = param; 3387 work->context = context; 3388 work->event = event; 3389 3390 queue_work(mlx5_ib_event_wq, &work->work); 3391 } 3392 3393 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3394 { 3395 struct mlx5_hca_vport_context vport_ctx; 3396 int err; 3397 int port; 3398 3399 for (port = 1; port <= dev->num_ports; port++) { 3400 dev->mdev->port_caps[port - 1].has_smi = false; 3401 if (MLX5_CAP_GEN(dev->mdev, port_type) == 3402 MLX5_CAP_PORT_TYPE_IB) { 3403 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 3404 err = mlx5_query_hca_vport_context(dev->mdev, 0, 3405 port, 0, 3406 &vport_ctx); 3407 if (err) { 3408 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3409 port, err); 3410 return err; 3411 } 3412 dev->mdev->port_caps[port - 1].has_smi = 3413 vport_ctx.has_smi; 3414 } else { 3415 dev->mdev->port_caps[port - 1].has_smi = true; 3416 } 3417 } 3418 } 3419 return 0; 3420 } 3421 3422 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3423 { 3424 int port; 3425 3426 for (port = 1; port <= dev->num_ports; port++) 3427 mlx5_query_ext_port_caps(dev, port); 3428 } 3429 3430 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3431 { 3432 struct ib_device_attr *dprops = NULL; 3433 struct ib_port_attr *pprops = NULL; 3434 int err = -ENOMEM; 3435 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 3436 3437 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 3438 if (!pprops) 3439 goto out; 3440 3441 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 3442 if (!dprops) 3443 goto out; 3444 3445 err = set_has_smi_cap(dev); 3446 if (err) 3447 goto out; 3448 3449 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 3450 if (err) { 3451 mlx5_ib_warn(dev, "query_device failed %d\n", err); 3452 goto out; 3453 } 3454 3455 memset(pprops, 0, sizeof(*pprops)); 3456 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3457 if (err) { 3458 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3459 port, err); 3460 goto out; 3461 } 3462 3463 dev->mdev->port_caps[port - 1].pkey_table_len = 3464 dprops->max_pkeys; 3465 dev->mdev->port_caps[port - 1].gid_table_len = 3466 pprops->gid_tbl_len; 3467 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 3468 port, dprops->max_pkeys, pprops->gid_tbl_len); 3469 3470 out: 3471 kfree(pprops); 3472 kfree(dprops); 3473 3474 return err; 3475 } 3476 3477 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3478 { 3479 int err; 3480 3481 err = mlx5_mr_cache_cleanup(dev); 3482 if (err) 3483 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3484 3485 if (dev->umrc.qp) 3486 mlx5_ib_destroy_qp(dev->umrc.qp); 3487 if (dev->umrc.cq) 3488 ib_free_cq(dev->umrc.cq); 3489 if (dev->umrc.pd) 3490 ib_dealloc_pd(dev->umrc.pd); 3491 } 3492 3493 enum { 3494 MAX_UMR_WR = 128, 3495 }; 3496 3497 static int create_umr_res(struct mlx5_ib_dev *dev) 3498 { 3499 struct ib_qp_init_attr *init_attr = NULL; 3500 struct ib_qp_attr *attr = NULL; 3501 struct ib_pd *pd; 3502 struct ib_cq *cq; 3503 struct ib_qp *qp; 3504 int ret; 3505 3506 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3507 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3508 if (!attr || !init_attr) { 3509 ret = -ENOMEM; 3510 goto error_0; 3511 } 3512 3513 pd = ib_alloc_pd(&dev->ib_dev, 0); 3514 if (IS_ERR(pd)) { 3515 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3516 ret = PTR_ERR(pd); 3517 goto error_0; 3518 } 3519 3520 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3521 if (IS_ERR(cq)) { 3522 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3523 ret = PTR_ERR(cq); 3524 goto error_2; 3525 } 3526 3527 init_attr->send_cq = cq; 3528 init_attr->recv_cq = cq; 3529 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3530 init_attr->cap.max_send_wr = MAX_UMR_WR; 3531 init_attr->cap.max_send_sge = 1; 3532 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3533 init_attr->port_num = 1; 3534 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3535 if (IS_ERR(qp)) { 3536 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3537 ret = PTR_ERR(qp); 3538 goto error_3; 3539 } 3540 qp->device = &dev->ib_dev; 3541 qp->real_qp = qp; 3542 qp->uobject = NULL; 3543 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3544 qp->send_cq = init_attr->send_cq; 3545 qp->recv_cq = init_attr->recv_cq; 3546 3547 attr->qp_state = IB_QPS_INIT; 3548 attr->port_num = 1; 3549 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3550 IB_QP_PORT, NULL); 3551 if (ret) { 3552 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3553 goto error_4; 3554 } 3555 3556 memset(attr, 0, sizeof(*attr)); 3557 attr->qp_state = IB_QPS_RTR; 3558 attr->path_mtu = IB_MTU_256; 3559 3560 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3561 if (ret) { 3562 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3563 goto error_4; 3564 } 3565 3566 memset(attr, 0, sizeof(*attr)); 3567 attr->qp_state = IB_QPS_RTS; 3568 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3569 if (ret) { 3570 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3571 goto error_4; 3572 } 3573 3574 dev->umrc.qp = qp; 3575 dev->umrc.cq = cq; 3576 dev->umrc.pd = pd; 3577 3578 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3579 ret = mlx5_mr_cache_init(dev); 3580 if (ret) { 3581 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3582 goto error_4; 3583 } 3584 3585 kfree(attr); 3586 kfree(init_attr); 3587 3588 return 0; 3589 3590 error_4: 3591 mlx5_ib_destroy_qp(qp); 3592 dev->umrc.qp = NULL; 3593 3594 error_3: 3595 ib_free_cq(cq); 3596 dev->umrc.cq = NULL; 3597 3598 error_2: 3599 ib_dealloc_pd(pd); 3600 dev->umrc.pd = NULL; 3601 3602 error_0: 3603 kfree(attr); 3604 kfree(init_attr); 3605 return ret; 3606 } 3607 3608 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3609 { 3610 switch (umr_fence_cap) { 3611 case MLX5_CAP_UMR_FENCE_NONE: 3612 return MLX5_FENCE_MODE_NONE; 3613 case MLX5_CAP_UMR_FENCE_SMALL: 3614 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3615 default: 3616 return MLX5_FENCE_MODE_STRONG_ORDERING; 3617 } 3618 } 3619 3620 static int create_dev_resources(struct mlx5_ib_resources *devr) 3621 { 3622 struct ib_srq_init_attr attr; 3623 struct mlx5_ib_dev *dev; 3624 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3625 int port; 3626 int ret = 0; 3627 3628 dev = container_of(devr, struct mlx5_ib_dev, devr); 3629 3630 mutex_init(&devr->mutex); 3631 3632 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3633 if (IS_ERR(devr->p0)) { 3634 ret = PTR_ERR(devr->p0); 3635 goto error0; 3636 } 3637 devr->p0->device = &dev->ib_dev; 3638 devr->p0->uobject = NULL; 3639 atomic_set(&devr->p0->usecnt, 0); 3640 3641 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3642 if (IS_ERR(devr->c0)) { 3643 ret = PTR_ERR(devr->c0); 3644 goto error1; 3645 } 3646 devr->c0->device = &dev->ib_dev; 3647 devr->c0->uobject = NULL; 3648 devr->c0->comp_handler = NULL; 3649 devr->c0->event_handler = NULL; 3650 devr->c0->cq_context = NULL; 3651 atomic_set(&devr->c0->usecnt, 0); 3652 3653 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3654 if (IS_ERR(devr->x0)) { 3655 ret = PTR_ERR(devr->x0); 3656 goto error2; 3657 } 3658 devr->x0->device = &dev->ib_dev; 3659 devr->x0->inode = NULL; 3660 atomic_set(&devr->x0->usecnt, 0); 3661 mutex_init(&devr->x0->tgt_qp_mutex); 3662 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3663 3664 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3665 if (IS_ERR(devr->x1)) { 3666 ret = PTR_ERR(devr->x1); 3667 goto error3; 3668 } 3669 devr->x1->device = &dev->ib_dev; 3670 devr->x1->inode = NULL; 3671 atomic_set(&devr->x1->usecnt, 0); 3672 mutex_init(&devr->x1->tgt_qp_mutex); 3673 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3674 3675 memset(&attr, 0, sizeof(attr)); 3676 attr.attr.max_sge = 1; 3677 attr.attr.max_wr = 1; 3678 attr.srq_type = IB_SRQT_XRC; 3679 attr.ext.cq = devr->c0; 3680 attr.ext.xrc.xrcd = devr->x0; 3681 3682 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3683 if (IS_ERR(devr->s0)) { 3684 ret = PTR_ERR(devr->s0); 3685 goto error4; 3686 } 3687 devr->s0->device = &dev->ib_dev; 3688 devr->s0->pd = devr->p0; 3689 devr->s0->uobject = NULL; 3690 devr->s0->event_handler = NULL; 3691 devr->s0->srq_context = NULL; 3692 devr->s0->srq_type = IB_SRQT_XRC; 3693 devr->s0->ext.xrc.xrcd = devr->x0; 3694 devr->s0->ext.cq = devr->c0; 3695 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3696 atomic_inc(&devr->s0->ext.cq->usecnt); 3697 atomic_inc(&devr->p0->usecnt); 3698 atomic_set(&devr->s0->usecnt, 0); 3699 3700 memset(&attr, 0, sizeof(attr)); 3701 attr.attr.max_sge = 1; 3702 attr.attr.max_wr = 1; 3703 attr.srq_type = IB_SRQT_BASIC; 3704 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3705 if (IS_ERR(devr->s1)) { 3706 ret = PTR_ERR(devr->s1); 3707 goto error5; 3708 } 3709 devr->s1->device = &dev->ib_dev; 3710 devr->s1->pd = devr->p0; 3711 devr->s1->uobject = NULL; 3712 devr->s1->event_handler = NULL; 3713 devr->s1->srq_context = NULL; 3714 devr->s1->srq_type = IB_SRQT_BASIC; 3715 devr->s1->ext.cq = devr->c0; 3716 atomic_inc(&devr->p0->usecnt); 3717 atomic_set(&devr->s1->usecnt, 0); 3718 3719 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3720 INIT_WORK(&devr->ports[port].pkey_change_work, 3721 pkey_change_handler); 3722 devr->ports[port].devr = devr; 3723 } 3724 3725 return 0; 3726 3727 error5: 3728 mlx5_ib_destroy_srq(devr->s0); 3729 error4: 3730 mlx5_ib_dealloc_xrcd(devr->x1); 3731 error3: 3732 mlx5_ib_dealloc_xrcd(devr->x0); 3733 error2: 3734 mlx5_ib_destroy_cq(devr->c0); 3735 error1: 3736 mlx5_ib_dealloc_pd(devr->p0); 3737 error0: 3738 return ret; 3739 } 3740 3741 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3742 { 3743 struct mlx5_ib_dev *dev = 3744 container_of(devr, struct mlx5_ib_dev, devr); 3745 int port; 3746 3747 mlx5_ib_destroy_srq(devr->s1); 3748 mlx5_ib_destroy_srq(devr->s0); 3749 mlx5_ib_dealloc_xrcd(devr->x0); 3750 mlx5_ib_dealloc_xrcd(devr->x1); 3751 mlx5_ib_destroy_cq(devr->c0); 3752 mlx5_ib_dealloc_pd(devr->p0); 3753 3754 /* Make sure no change P_Key work items are still executing */ 3755 for (port = 0; port < dev->num_ports; ++port) 3756 cancel_work_sync(&devr->ports[port].pkey_change_work); 3757 } 3758 3759 static u32 get_core_cap_flags(struct ib_device *ibdev) 3760 { 3761 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3762 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3763 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3764 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3765 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3766 u32 ret = 0; 3767 3768 if (ll == IB_LINK_LAYER_INFINIBAND) 3769 return RDMA_CORE_PORT_IBA_IB; 3770 3771 if (raw_support) 3772 ret = RDMA_CORE_PORT_RAW_PACKET; 3773 3774 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3775 return ret; 3776 3777 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3778 return ret; 3779 3780 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3781 ret |= RDMA_CORE_PORT_IBA_ROCE; 3782 3783 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3784 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3785 3786 return ret; 3787 } 3788 3789 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3790 struct ib_port_immutable *immutable) 3791 { 3792 struct ib_port_attr attr; 3793 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3794 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3795 int err; 3796 3797 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3798 3799 err = ib_query_port(ibdev, port_num, &attr); 3800 if (err) 3801 return err; 3802 3803 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3804 immutable->gid_tbl_len = attr.gid_tbl_len; 3805 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3806 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3807 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3808 3809 return 0; 3810 } 3811 3812 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3813 struct ib_port_immutable *immutable) 3814 { 3815 struct ib_port_attr attr; 3816 int err; 3817 3818 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3819 3820 err = ib_query_port(ibdev, port_num, &attr); 3821 if (err) 3822 return err; 3823 3824 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3825 immutable->gid_tbl_len = attr.gid_tbl_len; 3826 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3827 3828 return 0; 3829 } 3830 3831 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3832 { 3833 struct mlx5_ib_dev *dev = 3834 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3835 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3836 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3837 fw_rev_sub(dev->mdev)); 3838 } 3839 3840 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3841 { 3842 struct mlx5_core_dev *mdev = dev->mdev; 3843 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3844 MLX5_FLOW_NAMESPACE_LAG); 3845 struct mlx5_flow_table *ft; 3846 int err; 3847 3848 if (!ns || !mlx5_lag_is_active(mdev)) 3849 return 0; 3850 3851 err = mlx5_cmd_create_vport_lag(mdev); 3852 if (err) 3853 return err; 3854 3855 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3856 if (IS_ERR(ft)) { 3857 err = PTR_ERR(ft); 3858 goto err_destroy_vport_lag; 3859 } 3860 3861 dev->flow_db->lag_demux_ft = ft; 3862 return 0; 3863 3864 err_destroy_vport_lag: 3865 mlx5_cmd_destroy_vport_lag(mdev); 3866 return err; 3867 } 3868 3869 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3870 { 3871 struct mlx5_core_dev *mdev = dev->mdev; 3872 3873 if (dev->flow_db->lag_demux_ft) { 3874 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3875 dev->flow_db->lag_demux_ft = NULL; 3876 3877 mlx5_cmd_destroy_vport_lag(mdev); 3878 } 3879 } 3880 3881 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3882 { 3883 int err; 3884 3885 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 3886 err = register_netdevice_notifier(&dev->roce[port_num].nb); 3887 if (err) { 3888 dev->roce[port_num].nb.notifier_call = NULL; 3889 return err; 3890 } 3891 3892 return 0; 3893 } 3894 3895 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3896 { 3897 if (dev->roce[port_num].nb.notifier_call) { 3898 unregister_netdevice_notifier(&dev->roce[port_num].nb); 3899 dev->roce[port_num].nb.notifier_call = NULL; 3900 } 3901 } 3902 3903 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num) 3904 { 3905 int err; 3906 3907 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3908 err = mlx5_nic_vport_enable_roce(dev->mdev); 3909 if (err) 3910 return err; 3911 } 3912 3913 err = mlx5_eth_lag_init(dev); 3914 if (err) 3915 goto err_disable_roce; 3916 3917 return 0; 3918 3919 err_disable_roce: 3920 if (MLX5_CAP_GEN(dev->mdev, roce)) 3921 mlx5_nic_vport_disable_roce(dev->mdev); 3922 3923 return err; 3924 } 3925 3926 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3927 { 3928 mlx5_eth_lag_cleanup(dev); 3929 if (MLX5_CAP_GEN(dev->mdev, roce)) 3930 mlx5_nic_vport_disable_roce(dev->mdev); 3931 } 3932 3933 struct mlx5_ib_counter { 3934 const char *name; 3935 size_t offset; 3936 }; 3937 3938 #define INIT_Q_COUNTER(_name) \ 3939 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3940 3941 static const struct mlx5_ib_counter basic_q_cnts[] = { 3942 INIT_Q_COUNTER(rx_write_requests), 3943 INIT_Q_COUNTER(rx_read_requests), 3944 INIT_Q_COUNTER(rx_atomic_requests), 3945 INIT_Q_COUNTER(out_of_buffer), 3946 }; 3947 3948 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3949 INIT_Q_COUNTER(out_of_sequence), 3950 }; 3951 3952 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3953 INIT_Q_COUNTER(duplicate_request), 3954 INIT_Q_COUNTER(rnr_nak_retry_err), 3955 INIT_Q_COUNTER(packet_seq_err), 3956 INIT_Q_COUNTER(implied_nak_seq_err), 3957 INIT_Q_COUNTER(local_ack_timeout_err), 3958 }; 3959 3960 #define INIT_CONG_COUNTER(_name) \ 3961 { .name = #_name, .offset = \ 3962 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3963 3964 static const struct mlx5_ib_counter cong_cnts[] = { 3965 INIT_CONG_COUNTER(rp_cnp_ignored), 3966 INIT_CONG_COUNTER(rp_cnp_handled), 3967 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3968 INIT_CONG_COUNTER(np_cnp_sent), 3969 }; 3970 3971 static const struct mlx5_ib_counter extended_err_cnts[] = { 3972 INIT_Q_COUNTER(resp_local_length_error), 3973 INIT_Q_COUNTER(resp_cqe_error), 3974 INIT_Q_COUNTER(req_cqe_error), 3975 INIT_Q_COUNTER(req_remote_invalid_request), 3976 INIT_Q_COUNTER(req_remote_access_errors), 3977 INIT_Q_COUNTER(resp_remote_access_errors), 3978 INIT_Q_COUNTER(resp_cqe_flush_error), 3979 INIT_Q_COUNTER(req_cqe_flush_error), 3980 }; 3981 3982 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3983 { 3984 int i; 3985 3986 for (i = 0; i < dev->num_ports; i++) { 3987 if (dev->port[i].cnts.set_id) 3988 mlx5_core_dealloc_q_counter(dev->mdev, 3989 dev->port[i].cnts.set_id); 3990 kfree(dev->port[i].cnts.names); 3991 kfree(dev->port[i].cnts.offsets); 3992 } 3993 } 3994 3995 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3996 struct mlx5_ib_counters *cnts) 3997 { 3998 u32 num_counters; 3999 4000 num_counters = ARRAY_SIZE(basic_q_cnts); 4001 4002 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 4003 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 4004 4005 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 4006 num_counters += ARRAY_SIZE(retrans_q_cnts); 4007 4008 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 4009 num_counters += ARRAY_SIZE(extended_err_cnts); 4010 4011 cnts->num_q_counters = num_counters; 4012 4013 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4014 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 4015 num_counters += ARRAY_SIZE(cong_cnts); 4016 } 4017 4018 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 4019 if (!cnts->names) 4020 return -ENOMEM; 4021 4022 cnts->offsets = kcalloc(num_counters, 4023 sizeof(cnts->offsets), GFP_KERNEL); 4024 if (!cnts->offsets) 4025 goto err_names; 4026 4027 return 0; 4028 4029 err_names: 4030 kfree(cnts->names); 4031 cnts->names = NULL; 4032 return -ENOMEM; 4033 } 4034 4035 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 4036 const char **names, 4037 size_t *offsets) 4038 { 4039 int i; 4040 int j = 0; 4041 4042 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 4043 names[j] = basic_q_cnts[i].name; 4044 offsets[j] = basic_q_cnts[i].offset; 4045 } 4046 4047 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 4048 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 4049 names[j] = out_of_seq_q_cnts[i].name; 4050 offsets[j] = out_of_seq_q_cnts[i].offset; 4051 } 4052 } 4053 4054 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 4055 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 4056 names[j] = retrans_q_cnts[i].name; 4057 offsets[j] = retrans_q_cnts[i].offset; 4058 } 4059 } 4060 4061 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 4062 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 4063 names[j] = extended_err_cnts[i].name; 4064 offsets[j] = extended_err_cnts[i].offset; 4065 } 4066 } 4067 4068 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4069 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 4070 names[j] = cong_cnts[i].name; 4071 offsets[j] = cong_cnts[i].offset; 4072 } 4073 } 4074 } 4075 4076 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 4077 { 4078 int err = 0; 4079 int i; 4080 4081 for (i = 0; i < dev->num_ports; i++) { 4082 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 4083 if (err) 4084 goto err_alloc; 4085 4086 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 4087 dev->port[i].cnts.offsets); 4088 4089 err = mlx5_core_alloc_q_counter(dev->mdev, 4090 &dev->port[i].cnts.set_id); 4091 if (err) { 4092 mlx5_ib_warn(dev, 4093 "couldn't allocate queue counter for port %d, err %d\n", 4094 i + 1, err); 4095 goto err_alloc; 4096 } 4097 dev->port[i].cnts.set_id_valid = true; 4098 } 4099 4100 return 0; 4101 4102 err_alloc: 4103 mlx5_ib_dealloc_counters(dev); 4104 return err; 4105 } 4106 4107 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 4108 u8 port_num) 4109 { 4110 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4111 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4112 4113 /* We support only per port stats */ 4114 if (port_num == 0) 4115 return NULL; 4116 4117 return rdma_alloc_hw_stats_struct(port->cnts.names, 4118 port->cnts.num_q_counters + 4119 port->cnts.num_cong_counters, 4120 RDMA_HW_STATS_DEFAULT_LIFESPAN); 4121 } 4122 4123 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 4124 struct mlx5_ib_port *port, 4125 struct rdma_hw_stats *stats) 4126 { 4127 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 4128 void *out; 4129 __be32 val; 4130 int ret, i; 4131 4132 out = kvzalloc(outlen, GFP_KERNEL); 4133 if (!out) 4134 return -ENOMEM; 4135 4136 ret = mlx5_core_query_q_counter(mdev, 4137 port->cnts.set_id, 0, 4138 out, outlen); 4139 if (ret) 4140 goto free; 4141 4142 for (i = 0; i < port->cnts.num_q_counters; i++) { 4143 val = *(__be32 *)(out + port->cnts.offsets[i]); 4144 stats->value[i] = (u64)be32_to_cpu(val); 4145 } 4146 4147 free: 4148 kvfree(out); 4149 return ret; 4150 } 4151 4152 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 4153 struct rdma_hw_stats *stats, 4154 u8 port_num, int index) 4155 { 4156 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4157 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4158 struct mlx5_core_dev *mdev; 4159 int ret, num_counters; 4160 u8 mdev_port_num; 4161 4162 if (!stats) 4163 return -EINVAL; 4164 4165 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters; 4166 4167 /* q_counters are per IB device, query the master mdev */ 4168 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 4169 if (ret) 4170 return ret; 4171 4172 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4173 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 4174 &mdev_port_num); 4175 if (!mdev) { 4176 /* If port is not affiliated yet, its in down state 4177 * which doesn't have any counters yet, so it would be 4178 * zero. So no need to read from the HCA. 4179 */ 4180 goto done; 4181 } 4182 ret = mlx5_lag_query_cong_counters(dev->mdev, 4183 stats->value + 4184 port->cnts.num_q_counters, 4185 port->cnts.num_cong_counters, 4186 port->cnts.offsets + 4187 port->cnts.num_q_counters); 4188 4189 mlx5_ib_put_native_port_mdev(dev, port_num); 4190 if (ret) 4191 return ret; 4192 } 4193 4194 done: 4195 return num_counters; 4196 } 4197 4198 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 4199 { 4200 return mlx5_rdma_netdev_free(netdev); 4201 } 4202 4203 static struct net_device* 4204 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 4205 u8 port_num, 4206 enum rdma_netdev_t type, 4207 const char *name, 4208 unsigned char name_assign_type, 4209 void (*setup)(struct net_device *)) 4210 { 4211 struct net_device *netdev; 4212 struct rdma_netdev *rn; 4213 4214 if (type != RDMA_NETDEV_IPOIB) 4215 return ERR_PTR(-EOPNOTSUPP); 4216 4217 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 4218 name, setup); 4219 if (likely(!IS_ERR_OR_NULL(netdev))) { 4220 rn = netdev_priv(netdev); 4221 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 4222 } 4223 return netdev; 4224 } 4225 4226 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 4227 { 4228 if (!dev->delay_drop.dbg) 4229 return; 4230 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 4231 kfree(dev->delay_drop.dbg); 4232 dev->delay_drop.dbg = NULL; 4233 } 4234 4235 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 4236 { 4237 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4238 return; 4239 4240 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4241 delay_drop_debugfs_cleanup(dev); 4242 } 4243 4244 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 4245 size_t count, loff_t *pos) 4246 { 4247 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4248 char lbuf[20]; 4249 int len; 4250 4251 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 4252 return simple_read_from_buffer(buf, count, pos, lbuf, len); 4253 } 4254 4255 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 4256 size_t count, loff_t *pos) 4257 { 4258 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4259 u32 timeout; 4260 u32 var; 4261 4262 if (kstrtouint_from_user(buf, count, 0, &var)) 4263 return -EFAULT; 4264 4265 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 4266 1000); 4267 if (timeout != var) 4268 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 4269 timeout); 4270 4271 delay_drop->timeout = timeout; 4272 4273 return count; 4274 } 4275 4276 static const struct file_operations fops_delay_drop_timeout = { 4277 .owner = THIS_MODULE, 4278 .open = simple_open, 4279 .write = delay_drop_timeout_write, 4280 .read = delay_drop_timeout_read, 4281 }; 4282 4283 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 4284 { 4285 struct mlx5_ib_dbg_delay_drop *dbg; 4286 4287 if (!mlx5_debugfs_root) 4288 return 0; 4289 4290 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 4291 if (!dbg) 4292 return -ENOMEM; 4293 4294 dev->delay_drop.dbg = dbg; 4295 4296 dbg->dir_debugfs = 4297 debugfs_create_dir("delay_drop", 4298 dev->mdev->priv.dbg_root); 4299 if (!dbg->dir_debugfs) 4300 goto out_debugfs; 4301 4302 dbg->events_cnt_debugfs = 4303 debugfs_create_atomic_t("num_timeout_events", 0400, 4304 dbg->dir_debugfs, 4305 &dev->delay_drop.events_cnt); 4306 if (!dbg->events_cnt_debugfs) 4307 goto out_debugfs; 4308 4309 dbg->rqs_cnt_debugfs = 4310 debugfs_create_atomic_t("num_rqs", 0400, 4311 dbg->dir_debugfs, 4312 &dev->delay_drop.rqs_cnt); 4313 if (!dbg->rqs_cnt_debugfs) 4314 goto out_debugfs; 4315 4316 dbg->timeout_debugfs = 4317 debugfs_create_file("timeout", 0600, 4318 dbg->dir_debugfs, 4319 &dev->delay_drop, 4320 &fops_delay_drop_timeout); 4321 if (!dbg->timeout_debugfs) 4322 goto out_debugfs; 4323 4324 return 0; 4325 4326 out_debugfs: 4327 delay_drop_debugfs_cleanup(dev); 4328 return -ENOMEM; 4329 } 4330 4331 static void init_delay_drop(struct mlx5_ib_dev *dev) 4332 { 4333 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4334 return; 4335 4336 mutex_init(&dev->delay_drop.lock); 4337 dev->delay_drop.dev = dev; 4338 dev->delay_drop.activate = false; 4339 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4340 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4341 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4342 atomic_set(&dev->delay_drop.events_cnt, 0); 4343 4344 if (delay_drop_debugfs_init(dev)) 4345 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 4346 } 4347 4348 static const struct cpumask * 4349 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 4350 { 4351 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4352 4353 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 4354 } 4355 4356 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4357 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 4358 struct mlx5_ib_multiport_info *mpi) 4359 { 4360 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4361 struct mlx5_ib_port *port = &ibdev->port[port_num]; 4362 int comps; 4363 int err; 4364 int i; 4365 4366 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 4367 4368 spin_lock(&port->mp.mpi_lock); 4369 if (!mpi->ibdev) { 4370 spin_unlock(&port->mp.mpi_lock); 4371 return; 4372 } 4373 mpi->ibdev = NULL; 4374 4375 spin_unlock(&port->mp.mpi_lock); 4376 mlx5_remove_netdev_notifier(ibdev, port_num); 4377 spin_lock(&port->mp.mpi_lock); 4378 4379 comps = mpi->mdev_refcnt; 4380 if (comps) { 4381 mpi->unaffiliate = true; 4382 init_completion(&mpi->unref_comp); 4383 spin_unlock(&port->mp.mpi_lock); 4384 4385 for (i = 0; i < comps; i++) 4386 wait_for_completion(&mpi->unref_comp); 4387 4388 spin_lock(&port->mp.mpi_lock); 4389 mpi->unaffiliate = false; 4390 } 4391 4392 port->mp.mpi = NULL; 4393 4394 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4395 4396 spin_unlock(&port->mp.mpi_lock); 4397 4398 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 4399 4400 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 4401 /* Log an error, still needed to cleanup the pointers and add 4402 * it back to the list. 4403 */ 4404 if (err) 4405 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 4406 port_num + 1); 4407 4408 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 4409 } 4410 4411 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4412 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 4413 struct mlx5_ib_multiport_info *mpi) 4414 { 4415 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4416 int err; 4417 4418 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 4419 if (ibdev->port[port_num].mp.mpi) { 4420 mlx5_ib_warn(ibdev, "port %d already affiliated.\n", 4421 port_num + 1); 4422 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4423 return false; 4424 } 4425 4426 ibdev->port[port_num].mp.mpi = mpi; 4427 mpi->ibdev = ibdev; 4428 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4429 4430 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 4431 if (err) 4432 goto unbind; 4433 4434 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 4435 if (err) 4436 goto unbind; 4437 4438 err = mlx5_add_netdev_notifier(ibdev, port_num); 4439 if (err) { 4440 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 4441 port_num + 1); 4442 goto unbind; 4443 } 4444 4445 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 4446 if (err) 4447 goto unbind; 4448 4449 return true; 4450 4451 unbind: 4452 mlx5_ib_unbind_slave_port(ibdev, mpi); 4453 return false; 4454 } 4455 4456 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 4457 { 4458 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4459 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4460 port_num + 1); 4461 struct mlx5_ib_multiport_info *mpi; 4462 int err; 4463 int i; 4464 4465 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4466 return 0; 4467 4468 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4469 &dev->sys_image_guid); 4470 if (err) 4471 return err; 4472 4473 err = mlx5_nic_vport_enable_roce(dev->mdev); 4474 if (err) 4475 return err; 4476 4477 mutex_lock(&mlx5_ib_multiport_mutex); 4478 for (i = 0; i < dev->num_ports; i++) { 4479 bool bound = false; 4480 4481 /* build a stub multiport info struct for the native port. */ 4482 if (i == port_num) { 4483 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4484 if (!mpi) { 4485 mutex_unlock(&mlx5_ib_multiport_mutex); 4486 mlx5_nic_vport_disable_roce(dev->mdev); 4487 return -ENOMEM; 4488 } 4489 4490 mpi->is_master = true; 4491 mpi->mdev = dev->mdev; 4492 mpi->sys_image_guid = dev->sys_image_guid; 4493 dev->port[i].mp.mpi = mpi; 4494 mpi->ibdev = dev; 4495 mpi = NULL; 4496 continue; 4497 } 4498 4499 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4500 list) { 4501 if (dev->sys_image_guid == mpi->sys_image_guid && 4502 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 4503 bound = mlx5_ib_bind_slave_port(dev, mpi); 4504 } 4505 4506 if (bound) { 4507 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 4508 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4509 list_del(&mpi->list); 4510 break; 4511 } 4512 } 4513 if (!bound) { 4514 get_port_caps(dev, i + 1); 4515 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4516 i + 1); 4517 } 4518 } 4519 4520 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4521 mutex_unlock(&mlx5_ib_multiport_mutex); 4522 return err; 4523 } 4524 4525 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4526 { 4527 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4528 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4529 port_num + 1); 4530 int i; 4531 4532 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4533 return; 4534 4535 mutex_lock(&mlx5_ib_multiport_mutex); 4536 for (i = 0; i < dev->num_ports; i++) { 4537 if (dev->port[i].mp.mpi) { 4538 /* Destroy the native port stub */ 4539 if (i == port_num) { 4540 kfree(dev->port[i].mp.mpi); 4541 dev->port[i].mp.mpi = NULL; 4542 } else { 4543 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 4544 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 4545 } 4546 } 4547 } 4548 4549 mlx5_ib_dbg(dev, "removing from devlist\n"); 4550 list_del(&dev->ib_dev_list); 4551 mutex_unlock(&mlx5_ib_multiport_mutex); 4552 4553 mlx5_nic_vport_disable_roce(dev->mdev); 4554 } 4555 4556 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4557 { 4558 mlx5_ib_cleanup_multiport_master(dev); 4559 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4560 cleanup_srcu_struct(&dev->mr_srcu); 4561 #endif 4562 kfree(dev->port); 4563 } 4564 4565 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4566 { 4567 struct mlx5_core_dev *mdev = dev->mdev; 4568 const char *name; 4569 int err; 4570 int i; 4571 4572 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 4573 GFP_KERNEL); 4574 if (!dev->port) 4575 return -ENOMEM; 4576 4577 for (i = 0; i < dev->num_ports; i++) { 4578 spin_lock_init(&dev->port[i].mp.mpi_lock); 4579 rwlock_init(&dev->roce[i].netdev_lock); 4580 } 4581 4582 err = mlx5_ib_init_multiport_master(dev); 4583 if (err) 4584 goto err_free_port; 4585 4586 if (!mlx5_core_mp_enabled(mdev)) { 4587 for (i = 1; i <= dev->num_ports; i++) { 4588 err = get_port_caps(dev, i); 4589 if (err) 4590 break; 4591 } 4592 } else { 4593 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 4594 } 4595 if (err) 4596 goto err_mp; 4597 4598 if (mlx5_use_mad_ifc(dev)) 4599 get_ext_port_caps(dev); 4600 4601 if (!mlx5_lag_is_active(mdev)) 4602 name = "mlx5_%d"; 4603 else 4604 name = "mlx5_bond_%d"; 4605 4606 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 4607 dev->ib_dev.owner = THIS_MODULE; 4608 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4609 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4610 dev->ib_dev.phys_port_cnt = dev->num_ports; 4611 dev->ib_dev.num_comp_vectors = 4612 dev->mdev->priv.eq_table.num_comp_vectors; 4613 dev->ib_dev.dev.parent = &mdev->pdev->dev; 4614 4615 mutex_init(&dev->cap_mask_mutex); 4616 INIT_LIST_HEAD(&dev->qp_list); 4617 spin_lock_init(&dev->reset_flow_resource_lock); 4618 4619 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4620 err = init_srcu_struct(&dev->mr_srcu); 4621 if (err) 4622 goto err_free_port; 4623 #endif 4624 4625 return 0; 4626 err_mp: 4627 mlx5_ib_cleanup_multiport_master(dev); 4628 4629 err_free_port: 4630 kfree(dev->port); 4631 4632 return -ENOMEM; 4633 } 4634 4635 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 4636 { 4637 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 4638 4639 if (!dev->flow_db) 4640 return -ENOMEM; 4641 4642 mutex_init(&dev->flow_db->lock); 4643 4644 return 0; 4645 } 4646 4647 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 4648 { 4649 struct mlx5_ib_dev *nic_dev; 4650 4651 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 4652 4653 if (!nic_dev) 4654 return -EINVAL; 4655 4656 dev->flow_db = nic_dev->flow_db; 4657 4658 return 0; 4659 } 4660 4661 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 4662 { 4663 kfree(dev->flow_db); 4664 } 4665 4666 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4667 { 4668 struct mlx5_core_dev *mdev = dev->mdev; 4669 int err; 4670 4671 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 4672 dev->ib_dev.uverbs_cmd_mask = 4673 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 4674 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 4675 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 4676 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 4677 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 4678 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 4679 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 4680 (1ull << IB_USER_VERBS_CMD_REG_MR) | 4681 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 4682 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 4683 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 4684 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 4685 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 4686 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 4687 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 4688 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 4689 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 4690 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 4691 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 4692 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 4693 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 4694 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 4695 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 4696 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 4697 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 4698 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 4699 dev->ib_dev.uverbs_ex_cmd_mask = 4700 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 4701 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4702 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4703 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 4704 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 4705 4706 dev->ib_dev.query_device = mlx5_ib_query_device; 4707 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 4708 dev->ib_dev.query_gid = mlx5_ib_query_gid; 4709 dev->ib_dev.add_gid = mlx5_ib_add_gid; 4710 dev->ib_dev.del_gid = mlx5_ib_del_gid; 4711 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 4712 dev->ib_dev.modify_device = mlx5_ib_modify_device; 4713 dev->ib_dev.modify_port = mlx5_ib_modify_port; 4714 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 4715 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 4716 dev->ib_dev.mmap = mlx5_ib_mmap; 4717 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 4718 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 4719 dev->ib_dev.create_ah = mlx5_ib_create_ah; 4720 dev->ib_dev.query_ah = mlx5_ib_query_ah; 4721 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 4722 dev->ib_dev.create_srq = mlx5_ib_create_srq; 4723 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 4724 dev->ib_dev.query_srq = mlx5_ib_query_srq; 4725 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 4726 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 4727 dev->ib_dev.create_qp = mlx5_ib_create_qp; 4728 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 4729 dev->ib_dev.query_qp = mlx5_ib_query_qp; 4730 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 4731 dev->ib_dev.post_send = mlx5_ib_post_send; 4732 dev->ib_dev.post_recv = mlx5_ib_post_recv; 4733 dev->ib_dev.create_cq = mlx5_ib_create_cq; 4734 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 4735 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 4736 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 4737 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 4738 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 4739 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 4740 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 4741 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 4742 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 4743 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 4744 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 4745 dev->ib_dev.process_mad = mlx5_ib_process_mad; 4746 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 4747 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 4748 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 4749 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 4750 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 4751 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 4752 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 4753 4754 if (mlx5_core_is_pf(mdev)) { 4755 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 4756 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 4757 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 4758 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 4759 } 4760 4761 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 4762 4763 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4764 4765 if (MLX5_CAP_GEN(mdev, imaicl)) { 4766 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 4767 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 4768 dev->ib_dev.uverbs_cmd_mask |= 4769 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4770 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4771 } 4772 4773 if (MLX5_CAP_GEN(mdev, xrc)) { 4774 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 4775 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 4776 dev->ib_dev.uverbs_cmd_mask |= 4777 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4778 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4779 } 4780 4781 dev->ib_dev.create_flow = mlx5_ib_create_flow; 4782 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 4783 dev->ib_dev.uverbs_ex_cmd_mask |= 4784 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4785 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4786 4787 err = init_node_data(dev); 4788 if (err) 4789 return err; 4790 4791 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4792 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4793 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4794 mutex_init(&dev->lb_mutex); 4795 4796 return 0; 4797 } 4798 4799 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4800 { 4801 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 4802 dev->ib_dev.query_port = mlx5_ib_query_port; 4803 4804 return 0; 4805 } 4806 4807 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 4808 { 4809 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 4810 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 4811 4812 return 0; 4813 } 4814 4815 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev, 4816 u8 port_num) 4817 { 4818 int i; 4819 4820 for (i = 0; i < dev->num_ports; i++) { 4821 dev->roce[i].dev = dev; 4822 dev->roce[i].native_port_num = i + 1; 4823 dev->roce[i].last_port_state = IB_PORT_DOWN; 4824 } 4825 4826 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 4827 dev->ib_dev.create_wq = mlx5_ib_create_wq; 4828 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4829 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4830 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4831 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4832 4833 dev->ib_dev.uverbs_ex_cmd_mask |= 4834 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4835 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4836 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4837 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4838 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4839 4840 return mlx5_add_netdev_notifier(dev, port_num); 4841 } 4842 4843 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 4844 { 4845 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4846 4847 mlx5_remove_netdev_notifier(dev, port_num); 4848 } 4849 4850 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 4851 { 4852 struct mlx5_core_dev *mdev = dev->mdev; 4853 enum rdma_link_layer ll; 4854 int port_type_cap; 4855 int err = 0; 4856 u8 port_num; 4857 4858 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4859 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4860 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4861 4862 if (ll == IB_LINK_LAYER_ETHERNET) 4863 err = mlx5_ib_stage_common_roce_init(dev, port_num); 4864 4865 return err; 4866 } 4867 4868 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 4869 { 4870 mlx5_ib_stage_common_roce_cleanup(dev); 4871 } 4872 4873 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 4874 { 4875 struct mlx5_core_dev *mdev = dev->mdev; 4876 enum rdma_link_layer ll; 4877 int port_type_cap; 4878 u8 port_num; 4879 int err; 4880 4881 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4882 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4883 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4884 4885 if (ll == IB_LINK_LAYER_ETHERNET) { 4886 err = mlx5_ib_stage_common_roce_init(dev, port_num); 4887 if (err) 4888 return err; 4889 4890 err = mlx5_enable_eth(dev, port_num); 4891 if (err) 4892 goto cleanup; 4893 } 4894 4895 return 0; 4896 cleanup: 4897 mlx5_ib_stage_common_roce_cleanup(dev); 4898 4899 return err; 4900 } 4901 4902 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 4903 { 4904 struct mlx5_core_dev *mdev = dev->mdev; 4905 enum rdma_link_layer ll; 4906 int port_type_cap; 4907 u8 port_num; 4908 4909 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4910 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4911 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4912 4913 if (ll == IB_LINK_LAYER_ETHERNET) { 4914 mlx5_disable_eth(dev); 4915 mlx5_ib_stage_common_roce_cleanup(dev); 4916 } 4917 } 4918 4919 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 4920 { 4921 return create_dev_resources(&dev->devr); 4922 } 4923 4924 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 4925 { 4926 destroy_dev_resources(&dev->devr); 4927 } 4928 4929 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 4930 { 4931 mlx5_ib_internal_fill_odp_caps(dev); 4932 4933 return mlx5_ib_odp_init_one(dev); 4934 } 4935 4936 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 4937 { 4938 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4939 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 4940 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 4941 4942 return mlx5_ib_alloc_counters(dev); 4943 } 4944 4945 return 0; 4946 } 4947 4948 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 4949 { 4950 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4951 mlx5_ib_dealloc_counters(dev); 4952 } 4953 4954 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4955 { 4956 return mlx5_ib_init_cong_debugfs(dev, 4957 mlx5_core_native_port_num(dev->mdev) - 1); 4958 } 4959 4960 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4961 { 4962 mlx5_ib_cleanup_cong_debugfs(dev, 4963 mlx5_core_native_port_num(dev->mdev) - 1); 4964 } 4965 4966 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4967 { 4968 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4969 if (!dev->mdev->priv.uar) 4970 return -ENOMEM; 4971 return 0; 4972 } 4973 4974 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4975 { 4976 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4977 } 4978 4979 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4980 { 4981 int err; 4982 4983 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4984 if (err) 4985 return err; 4986 4987 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4988 if (err) 4989 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4990 4991 return err; 4992 } 4993 4994 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4995 { 4996 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4997 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4998 } 4999 5000 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 5001 { 5002 return ib_register_device(&dev->ib_dev, NULL); 5003 } 5004 5005 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 5006 { 5007 destroy_umrc_res(dev); 5008 } 5009 5010 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 5011 { 5012 ib_unregister_device(&dev->ib_dev); 5013 } 5014 5015 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 5016 { 5017 return create_umr_res(dev); 5018 } 5019 5020 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 5021 { 5022 init_delay_drop(dev); 5023 5024 return 0; 5025 } 5026 5027 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 5028 { 5029 cancel_delay_drop(dev); 5030 } 5031 5032 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev) 5033 { 5034 int err; 5035 int i; 5036 5037 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 5038 err = device_create_file(&dev->ib_dev.dev, 5039 mlx5_class_attributes[i]); 5040 if (err) 5041 return err; 5042 } 5043 5044 return 0; 5045 } 5046 5047 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev) 5048 { 5049 mlx5_ib_register_vport_reps(dev); 5050 5051 return 0; 5052 } 5053 5054 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev) 5055 { 5056 mlx5_ib_unregister_vport_reps(dev); 5057 } 5058 5059 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 5060 const struct mlx5_ib_profile *profile, 5061 int stage) 5062 { 5063 /* Number of stages to cleanup */ 5064 while (stage) { 5065 stage--; 5066 if (profile->stage[stage].cleanup) 5067 profile->stage[stage].cleanup(dev); 5068 } 5069 5070 ib_dealloc_device((struct ib_device *)dev); 5071 } 5072 5073 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num); 5074 5075 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 5076 const struct mlx5_ib_profile *profile) 5077 { 5078 int err; 5079 int i; 5080 5081 printk_once(KERN_INFO "%s", mlx5_version); 5082 5083 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5084 if (profile->stage[i].init) { 5085 err = profile->stage[i].init(dev); 5086 if (err) 5087 goto err_out; 5088 } 5089 } 5090 5091 dev->profile = profile; 5092 dev->ib_active = true; 5093 5094 return dev; 5095 5096 err_out: 5097 __mlx5_ib_remove(dev, profile, i); 5098 5099 return NULL; 5100 } 5101 5102 static const struct mlx5_ib_profile pf_profile = { 5103 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5104 mlx5_ib_stage_init_init, 5105 mlx5_ib_stage_init_cleanup), 5106 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 5107 mlx5_ib_stage_flow_db_init, 5108 mlx5_ib_stage_flow_db_cleanup), 5109 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5110 mlx5_ib_stage_caps_init, 5111 NULL), 5112 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5113 mlx5_ib_stage_non_default_cb, 5114 NULL), 5115 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5116 mlx5_ib_stage_roce_init, 5117 mlx5_ib_stage_roce_cleanup), 5118 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5119 mlx5_ib_stage_dev_res_init, 5120 mlx5_ib_stage_dev_res_cleanup), 5121 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5122 mlx5_ib_stage_odp_init, 5123 NULL), 5124 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5125 mlx5_ib_stage_counters_init, 5126 mlx5_ib_stage_counters_cleanup), 5127 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5128 mlx5_ib_stage_cong_debugfs_init, 5129 mlx5_ib_stage_cong_debugfs_cleanup), 5130 STAGE_CREATE(MLX5_IB_STAGE_UAR, 5131 mlx5_ib_stage_uar_init, 5132 mlx5_ib_stage_uar_cleanup), 5133 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5134 mlx5_ib_stage_bfrag_init, 5135 mlx5_ib_stage_bfrag_cleanup), 5136 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5137 NULL, 5138 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5139 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5140 mlx5_ib_stage_ib_reg_init, 5141 mlx5_ib_stage_ib_reg_cleanup), 5142 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5143 mlx5_ib_stage_post_ib_reg_umr_init, 5144 NULL), 5145 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5146 mlx5_ib_stage_delay_drop_init, 5147 mlx5_ib_stage_delay_drop_cleanup), 5148 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 5149 mlx5_ib_stage_class_attr_init, 5150 NULL), 5151 }; 5152 5153 static const struct mlx5_ib_profile nic_rep_profile = { 5154 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5155 mlx5_ib_stage_init_init, 5156 mlx5_ib_stage_init_cleanup), 5157 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 5158 mlx5_ib_stage_flow_db_init, 5159 mlx5_ib_stage_flow_db_cleanup), 5160 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5161 mlx5_ib_stage_caps_init, 5162 NULL), 5163 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5164 mlx5_ib_stage_rep_non_default_cb, 5165 NULL), 5166 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5167 mlx5_ib_stage_rep_roce_init, 5168 mlx5_ib_stage_rep_roce_cleanup), 5169 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5170 mlx5_ib_stage_dev_res_init, 5171 mlx5_ib_stage_dev_res_cleanup), 5172 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5173 mlx5_ib_stage_counters_init, 5174 mlx5_ib_stage_counters_cleanup), 5175 STAGE_CREATE(MLX5_IB_STAGE_UAR, 5176 mlx5_ib_stage_uar_init, 5177 mlx5_ib_stage_uar_cleanup), 5178 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5179 mlx5_ib_stage_bfrag_init, 5180 mlx5_ib_stage_bfrag_cleanup), 5181 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5182 NULL, 5183 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5184 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5185 mlx5_ib_stage_ib_reg_init, 5186 mlx5_ib_stage_ib_reg_cleanup), 5187 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5188 mlx5_ib_stage_post_ib_reg_umr_init, 5189 NULL), 5190 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 5191 mlx5_ib_stage_class_attr_init, 5192 NULL), 5193 STAGE_CREATE(MLX5_IB_STAGE_REP_REG, 5194 mlx5_ib_stage_rep_reg_init, 5195 mlx5_ib_stage_rep_reg_cleanup), 5196 }; 5197 5198 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num) 5199 { 5200 struct mlx5_ib_multiport_info *mpi; 5201 struct mlx5_ib_dev *dev; 5202 bool bound = false; 5203 int err; 5204 5205 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5206 if (!mpi) 5207 return NULL; 5208 5209 mpi->mdev = mdev; 5210 5211 err = mlx5_query_nic_vport_system_image_guid(mdev, 5212 &mpi->sys_image_guid); 5213 if (err) { 5214 kfree(mpi); 5215 return NULL; 5216 } 5217 5218 mutex_lock(&mlx5_ib_multiport_mutex); 5219 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5220 if (dev->sys_image_guid == mpi->sys_image_guid) 5221 bound = mlx5_ib_bind_slave_port(dev, mpi); 5222 5223 if (bound) { 5224 rdma_roce_rescan_device(&dev->ib_dev); 5225 break; 5226 } 5227 } 5228 5229 if (!bound) { 5230 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5231 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5232 } else { 5233 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1); 5234 } 5235 mutex_unlock(&mlx5_ib_multiport_mutex); 5236 5237 return mpi; 5238 } 5239 5240 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 5241 { 5242 enum rdma_link_layer ll; 5243 struct mlx5_ib_dev *dev; 5244 int port_type_cap; 5245 5246 printk_once(KERN_INFO "%s", mlx5_version); 5247 5248 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5249 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5250 5251 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) { 5252 u8 port_num = mlx5_core_native_port_num(mdev) - 1; 5253 5254 return mlx5_ib_add_slave_port(mdev, port_num); 5255 } 5256 5257 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 5258 if (!dev) 5259 return NULL; 5260 5261 dev->mdev = mdev; 5262 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5263 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5264 5265 if (MLX5_VPORT_MANAGER(mdev) && 5266 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 5267 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0); 5268 5269 return __mlx5_ib_add(dev, &nic_rep_profile); 5270 } 5271 5272 return __mlx5_ib_add(dev, &pf_profile); 5273 } 5274 5275 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 5276 { 5277 struct mlx5_ib_multiport_info *mpi; 5278 struct mlx5_ib_dev *dev; 5279 5280 if (mlx5_core_is_mp_slave(mdev)) { 5281 mpi = context; 5282 mutex_lock(&mlx5_ib_multiport_mutex); 5283 if (mpi->ibdev) 5284 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5285 list_del(&mpi->list); 5286 mutex_unlock(&mlx5_ib_multiport_mutex); 5287 return; 5288 } 5289 5290 dev = context; 5291 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5292 } 5293 5294 static struct mlx5_interface mlx5_ib_interface = { 5295 .add = mlx5_ib_add, 5296 .remove = mlx5_ib_remove, 5297 .event = mlx5_ib_event, 5298 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5299 .pfault = mlx5_ib_pfault, 5300 #endif 5301 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 5302 }; 5303 5304 static int __init mlx5_ib_init(void) 5305 { 5306 int err; 5307 5308 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5309 if (!mlx5_ib_event_wq) 5310 return -ENOMEM; 5311 5312 mlx5_ib_odp_init(); 5313 5314 err = mlx5_register_interface(&mlx5_ib_interface); 5315 5316 return err; 5317 } 5318 5319 static void __exit mlx5_ib_cleanup(void) 5320 { 5321 mlx5_unregister_interface(&mlx5_ib_interface); 5322 destroy_workqueue(mlx5_ib_event_wq); 5323 } 5324 5325 module_init(mlx5_ib_init); 5326 module_exit(mlx5_ib_cleanup); 5327