1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef NIC_H 10 #define NIC_H 11 12 #include <linux/netdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include "thunder_bgx.h" 16 17 /* PCI device IDs */ 18 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 19 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 20 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 21 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 22 23 /* Subsystem device IDs */ 24 #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E 25 #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E 26 #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E 27 28 #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E 29 #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134 30 #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234 31 #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334 32 33 34 /* PCI BAR nos */ 35 #define PCI_CFG_REG_BAR_NUM 0 36 #define PCI_MSIX_REG_BAR_NUM 4 37 38 /* NIC SRIOV VF count */ 39 #define MAX_NUM_VFS_SUPPORTED 128 40 #define DEFAULT_NUM_VF_ENABLED 8 41 42 #define NIC_TNS_BYPASS_MODE 0 43 #define NIC_TNS_MODE 1 44 45 /* NIC priv flags */ 46 #define NIC_SRIOV_ENABLED BIT(0) 47 48 /* Min/Max packet size */ 49 #define NIC_HW_MIN_FRS 64 50 #define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */ 51 52 /* Max pkinds */ 53 #define NIC_MAX_PKIND 16 54 55 /* Max when CPI_ALG is IP diffserv */ 56 #define NIC_MAX_CPI_PER_LMAC 64 57 58 /* NIC VF Interrupts */ 59 #define NICVF_INTR_CQ 0 60 #define NICVF_INTR_SQ 1 61 #define NICVF_INTR_RBDR 2 62 #define NICVF_INTR_PKT_DROP 3 63 #define NICVF_INTR_TCP_TIMER 4 64 #define NICVF_INTR_MBOX 5 65 #define NICVF_INTR_QS_ERR 6 66 67 #define NICVF_INTR_CQ_SHIFT 0 68 #define NICVF_INTR_SQ_SHIFT 8 69 #define NICVF_INTR_RBDR_SHIFT 16 70 #define NICVF_INTR_PKT_DROP_SHIFT 20 71 #define NICVF_INTR_TCP_TIMER_SHIFT 21 72 #define NICVF_INTR_MBOX_SHIFT 22 73 #define NICVF_INTR_QS_ERR_SHIFT 23 74 75 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 76 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 77 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 78 #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) 79 #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) 80 #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) 81 #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) 82 83 /* MSI-X interrupts */ 84 #define NIC_PF_MSIX_VECTORS 10 85 #define NIC_VF_MSIX_VECTORS 20 86 87 #define NIC_PF_INTR_ID_ECC0_SBE 0 88 #define NIC_PF_INTR_ID_ECC0_DBE 1 89 #define NIC_PF_INTR_ID_ECC1_SBE 2 90 #define NIC_PF_INTR_ID_ECC1_DBE 3 91 #define NIC_PF_INTR_ID_ECC2_SBE 4 92 #define NIC_PF_INTR_ID_ECC2_DBE 5 93 #define NIC_PF_INTR_ID_ECC3_SBE 6 94 #define NIC_PF_INTR_ID_ECC3_DBE 7 95 #define NIC_PF_INTR_ID_MBOX0 8 96 #define NIC_PF_INTR_ID_MBOX1 9 97 98 /* Minimum FIFO level before all packets for the CQ are dropped 99 * 100 * This value ensures that once a packet has been "accepted" 101 * for reception it will not get dropped due to non-availability 102 * of CQ descriptor. An errata in HW mandates this value to be 103 * atleast 0x100. 104 */ 105 #define NICPF_CQM_MIN_DROP_LEVEL 0x100 106 107 /* Global timer for CQ timer thresh interrupts 108 * Calculated for SCLK of 700Mhz 109 * value written should be a 1/16th of what is expected 110 * 111 * 1 tick per 0.025usec 112 */ 113 #define NICPF_CLK_PER_INT_TICK 1 114 115 /* Time to wait before we decide that a SQ is stuck. 116 * 117 * Since both pkt rx and tx notifications are done with same CQ, 118 * when packets are being received at very high rate (eg: L2 forwarding) 119 * then freeing transmitted skbs will be delayed and watchdog 120 * will kick in, resetting interface. Hence keeping this value high. 121 */ 122 #define NICVF_TX_TIMEOUT (50 * HZ) 123 124 struct nicvf_cq_poll { 125 struct nicvf *nicvf; 126 u8 cq_idx; /* Completion queue index */ 127 struct napi_struct napi; 128 }; 129 130 #define NIC_MAX_RSS_HASH_BITS 8 131 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 132 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 133 134 struct nicvf_rss_info { 135 bool enable; 136 #define RSS_L2_EXTENDED_HASH_ENA BIT(0) 137 #define RSS_IP_HASH_ENA BIT(1) 138 #define RSS_TCP_HASH_ENA BIT(2) 139 #define RSS_TCP_SYN_DIS BIT(3) 140 #define RSS_UDP_HASH_ENA BIT(4) 141 #define RSS_L4_EXTENDED_HASH_ENA BIT(5) 142 #define RSS_ROCE_ENA BIT(6) 143 #define RSS_L3_BI_DIRECTION_ENA BIT(7) 144 #define RSS_L4_BI_DIRECTION_ENA BIT(8) 145 u64 cfg; 146 u8 hash_bits; 147 u16 rss_size; 148 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 149 u64 key[RSS_HASH_KEY_SIZE]; 150 } ____cacheline_aligned_in_smp; 151 152 struct nicvf_pfc { 153 u8 autoneg; 154 u8 fc_rx; 155 u8 fc_tx; 156 }; 157 158 enum rx_stats_reg_offset { 159 RX_OCTS = 0x0, 160 RX_UCAST = 0x1, 161 RX_BCAST = 0x2, 162 RX_MCAST = 0x3, 163 RX_RED = 0x4, 164 RX_RED_OCTS = 0x5, 165 RX_ORUN = 0x6, 166 RX_ORUN_OCTS = 0x7, 167 RX_FCS = 0x8, 168 RX_L2ERR = 0x9, 169 RX_DRP_BCAST = 0xa, 170 RX_DRP_MCAST = 0xb, 171 RX_DRP_L3BCAST = 0xc, 172 RX_DRP_L3MCAST = 0xd, 173 RX_STATS_ENUM_LAST, 174 }; 175 176 enum tx_stats_reg_offset { 177 TX_OCTS = 0x0, 178 TX_UCAST = 0x1, 179 TX_BCAST = 0x2, 180 TX_MCAST = 0x3, 181 TX_DROP = 0x4, 182 TX_STATS_ENUM_LAST, 183 }; 184 185 struct nicvf_hw_stats { 186 u64 rx_bytes; 187 u64 rx_frames; 188 u64 rx_ucast_frames; 189 u64 rx_bcast_frames; 190 u64 rx_mcast_frames; 191 u64 rx_drops; 192 u64 rx_drop_red; 193 u64 rx_drop_red_bytes; 194 u64 rx_drop_overrun; 195 u64 rx_drop_overrun_bytes; 196 u64 rx_drop_bcast; 197 u64 rx_drop_mcast; 198 u64 rx_drop_l3_bcast; 199 u64 rx_drop_l3_mcast; 200 u64 rx_fcs_errors; 201 u64 rx_l2_errors; 202 203 u64 tx_bytes; 204 u64 tx_frames; 205 u64 tx_ucast_frames; 206 u64 tx_bcast_frames; 207 u64 tx_mcast_frames; 208 u64 tx_drops; 209 }; 210 211 struct nicvf_drv_stats { 212 /* CQE Rx errs */ 213 u64 rx_bgx_truncated_pkts; 214 u64 rx_jabber_errs; 215 u64 rx_fcs_errs; 216 u64 rx_bgx_errs; 217 u64 rx_prel2_errs; 218 u64 rx_l2_hdr_malformed; 219 u64 rx_oversize; 220 u64 rx_undersize; 221 u64 rx_l2_len_mismatch; 222 u64 rx_l2_pclp; 223 u64 rx_ip_ver_errs; 224 u64 rx_ip_csum_errs; 225 u64 rx_ip_hdr_malformed; 226 u64 rx_ip_payload_malformed; 227 u64 rx_ip_ttl_errs; 228 u64 rx_l3_pclp; 229 u64 rx_l4_malformed; 230 u64 rx_l4_csum_errs; 231 u64 rx_udp_len_errs; 232 u64 rx_l4_port_errs; 233 u64 rx_tcp_flag_errs; 234 u64 rx_tcp_offset_errs; 235 u64 rx_l4_pclp; 236 u64 rx_truncated_pkts; 237 238 /* CQE Tx errs */ 239 u64 tx_desc_fault; 240 u64 tx_hdr_cons_err; 241 u64 tx_subdesc_err; 242 u64 tx_max_size_exceeded; 243 u64 tx_imm_size_oflow; 244 u64 tx_data_seq_err; 245 u64 tx_mem_seq_err; 246 u64 tx_lock_viol; 247 u64 tx_data_fault; 248 u64 tx_tstmp_conflict; 249 u64 tx_tstmp_timeout; 250 u64 tx_mem_fault; 251 u64 tx_csum_overlap; 252 u64 tx_csum_overflow; 253 254 /* driver debug stats */ 255 u64 tx_tso; 256 u64 tx_timeout; 257 u64 txq_stop; 258 u64 txq_wake; 259 260 u64 rcv_buffer_alloc_failures; 261 u64 page_alloc; 262 263 struct u64_stats_sync syncp; 264 }; 265 266 struct cavium_ptp; 267 268 struct xcast_addr { 269 struct list_head list; 270 u64 addr; 271 }; 272 273 struct xcast_addr_list { 274 struct list_head list; 275 int count; 276 }; 277 278 struct nicvf_work { 279 struct delayed_work work; 280 u8 mode; 281 struct xcast_addr_list *mc; 282 }; 283 284 struct nicvf { 285 struct nicvf *pnicvf; 286 struct net_device *netdev; 287 struct pci_dev *pdev; 288 void __iomem *reg_base; 289 struct bpf_prog *xdp_prog; 290 #define MAX_QUEUES_PER_QSET 8 291 struct queue_set *qs; 292 void *iommu_domain; 293 u8 vf_id; 294 u8 sqs_id; 295 bool sqs_mode; 296 bool hw_tso; 297 bool t88; 298 299 /* Receive buffer alloc */ 300 u32 rb_page_offset; 301 u16 rb_pageref; 302 bool rb_alloc_fail; 303 bool rb_work_scheduled; 304 struct page *rb_page; 305 struct delayed_work rbdr_work; 306 struct tasklet_struct rbdr_task; 307 308 /* Secondary Qset */ 309 u8 sqs_count; 310 #define MAX_SQS_PER_VF_SINGLE_NODE 5 311 #define MAX_SQS_PER_VF 11 312 struct nicvf *snicvf[MAX_SQS_PER_VF]; 313 314 /* Queue count */ 315 u8 rx_queues; 316 u8 tx_queues; 317 u8 xdp_tx_queues; 318 u8 max_queues; 319 320 u8 node; 321 u8 cpi_alg; 322 bool link_up; 323 u8 mac_type; 324 u8 duplex; 325 u32 speed; 326 bool tns_mode; 327 bool loopback_supported; 328 struct nicvf_rss_info rss_info; 329 struct nicvf_pfc pfc; 330 struct tasklet_struct qs_err_task; 331 struct work_struct reset_task; 332 struct nicvf_work rx_mode_work; 333 334 /* PTP timestamp */ 335 struct cavium_ptp *ptp_clock; 336 /* Inbound timestamping is on */ 337 bool hw_rx_tstamp; 338 /* When the packet that requires timestamping is sent, hardware inserts 339 * two entries to the completion queue. First is the regular 340 * CQE_TYPE_SEND entry that signals that the packet was sent. 341 * The second is CQE_TYPE_SEND_PTP that contains the actual timestamp 342 * for that packet. 343 * `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND 344 * entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP 345 * entry. 346 * So `ptp_skb` is used to hold the pointer to the packet between 347 * the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers. 348 */ 349 struct sk_buff *ptp_skb; 350 /* `tx_ptp_skbs` is set when the hardware is sending a packet that 351 * requires timestamping. Cavium hardware can not process more than one 352 * such packet at once so this is set each time the driver submits 353 * a packet that requires timestamping to the send queue and clears 354 * each time it receives the entry on the completion queue saying 355 * that such packet was sent. 356 * So `tx_ptp_skbs` prevents driver from submitting more than one 357 * packet that requires timestamping to the hardware for transmitting. 358 */ 359 atomic_t tx_ptp_skbs; 360 361 /* Interrupt coalescing settings */ 362 u32 cq_coalesce_usecs; 363 u32 msg_enable; 364 365 /* Stats */ 366 struct nicvf_hw_stats hw_stats; 367 struct nicvf_drv_stats __percpu *drv_stats; 368 struct bgx_stats bgx_stats; 369 370 /* Napi */ 371 struct nicvf_cq_poll *napi[8]; 372 373 /* MSI-X */ 374 u8 num_vec; 375 char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15]; 376 bool irq_allocated[NIC_VF_MSIX_VECTORS]; 377 cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; 378 379 /* VF <-> PF mailbox communication */ 380 bool pf_acked; 381 bool pf_nacked; 382 bool set_mac_pending; 383 } ____cacheline_aligned_in_smp; 384 385 /* PF <--> VF Mailbox communication 386 * Eight 64bit registers are shared between PF and VF. 387 * Separate set for each VF. 388 * Writing '1' into last register mbx7 means end of message. 389 */ 390 391 /* PF <--> VF mailbox communication */ 392 #define NIC_PF_VF_MAILBOX_SIZE 2 393 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 394 395 /* Mailbox message types */ 396 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 397 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 398 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 399 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 400 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 401 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 402 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 403 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 404 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 405 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 406 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 407 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 408 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 409 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 410 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 411 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 412 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 413 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 414 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 415 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 416 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 417 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 418 #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */ 419 #define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */ 420 #define NIC_MBOX_MSG_PTP_CFG 0x19 /* HW packet timestamp */ 421 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 422 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 423 #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */ 424 #define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* Add MAC to DCAM filters */ 425 #define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST RX mode */ 426 427 struct nic_cfg_msg { 428 u8 msg; 429 u8 vf_id; 430 u8 node_id; 431 u8 tns_mode:1; 432 u8 sqs_mode:1; 433 u8 loopback_supported:1; 434 u8 mac_addr[ETH_ALEN]; 435 }; 436 437 /* Qset configuration */ 438 struct qs_cfg_msg { 439 u8 msg; 440 u8 num; 441 u8 sqs_count; 442 u64 cfg; 443 }; 444 445 /* Receive queue configuration */ 446 struct rq_cfg_msg { 447 u8 msg; 448 u8 qs_num; 449 u8 rq_num; 450 u64 cfg; 451 }; 452 453 /* Send queue configuration */ 454 struct sq_cfg_msg { 455 u8 msg; 456 u8 qs_num; 457 u8 sq_num; 458 bool sqs_mode; 459 u64 cfg; 460 }; 461 462 /* Set VF's MAC address */ 463 struct set_mac_msg { 464 u8 msg; 465 u8 vf_id; 466 u8 mac_addr[ETH_ALEN]; 467 }; 468 469 /* Set Maximum frame size */ 470 struct set_frs_msg { 471 u8 msg; 472 u8 vf_id; 473 u16 max_frs; 474 }; 475 476 /* Set CPI algorithm type */ 477 struct cpi_cfg_msg { 478 u8 msg; 479 u8 vf_id; 480 u8 rq_cnt; 481 u8 cpi_alg; 482 }; 483 484 /* Get RSS table size */ 485 struct rss_sz_msg { 486 u8 msg; 487 u8 vf_id; 488 u16 ind_tbl_size; 489 }; 490 491 /* Set RSS configuration */ 492 struct rss_cfg_msg { 493 u8 msg; 494 u8 vf_id; 495 u8 hash_bits; 496 u8 tbl_len; 497 u8 tbl_offset; 498 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 499 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 500 }; 501 502 struct bgx_stats_msg { 503 u8 msg; 504 u8 vf_id; 505 u8 rx; 506 u8 idx; 507 u64 stats; 508 }; 509 510 /* Physical interface link status */ 511 struct bgx_link_status { 512 u8 msg; 513 u8 mac_type; 514 u8 link_up; 515 u8 duplex; 516 u32 speed; 517 }; 518 519 /* Get Extra Qset IDs */ 520 struct sqs_alloc { 521 u8 msg; 522 u8 vf_id; 523 u8 qs_count; 524 }; 525 526 struct nicvf_ptr { 527 u8 msg; 528 u8 vf_id; 529 bool sqs_mode; 530 u8 sqs_id; 531 u64 nicvf; 532 }; 533 534 /* Set interface in loopback mode */ 535 struct set_loopback { 536 u8 msg; 537 u8 vf_id; 538 bool enable; 539 }; 540 541 /* Reset statistics counters */ 542 struct reset_stat_cfg { 543 u8 msg; 544 /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */ 545 u16 rx_stat_mask; 546 /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */ 547 u8 tx_stat_mask; 548 /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1) 549 * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1) 550 * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1) 551 * .. 552 * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1) 553 * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1) 554 */ 555 u16 rq_stat_mask; 556 /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1) 557 * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1) 558 * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1) 559 * .. 560 * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1) 561 * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1) 562 */ 563 u16 sq_stat_mask; 564 }; 565 566 struct pfc { 567 u8 msg; 568 u8 get; /* Get or set PFC settings */ 569 u8 autoneg; 570 u8 fc_rx; 571 u8 fc_tx; 572 }; 573 574 struct set_ptp { 575 u8 msg; 576 bool enable; 577 }; 578 579 struct xcast { 580 u8 msg; 581 union { 582 u8 mode; 583 u64 mac; 584 } data; 585 }; 586 587 /* 128 bit shared memory between PF and each VF */ 588 union nic_mbx { 589 struct { u8 msg; } msg; 590 struct nic_cfg_msg nic_cfg; 591 struct qs_cfg_msg qs; 592 struct rq_cfg_msg rq; 593 struct sq_cfg_msg sq; 594 struct set_mac_msg mac; 595 struct set_frs_msg frs; 596 struct cpi_cfg_msg cpi_cfg; 597 struct rss_sz_msg rss_size; 598 struct rss_cfg_msg rss_cfg; 599 struct bgx_stats_msg bgx_stats; 600 struct bgx_link_status link_status; 601 struct sqs_alloc sqs_alloc; 602 struct nicvf_ptr nicvf; 603 struct set_loopback lbk; 604 struct reset_stat_cfg reset_stat; 605 struct pfc pfc; 606 struct set_ptp ptp; 607 struct xcast xcast; 608 }; 609 610 #define NIC_NODE_ID_MASK 0x03 611 #define NIC_NODE_ID_SHIFT 44 612 613 static inline int nic_get_node_id(struct pci_dev *pdev) 614 { 615 u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); 616 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 617 } 618 619 static inline bool pass1_silicon(struct pci_dev *pdev) 620 { 621 return (pdev->revision < 8) && 622 (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); 623 } 624 625 static inline bool pass2_silicon(struct pci_dev *pdev) 626 { 627 return (pdev->revision >= 8) && 628 (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); 629 } 630 631 int nicvf_set_real_num_queues(struct net_device *netdev, 632 int tx_queues, int rx_queues); 633 int nicvf_open(struct net_device *netdev); 634 int nicvf_stop(struct net_device *netdev); 635 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 636 void nicvf_config_rss(struct nicvf *nic); 637 void nicvf_set_rss_key(struct nicvf *nic); 638 void nicvf_set_ethtool_ops(struct net_device *netdev); 639 void nicvf_update_stats(struct nicvf *nic); 640 void nicvf_update_lmac_stats(struct nicvf *nic); 641 642 #endif /* NIC_H */ 643