1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP. 5 * 6 */ 7 8 #include <linux/err.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/pinctrl/pinctrl.h> 15 16 #include "pinctrl-imx.h" 17 18 enum imx6sll_pads { 19 MX6SLL_PAD_RESERVE0 = 0, 20 MX6SLL_PAD_RESERVE1 = 1, 21 MX6SLL_PAD_RESERVE2 = 2, 22 MX6SLL_PAD_RESERVE3 = 3, 23 MX6SLL_PAD_RESERVE4 = 4, 24 MX6SLL_PAD_WDOG_B = 5, 25 MX6SLL_PAD_REF_CLK_24M = 6, 26 MX6SLL_PAD_REF_CLK_32K = 7, 27 MX6SLL_PAD_PWM1 = 8, 28 MX6SLL_PAD_KEY_COL0 = 9, 29 MX6SLL_PAD_KEY_ROW0 = 10, 30 MX6SLL_PAD_KEY_COL1 = 11, 31 MX6SLL_PAD_KEY_ROW1 = 12, 32 MX6SLL_PAD_KEY_COL2 = 13, 33 MX6SLL_PAD_KEY_ROW2 = 14, 34 MX6SLL_PAD_KEY_COL3 = 15, 35 MX6SLL_PAD_KEY_ROW3 = 16, 36 MX6SLL_PAD_KEY_COL4 = 17, 37 MX6SLL_PAD_KEY_ROW4 = 18, 38 MX6SLL_PAD_KEY_COL5 = 19, 39 MX6SLL_PAD_KEY_ROW5 = 20, 40 MX6SLL_PAD_KEY_COL6 = 21, 41 MX6SLL_PAD_KEY_ROW6 = 22, 42 MX6SLL_PAD_KEY_COL7 = 23, 43 MX6SLL_PAD_KEY_ROW7 = 24, 44 MX6SLL_PAD_EPDC_DATA00 = 25, 45 MX6SLL_PAD_EPDC_DATA01 = 26, 46 MX6SLL_PAD_EPDC_DATA02 = 27, 47 MX6SLL_PAD_EPDC_DATA03 = 28, 48 MX6SLL_PAD_EPDC_DATA04 = 29, 49 MX6SLL_PAD_EPDC_DATA05 = 30, 50 MX6SLL_PAD_EPDC_DATA06 = 31, 51 MX6SLL_PAD_EPDC_DATA07 = 32, 52 MX6SLL_PAD_EPDC_DATA08 = 33, 53 MX6SLL_PAD_EPDC_DATA09 = 34, 54 MX6SLL_PAD_EPDC_DATA10 = 35, 55 MX6SLL_PAD_EPDC_DATA11 = 36, 56 MX6SLL_PAD_EPDC_DATA12 = 37, 57 MX6SLL_PAD_EPDC_DATA13 = 38, 58 MX6SLL_PAD_EPDC_DATA14 = 39, 59 MX6SLL_PAD_EPDC_DATA15 = 40, 60 MX6SLL_PAD_EPDC_SDCLK = 41, 61 MX6SLL_PAD_EPDC_SDLE = 42, 62 MX6SLL_PAD_EPDC_SDOE = 43, 63 MX6SLL_PAD_EPDC_SDSHR = 44, 64 MX6SLL_PAD_EPDC_SDCE0 = 45, 65 MX6SLL_PAD_EPDC_SDCE1 = 46, 66 MX6SLL_PAD_EPDC_SDCE2 = 47, 67 MX6SLL_PAD_EPDC_SDCE3 = 48, 68 MX6SLL_PAD_EPDC_GDCLK = 49, 69 MX6SLL_PAD_EPDC_GDOE = 50, 70 MX6SLL_PAD_EPDC_GDRL = 51, 71 MX6SLL_PAD_EPDC_GDSP = 52, 72 MX6SLL_PAD_EPDC_VCOM0 = 53, 73 MX6SLL_PAD_EPDC_VCOM1 = 54, 74 MX6SLL_PAD_EPDC_BDR0 = 55, 75 MX6SLL_PAD_EPDC_BDR1 = 56, 76 MX6SLL_PAD_EPDC_PWR_CTRL0 = 57, 77 MX6SLL_PAD_EPDC_PWR_CTRL1 = 58, 78 MX6SLL_PAD_EPDC_PWR_CTRL2 = 59, 79 MX6SLL_PAD_EPDC_PWR_CTRL3 = 60, 80 MX6SLL_PAD_EPDC_PWR_COM = 61, 81 MX6SLL_PAD_EPDC_PWR_INT = 62, 82 MX6SLL_PAD_EPDC_PWR_STAT = 63, 83 MX6SLL_PAD_EPDC_PWR_WAKE = 64, 84 MX6SLL_PAD_LCD_CLK = 65, 85 MX6SLL_PAD_LCD_ENABLE = 66, 86 MX6SLL_PAD_LCD_HSYNC = 67, 87 MX6SLL_PAD_LCD_VSYNC = 68, 88 MX6SLL_PAD_LCD_RESET = 69, 89 MX6SLL_PAD_LCD_DATA00 = 70, 90 MX6SLL_PAD_LCD_DATA01 = 71, 91 MX6SLL_PAD_LCD_DATA02 = 72, 92 MX6SLL_PAD_LCD_DATA03 = 73, 93 MX6SLL_PAD_LCD_DATA04 = 74, 94 MX6SLL_PAD_LCD_DATA05 = 75, 95 MX6SLL_PAD_LCD_DATA06 = 76, 96 MX6SLL_PAD_LCD_DATA07 = 77, 97 MX6SLL_PAD_LCD_DATA08 = 78, 98 MX6SLL_PAD_LCD_DATA09 = 79, 99 MX6SLL_PAD_LCD_DATA10 = 80, 100 MX6SLL_PAD_LCD_DATA11 = 81, 101 MX6SLL_PAD_LCD_DATA12 = 82, 102 MX6SLL_PAD_LCD_DATA13 = 83, 103 MX6SLL_PAD_LCD_DATA14 = 84, 104 MX6SLL_PAD_LCD_DATA15 = 85, 105 MX6SLL_PAD_LCD_DATA16 = 86, 106 MX6SLL_PAD_LCD_DATA17 = 87, 107 MX6SLL_PAD_LCD_DATA18 = 88, 108 MX6SLL_PAD_LCD_DATA19 = 89, 109 MX6SLL_PAD_LCD_DATA20 = 90, 110 MX6SLL_PAD_LCD_DATA21 = 91, 111 MX6SLL_PAD_LCD_DATA22 = 92, 112 MX6SLL_PAD_LCD_DATA23 = 93, 113 MX6SLL_PAD_AUD_RXFS = 94, 114 MX6SLL_PAD_AUD_RXC = 95, 115 MX6SLL_PAD_AUD_RXD = 96, 116 MX6SLL_PAD_AUD_TXC = 97, 117 MX6SLL_PAD_AUD_TXFS = 98, 118 MX6SLL_PAD_AUD_TXD = 99, 119 MX6SLL_PAD_AUD_MCLK = 100, 120 MX6SLL_PAD_UART1_RXD = 101, 121 MX6SLL_PAD_UART1_TXD = 102, 122 MX6SLL_PAD_I2C1_SCL = 103, 123 MX6SLL_PAD_I2C1_SDA = 104, 124 MX6SLL_PAD_I2C2_SCL = 105, 125 MX6SLL_PAD_I2C2_SDA = 106, 126 MX6SLL_PAD_ECSPI1_SCLK = 107, 127 MX6SLL_PAD_ECSPI1_MOSI = 108, 128 MX6SLL_PAD_ECSPI1_MISO = 109, 129 MX6SLL_PAD_ECSPI1_SS0 = 110, 130 MX6SLL_PAD_ECSPI2_SCLK = 111, 131 MX6SLL_PAD_ECSPI2_MOSI = 112, 132 MX6SLL_PAD_ECSPI2_MISO = 113, 133 MX6SLL_PAD_ECSPI2_SS0 = 114, 134 MX6SLL_PAD_SD1_CLK = 115, 135 MX6SLL_PAD_SD1_CMD = 116, 136 MX6SLL_PAD_SD1_DATA0 = 117, 137 MX6SLL_PAD_SD1_DATA1 = 118, 138 MX6SLL_PAD_SD1_DATA2 = 119, 139 MX6SLL_PAD_SD1_DATA3 = 120, 140 MX6SLL_PAD_SD1_DATA4 = 121, 141 MX6SLL_PAD_SD1_DATA5 = 122, 142 MX6SLL_PAD_SD1_DATA6 = 123, 143 MX6SLL_PAD_SD1_DATA7 = 124, 144 MX6SLL_PAD_SD2_RESET = 125, 145 MX6SLL_PAD_SD2_CLK = 126, 146 MX6SLL_PAD_SD2_CMD = 127, 147 MX6SLL_PAD_SD2_DATA0 = 128, 148 MX6SLL_PAD_SD2_DATA1 = 129, 149 MX6SLL_PAD_SD2_DATA2 = 130, 150 MX6SLL_PAD_SD2_DATA3 = 131, 151 MX6SLL_PAD_SD2_DATA4 = 132, 152 MX6SLL_PAD_SD2_DATA5 = 133, 153 MX6SLL_PAD_SD2_DATA6 = 134, 154 MX6SLL_PAD_SD2_DATA7 = 135, 155 MX6SLL_PAD_SD3_CLK = 136, 156 MX6SLL_PAD_SD3_CMD = 137, 157 MX6SLL_PAD_SD3_DATA0 = 138, 158 MX6SLL_PAD_SD3_DATA1 = 139, 159 MX6SLL_PAD_SD3_DATA2 = 140, 160 MX6SLL_PAD_SD3_DATA3 = 141, 161 MX6SLL_PAD_GPIO4_IO20 = 142, 162 MX6SLL_PAD_GPIO4_IO21 = 143, 163 MX6SLL_PAD_GPIO4_IO19 = 144, 164 MX6SLL_PAD_GPIO4_IO25 = 145, 165 MX6SLL_PAD_GPIO4_IO18 = 146, 166 MX6SLL_PAD_GPIO4_IO24 = 147, 167 MX6SLL_PAD_GPIO4_IO23 = 148, 168 MX6SLL_PAD_GPIO4_IO17 = 149, 169 MX6SLL_PAD_GPIO4_IO22 = 150, 170 MX6SLL_PAD_GPIO4_IO16 = 151, 171 MX6SLL_PAD_GPIO4_IO26 = 152, 172 }; 173 174 /* Pad names for the pinmux subsystem */ 175 static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = { 176 IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0), 177 IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1), 178 IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2), 179 IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3), 180 IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4), 181 IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B), 182 IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M), 183 IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K), 184 IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1), 185 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0), 186 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0), 187 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1), 188 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1), 189 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2), 190 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2), 191 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3), 192 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3), 193 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4), 194 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4), 195 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5), 196 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5), 197 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6), 198 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6), 199 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7), 200 IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7), 201 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00), 202 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01), 203 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02), 204 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03), 205 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04), 206 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05), 207 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06), 208 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07), 209 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08), 210 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09), 211 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10), 212 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11), 213 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12), 214 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13), 215 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14), 216 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15), 217 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK), 218 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE), 219 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE), 220 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR), 221 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0), 222 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1), 223 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2), 224 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3), 225 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK), 226 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE), 227 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL), 228 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP), 229 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0), 230 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1), 231 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0), 232 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1), 233 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0), 234 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1), 235 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2), 236 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3), 237 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM), 238 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT), 239 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT), 240 IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE), 241 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK), 242 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE), 243 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC), 244 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC), 245 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET), 246 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00), 247 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01), 248 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02), 249 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03), 250 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04), 251 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05), 252 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06), 253 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07), 254 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08), 255 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09), 256 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10), 257 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11), 258 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12), 259 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13), 260 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14), 261 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15), 262 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16), 263 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17), 264 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18), 265 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19), 266 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20), 267 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21), 268 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22), 269 IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23), 270 IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS), 271 IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC), 272 IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD), 273 IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC), 274 IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS), 275 IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD), 276 IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK), 277 IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD), 278 IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD), 279 IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL), 280 IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA), 281 IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL), 282 IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA), 283 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK), 284 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI), 285 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO), 286 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0), 287 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK), 288 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI), 289 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO), 290 IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0), 291 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK), 292 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD), 293 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0), 294 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1), 295 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2), 296 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3), 297 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4), 298 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5), 299 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6), 300 IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7), 301 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET), 302 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK), 303 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD), 304 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0), 305 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1), 306 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2), 307 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3), 308 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4), 309 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5), 310 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6), 311 IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7), 312 IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK), 313 IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD), 314 IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0), 315 IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1), 316 IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2), 317 IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3), 318 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20), 319 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21), 320 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19), 321 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25), 322 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18), 323 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24), 324 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23), 325 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17), 326 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22), 327 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16), 328 IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26), 329 }; 330 331 static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = { 332 .pins = imx6sll_pinctrl_pads, 333 .npins = ARRAY_SIZE(imx6sll_pinctrl_pads), 334 .gpr_compatible = "fsl,imx6sll-iomuxc-gpr", 335 }; 336 337 static const struct of_device_id imx6sll_pinctrl_of_match[] = { 338 { .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, }, 339 { /* sentinel */ } 340 }; 341 342 static int imx6sll_pinctrl_probe(struct platform_device *pdev) 343 { 344 return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info); 345 } 346 347 static struct platform_driver imx6sll_pinctrl_driver = { 348 .driver = { 349 .name = "imx6sll-pinctrl", 350 .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match), 351 .suppress_bind_attrs = true, 352 }, 353 .probe = imx6sll_pinctrl_probe, 354 }; 355 356 static int __init imx6sll_pinctrl_init(void) 357 { 358 return platform_driver_register(&imx6sll_pinctrl_driver); 359 } 360 arch_initcall(imx6sll_pinctrl_init); 361