f6859558 | 13-Oct-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: baytrail: fsp: Use a function to update the Azalia config pointer
At present we directly pass the Azalia config pointer to the FSP UPD. This updates to use a function to do the stuff, like Bras
x86: baytrail: fsp: Use a function to update the Azalia config pointer
At present we directly pass the Azalia config pointer to the FSP UPD. This updates to use a function to do the stuff, like Braswell does.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
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f8f291b0 | 31-May-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer
At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros
x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer
At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
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e652e130 | 21-Apr-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: baytrail: Conditionally report S3 in the ACPI table
When U-Boot is built without ACPI S3 support, it should not report S3 in the ACPI table otherwise when kernel does STR it won't work.
Signed
x86: baytrail: Conditionally report S3 in the ACPI table
When U-Boot is built without ACPI S3 support, it should not report S3 in the ACPI table otherwise when kernel does STR it won't work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
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3ff11aaa | 17-Jun-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: baytrail: acpi: Hide internal UART per GNVS setting
If global NVS says internal UART is not enabled, hide it in the ASL code so that OS won't see it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.co
x86: baytrail: acpi: Hide internal UART per GNVS setting
If global NVS says internal UART is not enabled, hide it in the ASL code so that OS won't see it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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7bfe0da4 | 11-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: baytrail: Add GPIO ASL description
Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is
x86: baytrail: Add GPIO ASL description
Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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4ce022d3 | 11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: fsp: Move struct fspinit_rtbuf definition to chipset header
All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf as defined by the 1.0 spec, however there are FSPs that does not fol
x86: fsp: Move struct fspinit_rtbuf definition to chipset header
All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf as defined by the 1.0 spec, however there are FSPs that does not follow 1.0 spec (possible due to that FSP predates the 1.0 spec), and future FSP binary that is complaint to v1.1 spec defines an optional paltform-specific runtime data in the struct fspinit_rtbuf. Hence move the definition to chipset header.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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