1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <malloc.h> 27 #include <syscon.h> 28 #include <asm/acpi_s3.h> 29 #include <asm/control_regs.h> 30 #include <asm/coreboot_tables.h> 31 #include <asm/cpu.h> 32 #include <asm/lapic.h> 33 #include <asm/microcode.h> 34 #include <asm/mp.h> 35 #include <asm/mrccache.h> 36 #include <asm/msr.h> 37 #include <asm/mtrr.h> 38 #include <asm/post.h> 39 #include <asm/processor.h> 40 #include <asm/processor-flags.h> 41 #include <asm/interrupt.h> 42 #include <asm/tables.h> 43 #include <linux/compiler.h> 44 45 DECLARE_GLOBAL_DATA_PTR; 46 47 static const char *const x86_vendor_name[] = { 48 [X86_VENDOR_INTEL] = "Intel", 49 [X86_VENDOR_CYRIX] = "Cyrix", 50 [X86_VENDOR_AMD] = "AMD", 51 [X86_VENDOR_UMC] = "UMC", 52 [X86_VENDOR_NEXGEN] = "NexGen", 53 [X86_VENDOR_CENTAUR] = "Centaur", 54 [X86_VENDOR_RISE] = "Rise", 55 [X86_VENDOR_TRANSMETA] = "Transmeta", 56 [X86_VENDOR_NSC] = "NSC", 57 [X86_VENDOR_SIS] = "SiS", 58 }; 59 60 int __weak x86_cleanup_before_linux(void) 61 { 62 #ifdef CONFIG_BOOTSTAGE_STASH 63 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 64 CONFIG_BOOTSTAGE_STASH_SIZE); 65 #endif 66 67 return 0; 68 } 69 70 int x86_init_cache(void) 71 { 72 enable_caches(); 73 74 return 0; 75 } 76 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 77 78 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 79 { 80 printf("resetting ...\n"); 81 82 /* wait 50 ms */ 83 udelay(50000); 84 disable_interrupts(); 85 reset_cpu(0); 86 87 /*NOTREACHED*/ 88 return 0; 89 } 90 91 void flush_cache(unsigned long dummy1, unsigned long dummy2) 92 { 93 asm("wbinvd\n"); 94 } 95 96 __weak void reset_cpu(ulong addr) 97 { 98 /* Do a hard reset through the chipset's reset control register */ 99 outb(SYS_RST | RST_CPU, IO_PORT_RESET); 100 for (;;) 101 cpu_hlt(); 102 } 103 104 void x86_full_reset(void) 105 { 106 outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); 107 } 108 109 /* Define these functions to allow ehch-hcd to function */ 110 void flush_dcache_range(unsigned long start, unsigned long stop) 111 { 112 } 113 114 void invalidate_dcache_range(unsigned long start, unsigned long stop) 115 { 116 } 117 118 void dcache_enable(void) 119 { 120 enable_caches(); 121 } 122 123 void dcache_disable(void) 124 { 125 disable_caches(); 126 } 127 128 void icache_enable(void) 129 { 130 } 131 132 void icache_disable(void) 133 { 134 } 135 136 int icache_status(void) 137 { 138 return 1; 139 } 140 141 const char *cpu_vendor_name(int vendor) 142 { 143 const char *name; 144 name = "<invalid cpu vendor>"; 145 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 146 (x86_vendor_name[vendor] != 0)) 147 name = x86_vendor_name[vendor]; 148 149 return name; 150 } 151 152 char *cpu_get_name(char *name) 153 { 154 unsigned int *name_as_ints = (unsigned int *)name; 155 struct cpuid_result regs; 156 char *ptr; 157 int i; 158 159 /* This bit adds up to 48 bytes */ 160 for (i = 0; i < 3; i++) { 161 regs = cpuid(0x80000002 + i); 162 name_as_ints[i * 4 + 0] = regs.eax; 163 name_as_ints[i * 4 + 1] = regs.ebx; 164 name_as_ints[i * 4 + 2] = regs.ecx; 165 name_as_ints[i * 4 + 3] = regs.edx; 166 } 167 name[CPU_MAX_NAME_LEN - 1] = '\0'; 168 169 /* Skip leading spaces. */ 170 ptr = name; 171 while (*ptr == ' ') 172 ptr++; 173 174 return ptr; 175 } 176 177 int default_print_cpuinfo(void) 178 { 179 printf("CPU: %s, vendor %s, device %xh\n", 180 cpu_has_64bit() ? "x86_64" : "x86", 181 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 182 183 #ifdef CONFIG_HAVE_ACPI_RESUME 184 debug("ACPI previous sleep state: %s\n", 185 acpi_ss_string(gd->arch.prev_sleep_state)); 186 #endif 187 188 return 0; 189 } 190 191 void show_boot_progress(int val) 192 { 193 outb(val, POST_PORT); 194 } 195 196 #ifndef CONFIG_SYS_COREBOOT 197 /* 198 * Implement a weak default function for boards that optionally 199 * need to clean up the system before jumping to the kernel. 200 */ 201 __weak void board_final_cleanup(void) 202 { 203 } 204 205 int last_stage_init(void) 206 { 207 write_tables(); 208 209 board_final_cleanup(); 210 211 return 0; 212 } 213 #endif 214 215 static int x86_init_cpus(void) 216 { 217 #ifdef CONFIG_SMP 218 debug("Init additional CPUs\n"); 219 x86_mp_init(); 220 #else 221 struct udevice *dev; 222 223 /* 224 * This causes the cpu-x86 driver to be probed. 225 * We don't check return value here as we want to allow boards 226 * which have not been converted to use cpu uclass driver to boot. 227 */ 228 uclass_first_device(UCLASS_CPU, &dev); 229 #endif 230 231 return 0; 232 } 233 234 int cpu_init_r(void) 235 { 236 struct udevice *dev; 237 int ret; 238 239 if (!ll_boot_init()) 240 return 0; 241 242 ret = x86_init_cpus(); 243 if (ret) 244 return ret; 245 246 /* 247 * Set up the northbridge, PCH and LPC if available. Note that these 248 * may have had some limited pre-relocation init if they were probed 249 * before relocation, but this is post relocation. 250 */ 251 uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 252 uclass_first_device(UCLASS_PCH, &dev); 253 uclass_first_device(UCLASS_LPC, &dev); 254 255 /* Set up pin control if available */ 256 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); 257 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret); 258 259 return 0; 260 } 261 262 #ifndef CONFIG_EFI_STUB 263 int reserve_arch(void) 264 { 265 #ifdef CONFIG_ENABLE_MRC_CACHE 266 mrccache_reserve(); 267 #endif 268 269 #ifdef CONFIG_SEABIOS 270 high_table_reserve(); 271 #endif 272 273 return 0; 274 } 275 #endif 276