1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DDR_H__ 8 #define __DDR_H__ 9 struct board_specific_parameters { 10 u32 n_ranks; 11 u32 datarate_mhz_high; 12 u32 rank_gb; 13 u32 clk_adjust; 14 u32 wrlvl_start; 15 u32 wrlvl_ctl_2; 16 u32 wrlvl_ctl_3; 17 }; 18 19 /* 20 * These tables contain all valid speeds we want to override with board 21 * specific parameters. datarate_mhz_high values need to be in ascending order 22 * for each n_ranks group. 23 */ 24 25 static const struct board_specific_parameters udimm0[] = { 26 /* 27 * memory controller 0 28 * num| hi| rank| clk| wrlvl | wrlvl 29 * ranks| mhz| GB |adjst| start | ctl2 30 */ 31 #ifdef CONFIG_SYS_FSL_DDR4 32 {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a}, 33 #elif defined(CONFIG_SYS_FSL_DDR3) 34 {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, 35 {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, 36 {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, 37 {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, 38 {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, 39 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, 40 {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, 41 {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, 42 {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, 43 {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, 44 {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, 45 {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, 46 #else 47 #error DDR type not defined 48 #endif 49 {} 50 }; 51 52 #endif 53 54 static const struct board_specific_parameters *udimms[] = { 55 udimm0, 56 }; 57