1 /* 2 * Toradex Colibri PXA270 configuration file 3 * 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 5 * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Board Configuration Options 15 */ 16 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 17 #define CONFIG_SYS_TEXT_BASE 0x0 18 /* Avoid overwriting factory configuration block */ 19 #define CONFIG_BOARD_SIZE_LIMIT 0x40000 20 21 /* We will never enable dcache because we have to setup MMU first */ 22 #define CONFIG_SYS_DCACHE_OFF 23 24 /* 25 * Environment settings 26 */ 27 #define CONFIG_ENV_OVERWRITE 28 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) 29 #define CONFIG_ARCH_CPU_INIT 30 #define CONFIG_BOOTCOMMAND \ 31 "if fatload mmc 0 0xa0000000 uImage; then " \ 32 "bootm 0xa0000000; " \ 33 "fi; " \ 34 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ 35 "bootm 0xa0000000; " \ 36 "fi; " \ 37 "bootm 0xc0000;" 38 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" 39 #define CONFIG_TIMESTAMP 40 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 41 #define CONFIG_CMDLINE_TAG 42 #define CONFIG_SETUP_MEMORY_TAGS 43 #define CONFIG_LZMA /* LZMA compression support */ 44 #define CONFIG_OF_LIBFDT 45 46 /* 47 * Serial Console Configuration 48 */ 49 #define CONFIG_PXA_SERIAL 50 #define CONFIG_FFUART 1 51 #define CONFIG_CONS_INDEX 3 52 #define CONFIG_BAUDRATE 115200 53 54 /* 55 * Bootloader Components Configuration 56 */ 57 #define CONFIG_CMD_ENV 58 #define CONFIG_CMD_MMC 59 #define CONFIG_CMD_USB 60 61 /* I2C support */ 62 #ifdef CONFIG_SYS_I2C 63 #define CONFIG_CMD_I2C 64 #define CONFIG_SYS_I2C_PXA 65 #define CONFIG_PXA_STD_I2C 66 #define CONFIG_PXA_PWR_I2C 67 #define CONFIG_SYS_I2C_SPEED 100000 68 #endif 69 70 /* LCD support */ 71 #ifdef CONFIG_LCD 72 #define CONFIG_PXA_LCD 73 #define CONFIG_PXA_VGA 74 #define CONFIG_SYS_WHITE_ON_BLACK 75 #define CONFIG_CONSOLE_SCROLL_LINES 10 76 #define CONFIG_CMD_BMP 77 #define CONFIG_LCD_LOGO 78 #endif 79 80 /* 81 * Networking Configuration 82 */ 83 #ifdef CONFIG_CMD_NET 84 #define CONFIG_CMD_PING 85 #define CONFIG_CMD_DHCP 86 87 #define CONFIG_DRIVER_DM9000 1 88 #define CONFIG_DM9000_BASE 0x08000000 89 #define DM9000_IO (CONFIG_DM9000_BASE) 90 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 91 #define CONFIG_NET_RETRY_COUNT 10 92 93 #define CONFIG_BOOTP_BOOTFILESIZE 94 #define CONFIG_BOOTP_BOOTPATH 95 #define CONFIG_BOOTP_GATEWAY 96 #define CONFIG_BOOTP_HOSTNAME 97 #endif 98 99 /* 100 * HUSH Shell Configuration 101 */ 102 #define CONFIG_SYS_HUSH_PARSER 1 103 104 #undef CONFIG_SYS_LONGHELP /* Saves 10 KB */ 105 #undef CONFIG_SYS_PROMPT 106 #ifdef CONFIG_SYS_HUSH_PARSER 107 #define CONFIG_SYS_PROMPT "$ " 108 #else 109 #endif 110 #define CONFIG_SYS_CBSIZE 256 111 #define CONFIG_SYS_PBSIZE \ 112 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 113 #define CONFIG_SYS_MAXARGS 16 114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 115 #define CONFIG_SYS_DEVICE_NULLDEV 1 116 #define CONFIG_CMDLINE_EDITING 1 117 #define CONFIG_AUTO_COMPLETE 1 118 119 /* 120 * Clock Configuration 121 */ 122 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ 123 124 /* 125 * DRAM Map 126 */ 127 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 128 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 129 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 130 131 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 132 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ 133 134 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 135 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 136 137 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 138 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 139 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 140 141 /* 142 * NOR FLASH 143 */ 144 #ifdef CONFIG_CMD_FLASH 145 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 146 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 147 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 148 149 #define CONFIG_SYS_FLASH_CFI 150 #define CONFIG_FLASH_CFI_DRIVER 1 151 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 152 153 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 155 156 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) 157 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) 158 #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) 159 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) 160 161 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 162 #define CONFIG_SYS_FLASH_PROTECTION 1 163 164 #define CONFIG_ENV_IS_IN_FLASH 1 165 166 #else /* No flash */ 167 #define CONFIG_SYS_NO_FLASH 168 #define CONFIG_ENV_IS_NOWHERE 169 #endif 170 171 #define CONFIG_SYS_MONITOR_BASE 0x0 172 #define CONFIG_SYS_MONITOR_LEN 0x40000 173 174 /* Skip factory configuration block */ 175 #define CONFIG_ENV_ADDR \ 176 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) 177 #define CONFIG_ENV_SIZE 0x40000 178 #define CONFIG_ENV_SECT_SIZE 0x40000 179 180 /* 181 * GPIO settings 182 */ 183 #define CONFIG_SYS_GPSR0_VAL 0x00000000 184 #define CONFIG_SYS_GPSR1_VAL 0x00020000 185 #define CONFIG_SYS_GPSR2_VAL 0x0002c000 186 #define CONFIG_SYS_GPSR3_VAL 0x00000000 187 188 #define CONFIG_SYS_GPCR0_VAL 0x00000000 189 #define CONFIG_SYS_GPCR1_VAL 0x00000000 190 #define CONFIG_SYS_GPCR2_VAL 0x00000000 191 #define CONFIG_SYS_GPCR3_VAL 0x00000000 192 193 #define CONFIG_SYS_GPDR0_VAL 0xc8008000 194 #define CONFIG_SYS_GPDR1_VAL 0xfc02a981 195 #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff 196 #define CONFIG_SYS_GPDR3_VAL 0x0061e804 197 198 #define CONFIG_SYS_GAFR0_L_VAL 0x80100000 199 #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 200 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a 201 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 202 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 203 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 204 #define CONFIG_SYS_GAFR3_L_VAL 0x54000310 205 #define CONFIG_SYS_GAFR3_U_VAL 0x00005401 206 207 #define CONFIG_SYS_PSSR_VAL 0x30 208 209 /* 210 * Clock settings 211 */ 212 #define CONFIG_SYS_CKEN 0x00500240 213 #define CONFIG_SYS_CCCR 0x02000290 214 215 /* 216 * Memory settings 217 */ 218 #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 219 #define CONFIG_SYS_MSC1_VAL 0x9ee1f994 220 #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 221 #define CONFIG_SYS_MDCNFG_VAL 0x090009c9 222 #define CONFIG_SYS_MDREFR_VAL 0x2003a031 223 #define CONFIG_SYS_MDMRS_VAL 0x00220022 224 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 225 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 226 227 /* 228 * PCMCIA and CF Interfaces 229 */ 230 #define CONFIG_SYS_MECR_VAL 0x00000000 231 #define CONFIG_SYS_MCMEM0_VAL 0x00028307 232 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 233 #define CONFIG_SYS_MCATT0_VAL 0x00038787 234 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 235 #define CONFIG_SYS_MCIO0_VAL 0x0002830f 236 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 237 238 #include "pxa-common.h" 239 240 #endif /* __CONFIG_H */ 241