1 /*
2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/io.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <linux/sizes.h>
20 #include <common.h>
21 #include <fsl_esdhc.h>
22 #include <mmc.h>
23 #include <i2c.h>
24 #include <miiphy.h>
25 #include <netdev.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
28 #include "../common/pfuze.h"
29 #include <usb.h>
30 #include <usb/ehci-ci.h>
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
35 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
36 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
37 
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
39 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
40 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
41 
42 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
43 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
44 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
45 	PAD_CTL_ODE)
46 
47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
48 	PAD_CTL_SPEED_HIGH   |                                   \
49 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
50 
51 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
52 	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
53 
54 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
55 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
56 
57 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
58 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
59 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
60 	PAD_CTL_ODE)
61 
62 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
63 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
64 
65 int dram_init(void)
66 {
67 	gd->ram_size = imx_ddr_size();
68 
69 	return 0;
70 }
71 
72 static iomux_v3_cfg_t const uart1_pads[] = {
73 	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
74 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
75 };
76 
77 static iomux_v3_cfg_t const usdhc2_pads[] = {
78 	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 };
85 
86 static iomux_v3_cfg_t const usdhc3_pads[] = {
87 	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 	MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 	MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 	MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 	MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 
98 	/* CD pin */
99 	MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
100 
101 	/* RST_B, used for power reset cycle */
102 	MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
103 };
104 
105 static iomux_v3_cfg_t const usdhc4_pads[] = {
106 	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 	MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 };
114 
115 static iomux_v3_cfg_t const fec1_pads[] = {
116 	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
119 	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
120 	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
121 	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
122 	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
123 	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
124 	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
127 	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
128 	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
129 	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
130 };
131 
132 static iomux_v3_cfg_t const peri_3v3_pads[] = {
133 	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
134 };
135 
136 static iomux_v3_cfg_t const phy_control_pads[] = {
137 	/* 25MHz Ethernet PHY Clock */
138 	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
139 
140 	/* ENET PHY Power */
141 	MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
142 
143 	/* AR8031 PHY Reset */
144 	MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
145 };
146 
147 static void setup_iomux_uart(void)
148 {
149 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
150 }
151 
152 static int setup_fec(void)
153 {
154 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
155 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
156 	int reg, ret;
157 
158 	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
159 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
160 
161 	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
162 	if (ret)
163 		return ret;
164 
165 	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
166 					 ARRAY_SIZE(phy_control_pads));
167 
168 	/* Enable the ENET power, active low */
169 	gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
170 
171 	/* Reset AR8031 PHY */
172 	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
173 	mdelay(10);
174 	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
175 
176 	reg = readl(&anatop->pll_enet);
177 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
178 	writel(reg, &anatop->pll_enet);
179 
180 	return 0;
181 }
182 
183 int board_eth_init(bd_t *bis)
184 {
185 	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
186 	setup_fec();
187 
188 	return cpu_eth_init(bis);
189 }
190 
191 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
192 /* I2C1 for PMIC */
193 static struct i2c_pads_info i2c_pad_info1 = {
194 	.scl = {
195 		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
196 		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
197 		.gp = IMX_GPIO_NR(1, 0),
198 	},
199 	.sda = {
200 		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
201 		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
202 		.gp = IMX_GPIO_NR(1, 1),
203 	},
204 };
205 
206 int power_init_board(void)
207 {
208 	struct pmic *p;
209 	unsigned int reg;
210 	int ret;
211 
212 	p = pfuze_common_init(I2C_PMIC);
213 	if (!p)
214 		return -ENODEV;
215 
216 	ret = pfuze_mode_init(p, APS_PFM);
217 	if (ret < 0)
218 		return ret;
219 
220 	/* Enable power of VGEN5 3V3, needed for SD3 */
221 	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
222 	reg &= ~LDO_VOL_MASK;
223 	reg |= (LDOB_3_30V | (1 << LDO_EN));
224 	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
225 
226 	return 0;
227 }
228 
229 #ifdef CONFIG_USB_EHCI_MX6
230 #define USB_OTHERREGS_OFFSET	0x800
231 #define UCTRL_PWR_POL		(1 << 9)
232 
233 static iomux_v3_cfg_t const usb_otg_pads[] = {
234 	/* OGT1 */
235 	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
236 	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
237 	/* OTG2 */
238 	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
239 };
240 
241 static void setup_usb(void)
242 {
243 	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
244 					 ARRAY_SIZE(usb_otg_pads));
245 }
246 
247 int board_usb_phy_mode(int port)
248 {
249 	if (port == 1)
250 		return USB_INIT_HOST;
251 	else
252 		return usb_phy_mode(port);
253 }
254 
255 int board_ehci_hcd_init(int port)
256 {
257 	u32 *usbnc_usb_ctrl;
258 
259 	if (port > 1)
260 		return -EINVAL;
261 
262 	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
263 				 port * 4);
264 
265 	/* Set Power polarity */
266 	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
267 
268 	return 0;
269 }
270 #endif
271 
272 int board_phy_config(struct phy_device *phydev)
273 {
274 	/*
275 	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
276 	 * Phy control debug reg 0
277 	 */
278 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
279 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
280 
281 	/* rgmii tx clock delay enable */
282 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
283 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
284 
285 	if (phydev->drv->config)
286 		phydev->drv->config(phydev);
287 
288 	return 0;
289 }
290 
291 int board_early_init_f(void)
292 {
293 	setup_iomux_uart();
294 
295 	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
296 	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
297 					 ARRAY_SIZE(peri_3v3_pads));
298 
299 	/* Active high for ncp692 */
300 	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
301 
302 #ifdef CONFIG_USB_EHCI_MX6
303 	setup_usb();
304 #endif
305 
306 	return 0;
307 }
308 
309 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
310 	{USDHC2_BASE_ADDR, 0, 4},
311 	{USDHC3_BASE_ADDR},
312 	{USDHC4_BASE_ADDR},
313 };
314 
315 #define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 10)
316 #define USDHC3_PWR_GPIO	IMX_GPIO_NR(2, 11)
317 #define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 21)
318 
319 int board_mmc_get_env_dev(int devno)
320 {
321 	return devno - 1;
322 }
323 
324 int board_mmc_getcd(struct mmc *mmc)
325 {
326 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
327 	int ret = 0;
328 
329 	switch (cfg->esdhc_base) {
330 	case USDHC2_BASE_ADDR:
331 		ret = 1; /* Assume uSDHC2 is always present */
332 		break;
333 	case USDHC3_BASE_ADDR:
334 		ret = !gpio_get_value(USDHC3_CD_GPIO);
335 		break;
336 	case USDHC4_BASE_ADDR:
337 		ret = !gpio_get_value(USDHC4_CD_GPIO);
338 		break;
339 	}
340 
341 	return ret;
342 }
343 
344 int board_mmc_init(bd_t *bis)
345 {
346 #ifndef CONFIG_SPL_BUILD
347 	int i, ret;
348 
349 	/*
350 	 * According to the board_mmc_init() the following map is done:
351 	 * (U-Boot device node)    (Physical Port)
352 	 * mmc0                    USDHC2
353 	 * mmc1                    USDHC3
354 	 * mmc2                    USDHC4
355 	 */
356 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
357 		switch (i) {
358 		case 0:
359 			imx_iomux_v3_setup_multiple_pads(
360 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
361 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
362 			break;
363 		case 1:
364 			imx_iomux_v3_setup_multiple_pads(
365 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
366 			gpio_direction_input(USDHC3_CD_GPIO);
367 			gpio_direction_output(USDHC3_PWR_GPIO, 1);
368 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
369 			break;
370 		case 2:
371 			imx_iomux_v3_setup_multiple_pads(
372 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
373 			gpio_direction_input(USDHC4_CD_GPIO);
374 			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
375 			break;
376 		default:
377 			printf("Warning: you configured more USDHC controllers"
378 				"(%d) than supported by the board\n", i + 1);
379 			return -EINVAL;
380 			}
381 
382 			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
383 			if (ret) {
384 				printf("Warning: failed to initialize mmc dev %d\n", i);
385 				return ret;
386 			}
387 	}
388 
389 	return 0;
390 #else
391 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
392 	u32 val;
393 	u32 port;
394 
395 	val = readl(&src_regs->sbmr1);
396 
397 	if ((val & 0xc0) != 0x40) {
398 		printf("Not boot from USDHC!\n");
399 		return -EINVAL;
400 	}
401 
402 	port = (val >> 11) & 0x3;
403 	printf("port %d\n", port);
404 	switch (port) {
405 	case 1:
406 		imx_iomux_v3_setup_multiple_pads(
407 			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
408 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
409 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
410 		break;
411 	case 2:
412 		imx_iomux_v3_setup_multiple_pads(
413 			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
414 		gpio_direction_input(USDHC3_CD_GPIO);
415 		gpio_direction_output(USDHC3_PWR_GPIO, 1);
416 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
417 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
418 		break;
419 	case 3:
420 		imx_iomux_v3_setup_multiple_pads(
421 			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
422 		gpio_direction_input(USDHC4_CD_GPIO);
423 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
424 		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
425 		break;
426 	}
427 
428 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
429 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
430 #endif
431 }
432 
433 #ifdef CONFIG_FSL_QSPI
434 
435 #define QSPI_PAD_CTRL1	\
436 	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
437 	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
438 
439 static iomux_v3_cfg_t const quadspi_pads[] = {
440 	MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
441 	MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
442 	MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
443 	MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
444 	MX6_PAD_NAND_ALE__QSPI2_A_SS0_B		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
445 	MX6_PAD_NAND_CLE__QSPI2_A_SCLK		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
446 	MX6_PAD_NAND_DATA07__QSPI2_A_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
447 	MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
448 	MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
449 	MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
450 	MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
451 	MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
452 	MX6_PAD_NAND_DATA02__QSPI2_B_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
453 	MX6_PAD_NAND_DATA05__QSPI2_B_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
454 };
455 
456 int board_qspi_init(void)
457 {
458 	/* Set the iomux */
459 	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
460 					 ARRAY_SIZE(quadspi_pads));
461 
462 	/* Set the clock */
463 	enable_qspi_clk(1);
464 
465 	return 0;
466 }
467 #endif
468 
469 #ifdef CONFIG_VIDEO_MXS
470 static iomux_v3_cfg_t const lcd_pads[] = {
471 	MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
472 	MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
473 	MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
474 	MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
475 	MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
476 	MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
477 	MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
478 	MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
479 	MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
480 	MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
481 	MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
482 	MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
483 	MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
484 	MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
485 	MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
486 	MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
487 	MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
488 	MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
489 	MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
490 	MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
491 	MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
492 	MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
493 	MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
494 	MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
495 	MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
496 	MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
497 	MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
498 	MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
499 	MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
500 
501 	/* Use GPIO for Brightness adjustment, duty cycle = period */
502 	MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
503 };
504 
505 static int setup_lcd(void)
506 {
507 	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
508 
509 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
510 
511 	/* Reset the LCD */
512 	gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
513 	udelay(500);
514 	gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
515 
516 	/* Set Brightness to high */
517 	gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
518 
519 	return 0;
520 }
521 #endif
522 
523 int board_init(void)
524 {
525 	/* Address of boot parameters */
526 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
527 
528 #ifdef CONFIG_SYS_I2C_MXC
529 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
530 #endif
531 
532 #ifdef CONFIG_FSL_QSPI
533 	board_qspi_init();
534 #endif
535 
536 #ifdef CONFIG_VIDEO_MXS
537 	setup_lcd();
538 #endif
539 
540 	return 0;
541 }
542 
543 int checkboard(void)
544 {
545 	puts("Board: MX6SX SABRE SDB\n");
546 
547 	return 0;
548 }
549 
550 #ifdef CONFIG_SPL_BUILD
551 #include <libfdt.h>
552 #include <spl.h>
553 #include <asm/arch/mx6-ddr.h>
554 
555 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
556 	.dram_dqm0 = 0x00000028,
557 	.dram_dqm1 = 0x00000028,
558 	.dram_dqm2 = 0x00000028,
559 	.dram_dqm3 = 0x00000028,
560 	.dram_ras = 0x00000020,
561 	.dram_cas = 0x00000020,
562 	.dram_odt0 = 0x00000020,
563 	.dram_odt1 = 0x00000020,
564 	.dram_sdba2 = 0x00000000,
565 	.dram_sdcke0 = 0x00003000,
566 	.dram_sdcke1 = 0x00003000,
567 	.dram_sdclk_0 = 0x00000030,
568 	.dram_sdqs0 = 0x00000028,
569 	.dram_sdqs1 = 0x00000028,
570 	.dram_sdqs2 = 0x00000028,
571 	.dram_sdqs3 = 0x00000028,
572 	.dram_reset = 0x00000020,
573 };
574 
575 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
576 	.grp_addds = 0x00000020,
577 	.grp_ddrmode_ctl = 0x00020000,
578 	.grp_ddrpke = 0x00000000,
579 	.grp_ddrmode = 0x00020000,
580 	.grp_b0ds = 0x00000028,
581 	.grp_b1ds = 0x00000028,
582 	.grp_ctlds = 0x00000020,
583 	.grp_ddr_type = 0x000c0000,
584 	.grp_b2ds = 0x00000028,
585 	.grp_b3ds = 0x00000028,
586 };
587 
588 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
589 	.p0_mpwldectrl0 = 0x00290025,
590 	.p0_mpwldectrl1 = 0x00220022,
591 	.p0_mpdgctrl0 = 0x41480144,
592 	.p0_mpdgctrl1 = 0x01340130,
593 	.p0_mprddlctl = 0x3C3E4244,
594 	.p0_mpwrdlctl = 0x34363638,
595 };
596 
597 static struct mx6_ddr3_cfg mem_ddr = {
598 	.mem_speed = 1600,
599 	.density = 4,
600 	.width = 32,
601 	.banks = 8,
602 	.rowaddr = 15,
603 	.coladdr = 10,
604 	.pagesz = 2,
605 	.trcd = 1375,
606 	.trcmin = 4875,
607 	.trasmin = 3500,
608 };
609 
610 static void ccgr_init(void)
611 {
612 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
613 
614 	writel(0xFFFFFFFF, &ccm->CCGR0);
615 	writel(0xFFFFFFFF, &ccm->CCGR1);
616 	writel(0xFFFFFFFF, &ccm->CCGR2);
617 	writel(0xFFFFFFFF, &ccm->CCGR3);
618 	writel(0xFFFFFFFF, &ccm->CCGR4);
619 	writel(0xFFFFFFFF, &ccm->CCGR5);
620 	writel(0xFFFFFFFF, &ccm->CCGR6);
621 	writel(0xFFFFFFFF, &ccm->CCGR7);
622 }
623 
624 static void spl_dram_init(void)
625 {
626 	struct mx6_ddr_sysinfo sysinfo = {
627 		.dsize = mem_ddr.width/32,
628 		.cs_density = 24,
629 		.ncs = 1,
630 		.cs1_mirror = 0,
631 		.rtt_wr = 2,
632 		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
633 		.walat = 1,		/* Write additional latency */
634 		.ralat = 5,		/* Read additional latency */
635 		.mif3_mode = 3,		/* Command prediction working mode */
636 		.bi_on = 1,		/* Bank interleaving enabled */
637 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
638 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
639 		.ddr_type = DDR_TYPE_DDR3,
640 		.refsel = 1,	/* Refresh cycles at 32KHz */
641 		.refr = 7,	/* 8 refresh commands per refresh cycle */
642 	};
643 
644 	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
645 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
646 }
647 
648 void board_init_f(ulong dummy)
649 {
650 	/* setup AIPS and disable watchdog */
651 	arch_cpu_init();
652 
653 	ccgr_init();
654 
655 	/* iomux and setup of i2c */
656 	board_early_init_f();
657 
658 	/* setup GP timer */
659 	timer_init();
660 
661 	/* UART clocks enabled and gd valid - init serial console */
662 	preloader_console_init();
663 
664 	/* DDR initialization */
665 	spl_dram_init();
666 
667 	/* Clear the BSS. */
668 	memset(__bss_start, 0, __bss_end - __bss_start);
669 
670 	/* load/boot image from boot device */
671 	board_init_r(NULL, 0);
672 }
673 #endif
674