1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <asm/io.h> 10 #include <asm/mrccache.h> 11 #include <asm/mtrr.h> 12 #include <asm/pci.h> 13 #include <asm/post.h> 14 #include <asm/arch/device.h> 15 #include <asm/arch/msg_port.h> 16 #include <asm/arch/quark.h> 17 18 static struct pci_device_id mmc_supported[] = { 19 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 20 {}, 21 }; 22 23 static void quark_setup_mtrr(void) 24 { 25 u32 base, mask; 26 int i; 27 28 disable_caches(); 29 30 /* mark the VGA RAM area as uncacheable */ 31 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000, 32 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 33 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000, 34 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 35 36 /* mark other fixed range areas as cacheable */ 37 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000, 38 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 39 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000, 40 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 41 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000, 42 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 43 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000, 44 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 45 for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++) 46 msg_port_write(MSG_PORT_HOST_BRIDGE, i, 47 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 48 49 /* variable range MTRR#0: ROM area */ 50 mask = ~(CONFIG_SYS_MONITOR_LEN - 1); 51 base = CONFIG_SYS_TEXT_BASE & mask; 52 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), 53 base | MTRR_TYPE_WRBACK); 54 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM), 55 mask | MTRR_PHYS_MASK_VALID); 56 57 /* variable range MTRR#1: eSRAM area */ 58 mask = ~(ESRAM_SIZE - 1); 59 base = CONFIG_ESRAM_BASE & mask; 60 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), 61 base | MTRR_TYPE_WRBACK); 62 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM), 63 mask | MTRR_PHYS_MASK_VALID); 64 65 /* enable both variable and fixed range MTRRs */ 66 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE, 67 MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN); 68 69 enable_caches(); 70 } 71 72 static void quark_setup_bars(void) 73 { 74 /* GPIO - D31:F0:R44h */ 75 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 76 CONFIG_GPIO_BASE | IO_BAR_EN); 77 78 /* ACPI PM1 Block - D31:F0:R48h */ 79 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 80 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 81 82 /* GPE0 - D31:F0:R4Ch */ 83 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 84 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 85 86 /* WDT - D31:F0:R84h */ 87 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 88 CONFIG_WDT_BASE | IO_BAR_EN); 89 90 /* RCBA - D31:F0:RF0h */ 91 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 92 CONFIG_RCBA_BASE | MEM_BAR_EN); 93 94 /* ACPI P Block - Msg Port 04:R70h */ 95 msg_port_write(MSG_PORT_RMU, PBLK_BA, 96 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 97 98 /* SPI DMA - Msg Port 04:R7Ah */ 99 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 100 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 101 102 /* PCIe ECAM */ 103 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 104 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 105 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 106 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 107 } 108 109 static void quark_pcie_early_init(void) 110 { 111 /* 112 * Step1: Assert PCIe signal PERST# 113 * 114 * The CPU interface to the PERST# signal is platform dependent. 115 * Call the board-specific codes to perform this task. 116 */ 117 board_assert_perst(); 118 119 /* Step2: PHY common lane reset */ 120 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST); 121 /* wait 1 ms for PHY common lane reset */ 122 mdelay(1); 123 124 /* Step3: PHY sideband interface reset and controller main reset */ 125 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, 126 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 127 /* wait 80ms for PLL to lock */ 128 mdelay(80); 129 130 /* Step4: Controller sideband interface reset */ 131 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST); 132 /* wait 20ms for controller sideband interface reset */ 133 mdelay(20); 134 135 /* Step5: De-assert PERST# */ 136 board_deassert_perst(); 137 138 /* Step6: Controller primary interface reset */ 139 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST); 140 141 /* Mixer Load Lane 0 */ 142 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, 143 (1 << 6) | (1 << 7)); 144 145 /* Mixer Load Lane 1 */ 146 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, 147 (1 << 6) | (1 << 7)); 148 } 149 150 static void quark_usb_early_init(void) 151 { 152 /* The sequence below comes from Quark firmware writer guide */ 153 154 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, 155 1 << 1, (1 << 6) | (1 << 7)); 156 157 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG, 158 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10)); 159 160 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 161 162 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1); 163 164 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1, 165 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6); 166 167 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 168 169 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24); 170 } 171 172 static void quark_thermal_early_init(void) 173 { 174 /* The sequence below comes from Quark firmware writer guide */ 175 176 /* thermal sensor mode config */ 177 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 178 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5); 179 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 180 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | 181 (1 << 12), 1 << 9); 182 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14); 183 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17); 184 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18); 185 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f); 186 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17); 187 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 188 (1 << 8) | (1 << 9), 1 << 8); 189 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000); 190 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4, 191 0x7ff800, 0xc8 << 11); 192 193 /* thermal monitor catastrophic trip set point (105 celsius) */ 194 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155); 195 196 /* thermal monitor catastrophic trip clear point (0 celsius) */ 197 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16); 198 199 /* take thermal sensor out of reset */ 200 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0); 201 202 /* enable thermal monitor */ 203 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15); 204 205 /* lock all thermal configuration */ 206 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6)); 207 } 208 209 static void quark_enable_legacy_seg(void) 210 { 211 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2, 212 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 213 } 214 215 int arch_cpu_init(void) 216 { 217 int ret; 218 219 post_code(POST_CPU_INIT); 220 221 ret = x86_cpu_init_f(); 222 if (ret) 223 return ret; 224 225 /* 226 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs 227 * are accessed indirectly via the message port and not the traditional 228 * MSR mechanism. Only UC, WT and WB cache types are supported. 229 */ 230 quark_setup_mtrr(); 231 232 /* 233 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 234 * which need be initialized with suggested values 235 */ 236 quark_setup_bars(); 237 238 /* Initialize USB2 PHY */ 239 quark_usb_early_init(); 240 241 /* Initialize thermal sensor */ 242 quark_thermal_early_init(); 243 244 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 245 quark_enable_legacy_seg(); 246 247 return 0; 248 } 249 250 int arch_cpu_init_dm(void) 251 { 252 /* 253 * Initialize PCIe controller 254 * 255 * Quark SoC holds the PCIe controller in reset following a power on. 256 * U-Boot needs to release the PCIe controller from reset. The PCIe 257 * controller (D23:F0/F1) will not be visible in PCI configuration 258 * space and any access to its PCI configuration registers will cause 259 * system hang while it is held in reset. 260 */ 261 quark_pcie_early_init(); 262 263 return 0; 264 } 265 266 int print_cpuinfo(void) 267 { 268 post_code(POST_CPU_INFO); 269 return default_print_cpuinfo(); 270 } 271 272 void reset_cpu(ulong addr) 273 { 274 /* cold reset */ 275 x86_full_reset(); 276 } 277 278 static void quark_pcie_init(void) 279 { 280 u32 val; 281 282 /* PCIe upstream non-posted & posted request size */ 283 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, 284 CCFG_UPRS | CCFG_UNRS); 285 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, 286 CCFG_UPRS | CCFG_UNRS); 287 288 /* PCIe packet fast transmit mode (IPF) */ 289 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); 290 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); 291 292 /* PCIe message bus idle counter (SBIC) */ 293 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); 294 val |= MBC_SBIC; 295 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); 296 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); 297 val |= MBC_SBIC; 298 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); 299 } 300 301 static void quark_usb_init(void) 302 { 303 u32 bar; 304 305 /* Change USB EHCI packet buffer OUT/IN threshold */ 306 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); 307 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); 308 309 /* Disable USB device interrupts */ 310 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); 311 writel(0x7f, bar + USBD_INT_MASK); 312 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); 313 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); 314 } 315 316 int arch_early_init_r(void) 317 { 318 quark_pcie_init(); 319 320 quark_usb_init(); 321 322 return 0; 323 } 324 325 int cpu_mmc_init(bd_t *bis) 326 { 327 return pci_mmc_init("Quark SDHCI", mmc_supported); 328 } 329 330 int arch_misc_init(void) 331 { 332 #ifdef CONFIG_ENABLE_MRC_CACHE 333 /* 334 * We intend not to check any return value here, as even MRC cache 335 * is not saved successfully, it is not a severe error that will 336 * prevent system from continuing to boot. 337 */ 338 mrccache_save(); 339 #endif 340 341 return 0; 342 } 343 344 void board_final_cleanup(void) 345 { 346 struct quark_rcba *rcba; 347 u32 base, val; 348 349 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 350 base &= ~MEM_BAR_EN; 351 rcba = (struct quark_rcba *)base; 352 353 /* Initialize 'Component ID' to zero */ 354 val = readl(&rcba->esd); 355 val &= ~0xff0000; 356 writel(val, &rcba->esd); 357 358 /* Lock HMBOUND for security */ 359 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK); 360 361 return; 362 } 363