1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> 4 * Copyright (C) 2014-2016, Toradex AG 5 * copied from nitrogen6x 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/iomux.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/arch/mx6-ddr.h> 17 #include <asm/arch/mxc_hdmi.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/bootm.h> 20 #include <asm/gpio.h> 21 #include <asm/imx-common/iomux-v3.h> 22 #include <asm/imx-common/mxc_i2c.h> 23 #include <asm/imx-common/sata.h> 24 #include <asm/imx-common/boot_mode.h> 25 #include <asm/imx-common/video.h> 26 #include <asm/io.h> 27 #include <dm/platform_data/serial_mxc.h> 28 #include <dm/platdata.h> 29 #include <fsl_esdhc.h> 30 #include <i2c.h> 31 #include <imx_thermal.h> 32 #include <linux/errno.h> 33 #include <malloc.h> 34 #include <micrel.h> 35 #include <miiphy.h> 36 #include <mmc.h> 37 #include <netdev.h> 38 39 #include "../common/tdx-cfg-block.h" 40 #ifdef CONFIG_TDX_CMD_IMX_MFGR 41 #include "pf0100.h" 42 #endif 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 48 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 49 50 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 51 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 52 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 53 54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 56 57 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 58 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 59 60 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 62 63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 65 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 66 67 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ 68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 69 PAD_CTL_SRE_SLOW) 70 71 #define NO_PULLUP ( \ 72 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 73 PAD_CTL_SRE_SLOW) 74 75 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 76 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 77 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 78 79 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 80 81 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) 82 83 int dram_init(void) 84 { 85 /* use the DDR controllers configured size */ 86 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 87 (ulong)imx_ddr_size()); 88 89 return 0; 90 } 91 92 /* Colibri UARTA */ 93 iomux_v3_cfg_t const uart1_pads[] = { 94 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 95 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 96 }; 97 98 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 99 /* Colibri I2C */ 100 struct i2c_pads_info i2c_pad_info1 = { 101 .scl = { 102 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, 103 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, 104 .gp = IMX_GPIO_NR(1, 3) 105 }, 106 .sda = { 107 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, 108 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, 109 .gp = IMX_GPIO_NR(1, 6) 110 } 111 }; 112 113 /* Colibri local, PMIC, SGTL5000, STMPE811 */ 114 struct i2c_pads_info i2c_pad_info_loc = { 115 .scl = { 116 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 117 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 118 .gp = IMX_GPIO_NR(2, 30) 119 }, 120 .sda = { 121 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 122 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 123 .gp = IMX_GPIO_NR(3, 16) 124 } 125 }; 126 127 /* Apalis MMC */ 128 iomux_v3_cfg_t const usdhc1_pads[] = { 129 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 136 # define GPIO_MMC_CD IMX_GPIO_NR(2, 5) 137 }; 138 139 /* eMMC */ 140 iomux_v3_cfg_t const usdhc3_pads[] = { 141 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 147 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 148 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 149 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 }; 153 154 iomux_v3_cfg_t const enet_pads[] = { 155 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 156 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 157 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 158 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 159 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 160 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 161 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 162 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 163 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 164 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 165 }; 166 167 static void setup_iomux_enet(void) 168 { 169 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 170 } 171 172 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */ 173 iomux_v3_cfg_t const gpio_pads[] = { 174 /* ADDRESS[17:18] [25] used as GPIO */ 175 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), 176 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), 177 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), 178 /* ADDRESS[19:24] used as GPIO */ 179 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), 180 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), 181 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), 182 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), 183 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), 184 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), 185 /* DATA[16:29] [31] used as GPIO */ 186 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), 187 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), 188 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), 189 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), 190 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), 191 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), 192 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), 193 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), 194 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), 195 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), 196 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), 197 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), 198 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), 199 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), 200 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), 201 /* DQM[0:3] used as GPIO */ 202 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP), 203 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP), 204 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), 205 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), 206 /* RDY used as GPIO */ 207 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), 208 /* ADDRESS[16] DATA[30] used as GPIO */ 209 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN), 210 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), 211 /* CSI pins used as GPIO */ 212 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), 213 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), 214 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), 215 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), 216 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), 217 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN), 218 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), 219 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), 220 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), 221 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), 222 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), 223 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), 224 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), 225 /* GPIO */ 226 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP), 227 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), 228 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), 229 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), 230 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), 231 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), 232 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), 233 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), 234 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), 235 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), 236 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), 237 /* USBH_OC */ 238 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), 239 /* USBC_ID */ 240 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), 241 /* USBC_DET */ 242 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), 243 }; 244 245 static void setup_iomux_gpio(void) 246 { 247 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); 248 } 249 250 iomux_v3_cfg_t const usb_pads[] = { 251 /* USB_PE */ 252 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), 253 # define GPIO_USBH_EN IMX_GPIO_NR(3, 31) 254 }; 255 256 /* 257 * UARTs are used in DTE mode, switch the mode on all UARTs before 258 * any pinmuxing connects a (DCE) output to a transceiver output. 259 */ 260 #define UFCR 0x90 /* FIFO Control Register */ 261 #define UFCR_DCEDTE (1<<6) /* DCE=0 */ 262 263 static void setup_dtemode_uart(void) 264 { 265 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); 266 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); 267 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE); 268 } 269 270 static void setup_iomux_uart(void) 271 { 272 setup_dtemode_uart(); 273 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 274 } 275 276 #ifdef CONFIG_USB_EHCI_MX6 277 int board_ehci_hcd_init(int port) 278 { 279 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 280 return 0; 281 } 282 283 int board_ehci_power(int port, int on) 284 { 285 switch (port) { 286 case 0: 287 /* control OTG power */ 288 /* No special PE for USBC, always on when ID pin signals 289 host mode */ 290 break; 291 case 1: 292 /* Control MXM USBH */ 293 /* Set MXM USBH power enable, '0' means on */ 294 gpio_direction_output(GPIO_USBH_EN, !on); 295 mdelay(100); 296 break; 297 default: 298 break; 299 } 300 return 0; 301 } 302 #endif 303 304 #ifdef CONFIG_FSL_ESDHC 305 /* use the following sequence: eMMC, MMC */ 306 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { 307 {USDHC3_BASE_ADDR}, 308 {USDHC1_BASE_ADDR}, 309 }; 310 311 int board_mmc_getcd(struct mmc *mmc) 312 { 313 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 314 int ret = true; /* default: assume inserted */ 315 316 switch (cfg->esdhc_base) { 317 case USDHC1_BASE_ADDR: 318 gpio_direction_input(GPIO_MMC_CD); 319 ret = !gpio_get_value(GPIO_MMC_CD); 320 break; 321 } 322 323 return ret; 324 } 325 326 int board_mmc_init(bd_t *bis) 327 { 328 #ifndef CONFIG_SPL_BUILD 329 s32 status = 0; 330 u32 index = 0; 331 332 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 333 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 334 335 usdhc_cfg[0].max_bus_width = 8; 336 usdhc_cfg[1].max_bus_width = 4; 337 338 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 339 switch (index) { 340 case 0: 341 imx_iomux_v3_setup_multiple_pads( 342 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 343 break; 344 case 1: 345 imx_iomux_v3_setup_multiple_pads( 346 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 347 break; 348 default: 349 printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", 350 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 351 return status; 352 } 353 354 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 355 } 356 357 return status; 358 #else 359 struct src *psrc = (struct src *)SRC_BASE_ADDR; 360 unsigned reg = readl(&psrc->sbmr1) >> 11; 361 /* 362 * Upon reading BOOT_CFG register the following map is done: 363 * Bit 11 and 12 of BOOT_CFG register can determine the current 364 * mmc port 365 * 0x1 SD1 366 * 0x2 SD2 367 * 0x3 SD4 368 */ 369 370 switch (reg & 0x3) { 371 case 0x0: 372 imx_iomux_v3_setup_multiple_pads( 373 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 374 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; 375 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 376 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 377 break; 378 case 0x2: 379 imx_iomux_v3_setup_multiple_pads( 380 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 381 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 382 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 383 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 384 break; 385 default: 386 puts("MMC boot device not available"); 387 } 388 389 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 390 #endif 391 } 392 #endif 393 394 int board_phy_config(struct phy_device *phydev) 395 { 396 if (phydev->drv->config) 397 phydev->drv->config(phydev); 398 399 return 0; 400 } 401 402 int board_eth_init(bd_t *bis) 403 { 404 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 405 uint32_t base = IMX_FEC_BASE; 406 struct mii_dev *bus = NULL; 407 struct phy_device *phydev = NULL; 408 int ret; 409 410 /* provide the PHY clock from the i.MX 6 */ 411 ret = enable_fec_anatop_clock(0, ENET_50MHZ); 412 if (ret) 413 return ret; 414 /* set gpr1[ENET_CLK_SEL] */ 415 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); 416 417 setup_iomux_enet(); 418 419 #ifdef CONFIG_FEC_MXC 420 bus = fec_get_miibus(base, -1); 421 if (!bus) 422 return 0; 423 /* scan PHY 1..7 */ 424 phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); 425 if (!phydev) { 426 free(bus); 427 puts("no PHY found\n"); 428 return 0; 429 } 430 phy_reset(phydev); 431 printf("using PHY at %d\n", phydev->addr); 432 ret = fec_probe(bis, -1, base, bus, phydev); 433 if (ret) { 434 printf("FEC MXC: %s:failed\n", __func__); 435 free(phydev); 436 free(bus); 437 } 438 #endif 439 return 0; 440 } 441 442 static iomux_v3_cfg_t const pwr_intb_pads[] = { 443 /* 444 * the bootrom sets the iomux to vselect, potentially connecting 445 * two outputs. Set this back to GPIO 446 */ 447 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) 448 }; 449 450 #if defined(CONFIG_VIDEO_IPUV3) 451 452 static iomux_v3_cfg_t const backlight_pads[] = { 453 /* Backlight On */ 454 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), 455 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26) 456 /* Backlight PWM, used as GPIO in U-Boot */ 457 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP), 458 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 459 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9) 460 }; 461 462 static iomux_v3_cfg_t const rgb_pads[] = { 463 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB), 464 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB), 465 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB), 466 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB), 467 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB), 468 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB), 469 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB), 470 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB), 471 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB), 472 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB), 473 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB), 474 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB), 475 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB), 476 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB), 477 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB), 478 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB), 479 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB), 480 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB), 481 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB), 482 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB), 483 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB), 484 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB), 485 }; 486 487 static void do_enable_hdmi(struct display_info_t const *dev) 488 { 489 imx_enable_hdmi_phy(); 490 } 491 492 static void enable_rgb(struct display_info_t const *dev) 493 { 494 imx_iomux_v3_setup_multiple_pads( 495 rgb_pads, 496 ARRAY_SIZE(rgb_pads)); 497 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 498 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); 499 } 500 501 static int detect_default(struct display_info_t const *dev) 502 { 503 (void) dev; 504 return 1; 505 } 506 507 struct display_info_t const displays[] = {{ 508 .bus = -1, 509 .addr = 0, 510 .pixfmt = IPU_PIX_FMT_RGB24, 511 .detect = detect_hdmi, 512 .enable = do_enable_hdmi, 513 .mode = { 514 .name = "HDMI", 515 .refresh = 60, 516 .xres = 1024, 517 .yres = 768, 518 .pixclock = 15385, 519 .left_margin = 220, 520 .right_margin = 40, 521 .upper_margin = 21, 522 .lower_margin = 7, 523 .hsync_len = 60, 524 .vsync_len = 10, 525 .sync = FB_SYNC_EXT, 526 .vmode = FB_VMODE_NONINTERLACED 527 } }, { 528 .bus = -1, 529 .addr = 0, 530 .pixfmt = IPU_PIX_FMT_RGB666, 531 .detect = detect_default, 532 .enable = enable_rgb, 533 .mode = { 534 .name = "vga-rgb", 535 .refresh = 60, 536 .xres = 640, 537 .yres = 480, 538 .pixclock = 33000, 539 .left_margin = 48, 540 .right_margin = 16, 541 .upper_margin = 31, 542 .lower_margin = 11, 543 .hsync_len = 96, 544 .vsync_len = 2, 545 .sync = 0, 546 .vmode = FB_VMODE_NONINTERLACED 547 } }, { 548 .bus = -1, 549 .addr = 0, 550 .pixfmt = IPU_PIX_FMT_RGB666, 551 .enable = enable_rgb, 552 .mode = { 553 .name = "wvga-rgb", 554 .refresh = 60, 555 .xres = 800, 556 .yres = 480, 557 .pixclock = 25000, 558 .left_margin = 40, 559 .right_margin = 88, 560 .upper_margin = 33, 561 .lower_margin = 10, 562 .hsync_len = 128, 563 .vsync_len = 2, 564 .sync = 0, 565 .vmode = FB_VMODE_NONINTERLACED 566 } } }; 567 size_t display_count = ARRAY_SIZE(displays); 568 569 static void setup_display(void) 570 { 571 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 572 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 573 int reg; 574 575 enable_ipu_clock(); 576 imx_setup_hdmi(); 577 /* Turn on LDB0,IPU,IPU DI0 clocks */ 578 reg = __raw_readl(&mxc_ccm->CCGR3); 579 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 580 writel(reg, &mxc_ccm->CCGR3); 581 582 /* set LDB0, LDB1 clk select to 011/011 */ 583 reg = readl(&mxc_ccm->cs2cdr); 584 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 585 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 586 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 587 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 588 writel(reg, &mxc_ccm->cs2cdr); 589 590 reg = readl(&mxc_ccm->cscmr2); 591 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 592 writel(reg, &mxc_ccm->cscmr2); 593 594 reg = readl(&mxc_ccm->chsccdr); 595 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 596 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 597 writel(reg, &mxc_ccm->chsccdr); 598 599 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 600 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 601 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 602 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 603 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 604 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 605 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 606 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 607 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 608 writel(reg, &iomux->gpr[2]); 609 610 reg = readl(&iomux->gpr[3]); 611 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK 612 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 613 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 614 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 615 writel(reg, &iomux->gpr[3]); 616 617 /* backlight unconditionally on for now */ 618 imx_iomux_v3_setup_multiple_pads(backlight_pads, 619 ARRAY_SIZE(backlight_pads)); 620 /* use 0 for EDT 7", use 1 for LG fullHD panel */ 621 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); 622 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 623 } 624 #endif /* defined(CONFIG_VIDEO_IPUV3) */ 625 626 int board_early_init_f(void) 627 { 628 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads, 629 ARRAY_SIZE(pwr_intb_pads)); 630 setup_iomux_uart(); 631 632 #if defined(CONFIG_VIDEO_IPUV3) 633 setup_display(); 634 #endif 635 return 0; 636 } 637 638 /* 639 * Do not overwrite the console 640 * Use always serial for U-Boot console 641 */ 642 int overwrite_console(void) 643 { 644 return 1; 645 } 646 647 int board_init(void) 648 { 649 /* address of boot parameters */ 650 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 651 652 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 653 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); 654 655 #ifdef CONFIG_TDX_CMD_IMX_MFGR 656 (void) pmic_init(); 657 #endif 658 659 #ifdef CONFIG_CMD_SATA 660 setup_sata(); 661 #endif 662 663 setup_iomux_gpio(); 664 665 return 0; 666 } 667 668 #ifdef CONFIG_BOARD_LATE_INIT 669 int board_late_init(void) 670 { 671 #if defined(CONFIG_REVISION_TAG) && \ 672 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) 673 char env_str[256]; 674 u32 rev; 675 676 rev = get_board_rev(); 677 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); 678 setenv("board_rev", env_str); 679 #endif 680 681 return 0; 682 } 683 #endif /* CONFIG_BOARD_LATE_INIT */ 684 685 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) 686 int ft_system_setup(void *blob, bd_t *bd) 687 { 688 return 0; 689 } 690 #endif 691 692 int checkboard(void) 693 { 694 char it[] = " IT"; 695 int minc, maxc; 696 697 switch (get_cpu_temp_grade(&minc, &maxc)) { 698 case TEMP_AUTOMOTIVE: 699 case TEMP_INDUSTRIAL: 700 break; 701 case TEMP_EXTCOMMERCIAL: 702 default: 703 it[0] = 0; 704 }; 705 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n", 706 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo", 707 (gd->ram_size == 0x20000000) ? "512" : "256", it); 708 return 0; 709 } 710 711 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 712 int ft_board_setup(void *blob, bd_t *bd) 713 { 714 return ft_common_board_setup(blob, bd); 715 } 716 #endif 717 718 #ifdef CONFIG_CMD_BMODE 719 static const struct boot_mode board_boot_modes[] = { 720 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 721 {NULL, 0}, 722 }; 723 #endif 724 725 int misc_init_r(void) 726 { 727 #ifdef CONFIG_CMD_BMODE 728 add_board_boot_modes(board_boot_modes); 729 #endif 730 return 0; 731 } 732 733 #ifdef CONFIG_LDO_BYPASS_CHECK 734 /* TODO, use external pmic, for now always ldo_enable */ 735 void ldo_mode_set(int ldo_bypass) 736 { 737 return; 738 } 739 #endif 740 741 #ifdef CONFIG_SPL_BUILD 742 #include <spl.h> 743 #include <libfdt.h> 744 #include "asm/arch/mx6dl-ddr.h" 745 #include "asm/arch/iomux.h" 746 #include "asm/arch/crm_regs.h" 747 748 static int mx6s_dcd_table[] = { 749 /* ddr-setup.cfg */ 750 751 MX6_IOM_DRAM_SDQS0, 0x00000030, 752 MX6_IOM_DRAM_SDQS1, 0x00000030, 753 MX6_IOM_DRAM_SDQS2, 0x00000030, 754 MX6_IOM_DRAM_SDQS3, 0x00000030, 755 MX6_IOM_DRAM_SDQS4, 0x00000030, 756 MX6_IOM_DRAM_SDQS5, 0x00000030, 757 MX6_IOM_DRAM_SDQS6, 0x00000030, 758 MX6_IOM_DRAM_SDQS7, 0x00000030, 759 760 MX6_IOM_GRP_B0DS, 0x00000030, 761 MX6_IOM_GRP_B1DS, 0x00000030, 762 MX6_IOM_GRP_B2DS, 0x00000030, 763 MX6_IOM_GRP_B3DS, 0x00000030, 764 MX6_IOM_GRP_B4DS, 0x00000030, 765 MX6_IOM_GRP_B5DS, 0x00000030, 766 MX6_IOM_GRP_B6DS, 0x00000030, 767 MX6_IOM_GRP_B7DS, 0x00000030, 768 MX6_IOM_GRP_ADDDS, 0x00000030, 769 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 770 MX6_IOM_GRP_CTLDS, 0x00000030, 771 772 MX6_IOM_DRAM_DQM0, 0x00020030, 773 MX6_IOM_DRAM_DQM1, 0x00020030, 774 MX6_IOM_DRAM_DQM2, 0x00020030, 775 MX6_IOM_DRAM_DQM3, 0x00020030, 776 MX6_IOM_DRAM_DQM4, 0x00020030, 777 MX6_IOM_DRAM_DQM5, 0x00020030, 778 MX6_IOM_DRAM_DQM6, 0x00020030, 779 MX6_IOM_DRAM_DQM7, 0x00020030, 780 781 MX6_IOM_DRAM_CAS, 0x00020030, 782 MX6_IOM_DRAM_RAS, 0x00020030, 783 MX6_IOM_DRAM_SDCLK_0, 0x00020030, 784 MX6_IOM_DRAM_SDCLK_1, 0x00020030, 785 786 MX6_IOM_DRAM_RESET, 0x00020030, 787 MX6_IOM_DRAM_SDCKE0, 0x00003000, 788 MX6_IOM_DRAM_SDCKE1, 0x00003000, 789 790 MX6_IOM_DRAM_SDODT0, 0x00003030, 791 MX6_IOM_DRAM_SDODT1, 0x00003030, 792 793 /* (differential input) */ 794 MX6_IOM_DDRMODE_CTL, 0x00020000, 795 /* (differential input) */ 796 MX6_IOM_GRP_DDRMODE, 0x00020000, 797 /* disable ddr pullups */ 798 MX6_IOM_GRP_DDRPKE, 0x00000000, 799 MX6_IOM_DRAM_SDBA2, 0x00000000, 800 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 801 MX6_IOM_GRP_DDR_TYPE, 0x000C0000, 802 803 /* Read data DQ Byte0-3 delay */ 804 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, 805 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, 806 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, 807 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, 808 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, 809 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, 810 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, 811 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, 812 813 /* 814 * MDMISC mirroring interleaved (row/bank/col) 815 */ 816 /* TODO: check what the RALAT field does */ 817 MX6_MMDC_P0_MDMISC, 0x00081740, 818 819 /* 820 * MDSCR con_req 821 */ 822 MX6_MMDC_P0_MDSCR, 0x00008000, 823 824 825 /* 800mhz_2x64mx16.cfg */ 826 827 MX6_MMDC_P0_MDPDC, 0x0002002D, 828 MX6_MMDC_P0_MDCFG0, 0x2C305503, 829 MX6_MMDC_P0_MDCFG1, 0xB66D8D63, 830 MX6_MMDC_P0_MDCFG2, 0x01FF00DB, 831 MX6_MMDC_P0_MDRWD, 0x000026D2, 832 MX6_MMDC_P0_MDOR, 0x00301023, 833 MX6_MMDC_P0_MDOTC, 0x00333030, 834 MX6_MMDC_P0_MDPDC, 0x0002556D, 835 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */ 836 MX6_MMDC_P0_MDASP, 0x00000017, 837 /* DDR3 DATA BUS SIZE: 64BIT */ 838 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */ 839 /* DDR3 DATA BUS SIZE: 32BIT */ 840 MX6_MMDC_P0_MDCTL, 0x82190000, 841 842 /* Write commands to DDR */ 843 /* Load Mode Registers */ 844 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ 845 /* MX6_MMDC_P0_MDSCR, 0x04408032, */ 846 MX6_MMDC_P0_MDSCR, 0x04008032, 847 MX6_MMDC_P0_MDSCR, 0x00008033, 848 MX6_MMDC_P0_MDSCR, 0x00048031, 849 MX6_MMDC_P0_MDSCR, 0x13208030, 850 /* ZQ calibration */ 851 MX6_MMDC_P0_MDSCR, 0x04008040, 852 853 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, 854 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, 855 MX6_MMDC_P0_MDREF, 0x00005800, 856 857 MX6_MMDC_P0_MPODTCTRL, 0x00000000, 858 MX6_MMDC_P1_MPODTCTRL, 0x00000000, 859 860 MX6_MMDC_P0_MPDGCTRL0, 0x42360232, 861 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A, 862 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224, 863 MX6_MMDC_P1_MPDGCTRL1, 0x02110218, 864 865 MX6_MMDC_P0_MPRDDLCTL, 0x41434344, 866 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E, 867 MX6_MMDC_P0_MPWRDLCTL, 0x39383339, 868 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930, 869 870 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039, 871 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D, 872 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019, 873 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D, 874 875 MX6_MMDC_P0_MPMUR0, 0x00000800, 876 MX6_MMDC_P1_MPMUR0, 0x00000800, 877 MX6_MMDC_P0_MDSCR, 0x00000000, 878 MX6_MMDC_P0_MAPSR, 0x00011006, 879 }; 880 881 static int mx6dl_dcd_table[] = { 882 /* ddr-setup.cfg */ 883 884 MX6_IOM_DRAM_SDQS0, 0x00000030, 885 MX6_IOM_DRAM_SDQS1, 0x00000030, 886 MX6_IOM_DRAM_SDQS2, 0x00000030, 887 MX6_IOM_DRAM_SDQS3, 0x00000030, 888 MX6_IOM_DRAM_SDQS4, 0x00000030, 889 MX6_IOM_DRAM_SDQS5, 0x00000030, 890 MX6_IOM_DRAM_SDQS6, 0x00000030, 891 MX6_IOM_DRAM_SDQS7, 0x00000030, 892 893 MX6_IOM_GRP_B0DS, 0x00000030, 894 MX6_IOM_GRP_B1DS, 0x00000030, 895 MX6_IOM_GRP_B2DS, 0x00000030, 896 MX6_IOM_GRP_B3DS, 0x00000030, 897 MX6_IOM_GRP_B4DS, 0x00000030, 898 MX6_IOM_GRP_B5DS, 0x00000030, 899 MX6_IOM_GRP_B6DS, 0x00000030, 900 MX6_IOM_GRP_B7DS, 0x00000030, 901 MX6_IOM_GRP_ADDDS, 0x00000030, 902 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 903 MX6_IOM_GRP_CTLDS, 0x00000030, 904 905 MX6_IOM_DRAM_DQM0, 0x00020030, 906 MX6_IOM_DRAM_DQM1, 0x00020030, 907 MX6_IOM_DRAM_DQM2, 0x00020030, 908 MX6_IOM_DRAM_DQM3, 0x00020030, 909 MX6_IOM_DRAM_DQM4, 0x00020030, 910 MX6_IOM_DRAM_DQM5, 0x00020030, 911 MX6_IOM_DRAM_DQM6, 0x00020030, 912 MX6_IOM_DRAM_DQM7, 0x00020030, 913 914 MX6_IOM_DRAM_CAS, 0x00020030, 915 MX6_IOM_DRAM_RAS, 0x00020030, 916 MX6_IOM_DRAM_SDCLK_0, 0x00020030, 917 MX6_IOM_DRAM_SDCLK_1, 0x00020030, 918 919 MX6_IOM_DRAM_RESET, 0x00020030, 920 MX6_IOM_DRAM_SDCKE0, 0x00003000, 921 MX6_IOM_DRAM_SDCKE1, 0x00003000, 922 923 MX6_IOM_DRAM_SDODT0, 0x00003030, 924 MX6_IOM_DRAM_SDODT1, 0x00003030, 925 926 /* (differential input) */ 927 MX6_IOM_DDRMODE_CTL, 0x00020000, 928 /* (differential input) */ 929 MX6_IOM_GRP_DDRMODE, 0x00020000, 930 /* disable ddr pullups */ 931 MX6_IOM_GRP_DDRPKE, 0x00000000, 932 MX6_IOM_DRAM_SDBA2, 0x00000000, 933 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 934 MX6_IOM_GRP_DDR_TYPE, 0x000C0000, 935 936 /* Read data DQ Byte0-3 delay */ 937 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, 938 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, 939 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, 940 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, 941 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, 942 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, 943 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, 944 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, 945 946 /* 947 * MDMISC mirroring interleaved (row/bank/col) 948 */ 949 /* TODO: check what the RALAT field does */ 950 MX6_MMDC_P0_MDMISC, 0x00081740, 951 952 /* 953 * MDSCR con_req 954 */ 955 MX6_MMDC_P0_MDSCR, 0x00008000, 956 957 958 /* 800mhz_2x64mx16.cfg */ 959 960 MX6_MMDC_P0_MDPDC, 0x0002002D, 961 MX6_MMDC_P0_MDCFG0, 0x2C305503, 962 MX6_MMDC_P0_MDCFG1, 0xB66D8D63, 963 MX6_MMDC_P0_MDCFG2, 0x01FF00DB, 964 MX6_MMDC_P0_MDRWD, 0x000026D2, 965 MX6_MMDC_P0_MDOR, 0x00301023, 966 MX6_MMDC_P0_MDOTC, 0x00333030, 967 MX6_MMDC_P0_MDPDC, 0x0002556D, 968 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */ 969 MX6_MMDC_P0_MDASP, 0x00000017, 970 /* DDR3 DATA BUS SIZE: 64BIT */ 971 MX6_MMDC_P0_MDCTL, 0x821A0000, 972 /* DDR3 DATA BUS SIZE: 32BIT */ 973 /* MX6_MMDC_P0_MDCTL, 0x82190000, */ 974 975 /* Write commands to DDR */ 976 /* Load Mode Registers */ 977 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ 978 /* MX6_MMDC_P0_MDSCR, 0x04408032, */ 979 MX6_MMDC_P0_MDSCR, 0x04008032, 980 MX6_MMDC_P0_MDSCR, 0x00008033, 981 MX6_MMDC_P0_MDSCR, 0x00048031, 982 MX6_MMDC_P0_MDSCR, 0x13208030, 983 /* ZQ calibration */ 984 MX6_MMDC_P0_MDSCR, 0x04008040, 985 986 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, 987 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, 988 MX6_MMDC_P0_MDREF, 0x00005800, 989 990 MX6_MMDC_P0_MPODTCTRL, 0x00000000, 991 MX6_MMDC_P1_MPODTCTRL, 0x00000000, 992 993 MX6_MMDC_P0_MPDGCTRL0, 0x42360232, 994 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A, 995 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224, 996 MX6_MMDC_P1_MPDGCTRL1, 0x02110218, 997 998 MX6_MMDC_P0_MPRDDLCTL, 0x41434344, 999 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E, 1000 MX6_MMDC_P0_MPWRDLCTL, 0x39383339, 1001 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930, 1002 1003 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039, 1004 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D, 1005 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019, 1006 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D, 1007 1008 MX6_MMDC_P0_MPMUR0, 0x00000800, 1009 MX6_MMDC_P1_MPMUR0, 0x00000800, 1010 MX6_MMDC_P0_MDSCR, 0x00000000, 1011 MX6_MMDC_P0_MAPSR, 0x00011006, 1012 }; 1013 1014 static void ccgr_init(void) 1015 { 1016 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1017 1018 writel(0x00C03F3F, &ccm->CCGR0); 1019 writel(0x0030FC03, &ccm->CCGR1); 1020 writel(0x0FFFFFF3, &ccm->CCGR2); 1021 writel(0x3FF0300F, &ccm->CCGR3); 1022 writel(0x00FFF300, &ccm->CCGR4); 1023 writel(0x0F0000F3, &ccm->CCGR5); 1024 writel(0x000003FF, &ccm->CCGR6); 1025 1026 /* 1027 * Setup CCM_CCOSR register as follows: 1028 * 1029 * cko1_en = 1 --> CKO1 enabled 1030 * cko1_div = 111 --> divide by 8 1031 * cko1_sel = 1011 --> ahb_clk_root 1032 * 1033 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz 1034 */ 1035 writel(0x000000FB, &ccm->ccosr); 1036 } 1037 1038 static void gpr_init(void) 1039 { 1040 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 1041 1042 /* enable AXI cache for VDOA/VPU/IPU */ 1043 writel(0xF00000CF, &iomux->gpr[4]); 1044 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 1045 writel(0x007F007F, &iomux->gpr[6]); 1046 writel(0x007F007F, &iomux->gpr[7]); 1047 } 1048 1049 static void ddr_init(int *table, int size) 1050 { 1051 int i; 1052 1053 for (i = 0; i < size / 2 ; i++) 1054 writel(table[2 * i + 1], table[2 * i]); 1055 } 1056 1057 static void spl_dram_init(void) 1058 { 1059 int minc, maxc; 1060 1061 switch (get_cpu_temp_grade(&minc, &maxc)) { 1062 case TEMP_COMMERCIAL: 1063 case TEMP_EXTCOMMERCIAL: 1064 if (is_cpu_type(MXC_CPU_MX6DL)) { 1065 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n"); 1066 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); 1067 } else { 1068 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); 1069 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); 1070 } 1071 break; 1072 case TEMP_INDUSTRIAL: 1073 case TEMP_AUTOMOTIVE: 1074 default: 1075 if (is_cpu_type(MXC_CPU_MX6DL)) { 1076 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); 1077 } else { 1078 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); 1079 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); 1080 } 1081 break; 1082 }; 1083 udelay(100); 1084 } 1085 1086 void board_init_f(ulong dummy) 1087 { 1088 /* setup AIPS and disable watchdog */ 1089 arch_cpu_init(); 1090 1091 ccgr_init(); 1092 gpr_init(); 1093 1094 /* iomux and setup of i2c */ 1095 board_early_init_f(); 1096 1097 /* setup GP timer */ 1098 timer_init(); 1099 1100 /* UART clocks enabled and gd valid - init serial console */ 1101 preloader_console_init(); 1102 1103 /* Make sure we use dte mode */ 1104 setup_dtemode_uart(); 1105 1106 /* DDR initialization */ 1107 spl_dram_init(); 1108 1109 /* Clear the BSS. */ 1110 memset(__bss_start, 0, __bss_end - __bss_start); 1111 1112 /* load/boot image from boot device */ 1113 board_init_r(NULL, 0); 1114 } 1115 1116 void reset_cpu(ulong addr) 1117 { 1118 } 1119 1120 #endif 1121 1122 static struct mxc_serial_platdata mxc_serial_plat = { 1123 .reg = (struct mxc_uart *)UART1_BASE, 1124 .use_dte = true, 1125 }; 1126 1127 U_BOOT_DEVICE(mxc_serial) = { 1128 .name = "serial_mxc", 1129 .platdata = &mxc_serial_plat, 1130 }; 1131