1 /*
2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3  *
4  * Based on:
5  *
6  * -------------------------------------------------------------------------
7  *
8  *  linux/include/asm-arm/arch-davinci/hardware.h
9  *
10  *  Copyright (C) 2006 Texas Instruments.
11  *
12  * SPDX-License-Identifier:	GPL-2.0+
13  */
14 #ifndef __ASM_ARCH_HARDWARE_H
15 #define __ASM_ARCH_HARDWARE_H
16 
17 #include <config.h>
18 #include <linux/sizes.h>
19 
20 #define	REG(addr)	(*(volatile unsigned int *)(addr))
21 #define REG_P(addr)	((volatile unsigned int *)(addr))
22 
23 typedef volatile unsigned int	dv_reg;
24 typedef volatile unsigned int *	dv_reg_p;
25 
26 /*
27  * Base register addresses
28  *
29  * NOTE:  some of these DM6446-specific addresses DO NOT WORK
30  * on other DaVinci chips.  Double check them before you try
31  * using the addresses ... or PSC module identifiers, etc.
32  */
33 #ifndef CONFIG_SOC_DA8XX
34 
35 #define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
38 #define DAVINCI_UART0_BASE			(0x01c20000)
39 #define DAVINCI_UART1_BASE			(0x01c20400)
40 #define DAVINCI_TIMER3_BASE			(0x01c20800)
41 #define DAVINCI_I2C_BASE			(0x01c21000)
42 #define DAVINCI_TIMER0_BASE			(0x01c21400)
43 #define DAVINCI_TIMER1_BASE			(0x01c21800)
44 #define DAVINCI_WDOG_BASE			(0x01c21c00)
45 #define DAVINCI_PWM0_BASE			(0x01c22000)
46 #define DAVINCI_PWM1_BASE			(0x01c22400)
47 #define DAVINCI_PWM2_BASE			(0x01c22800)
48 #define DAVINCI_TIMER4_BASE			(0x01c23800)
49 #define DAVINCI_SYSTEM_MODULE_BASE		(0x01c40000)
50 #define DAVINCI_PLL_CNTRL0_BASE			(0x01c40800)
51 #define DAVINCI_PLL_CNTRL1_BASE			(0x01c40c00)
52 #define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01c41000)
53 #define DAVINCI_ARM_INTC_BASE			(0x01c48000)
54 #define DAVINCI_USB_OTG_BASE			(0x01c64000)
55 #define DAVINCI_CFC_ATA_BASE			(0x01c66000)
56 #define DAVINCI_SPI_BASE			(0x01c66800)
57 #define DAVINCI_GPIO_BASE			(0x01c67000)
58 #define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
59 #if !defined(CONFIG_SOC_DM646X)
60 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
61 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
62 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
63 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
64 #endif
65 #define DAVINCI_DDR_BASE			(0x80000000)
66 
67 #ifdef CONFIG_SOC_DM644X
68 #define DAVINCI_UART2_BASE			0x01c20800
69 #define DAVINCI_UHPI_BASE			0x01c67800
70 #define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01c80000
71 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01c81000
72 #define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01c82000
73 #define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01c84000
74 #define DAVINCI_IMCOP_BASE			0x01cc0000
75 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e00000
76 #define DAVINCI_VLYNQ_BASE			0x01e01000
77 #define DAVINCI_ASP_BASE			0x01e02000
78 #define DAVINCI_MMC_SD_BASE			0x01e10000
79 #define DAVINCI_MS_BASE				0x01e20000
80 #define DAVINCI_VLYNQ_REMOTE_BASE		0x0c000000
81 
82 #elif defined(CONFIG_SOC_DM355)
83 #define DAVINCI_MMC_SD1_BASE			0x01e00000
84 #define DAVINCI_ASP0_BASE			0x01e02000
85 #define DAVINCI_ASP1_BASE			0x01e04000
86 #define DAVINCI_UART2_BASE			0x01e06000
87 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
88 #define DAVINCI_MMC_SD0_BASE			0x01e11000
89 
90 #elif defined(CONFIG_SOC_DM365)
91 #define DAVINCI_MMC_SD1_BASE			0x01d00000
92 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01d10000
93 #define DAVINCI_MMC_SD0_BASE			0x01d11000
94 #define DAVINCI_DDR_EMIF_CTRL_BASE		0x20000000
95 #define DAVINCI_SPI0_BASE			0x01c66000
96 #define DAVINCI_SPI1_BASE			0x01c66800
97 
98 #elif defined(CONFIG_SOC_DM646X)
99 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x20008000
100 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x42000000
101 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	0x44000000
102 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x46000000
103 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
104 
105 #endif
106 
107 #else /* CONFIG_SOC_DA8XX */
108 
109 #define DAVINCI_UART0_BASE			0x01c42000
110 #define DAVINCI_UART1_BASE			0x01d0c000
111 #define DAVINCI_UART2_BASE			0x01d0d000
112 #define DAVINCI_I2C0_BASE			0x01c22000
113 #define DAVINCI_I2C1_BASE			0x01e28000
114 #define DAVINCI_TIMER0_BASE			0x01c20000
115 #define DAVINCI_TIMER1_BASE			0x01c21000
116 #define DAVINCI_WDOG_BASE			0x01c21000
117 #define DAVINCI_RTC_BASE			0x01c23000
118 #define DAVINCI_PLL_CNTRL0_BASE			0x01c11000
119 #define DAVINCI_PLL_CNTRL1_BASE			0x01e1a000
120 #define DAVINCI_PSC0_BASE			0x01c10000
121 #define DAVINCI_PSC1_BASE			0x01e27000
122 #define DAVINCI_SPI0_BASE			0x01c41000
123 #define DAVINCI_USB_OTG_BASE			0x01e00000
124 #define DAVINCI_SPI1_BASE			(cpu_is_da830() ? \
125 						0x01e12000 : 0x01f0e000)
126 #define DAVINCI_GPIO_BASE			0x01e26000
127 #define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01e23000
128 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01e22000
129 #define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01e20000
130 #define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01e24000
131 #define DAVINCI_SYSCFG1_BASE			0x01e2c000
132 #define DAVINCI_MMC_SD0_BASE			0x01c40000
133 #define DAVINCI_MMC_SD1_BASE			0x01e1b000
134 #define DAVINCI_TIMER2_BASE			0x01f0c000
135 #define DAVINCI_TIMER3_BASE			0x01f0d000
136 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x68000000
137 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x40000000
138 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x60000000
139 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x62000000
140 #define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE	0x64000000
141 #define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE	0x66000000
142 #define DAVINCI_DDR_EMIF_CTRL_BASE		0xb0000000
143 #define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
144 #define DAVINCI_INTC_BASE			0xfffee000
145 #define DAVINCI_BOOTCFG_BASE			0x01c14000
146 #define DAVINCI_LCD_CNTL_BASE			0x01e13000
147 #define DAVINCI_L3CBARAM_BASE			0x80000000
148 #define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
149 #define CHIP_REV_ID_REG				(DAVINCI_BOOTCFG_BASE + 0x24)
150 #define HOST1CFG				(DAVINCI_BOOTCFG_BASE + 0x44)
151 #define PSC0_MDCTL				(DAVINCI_PSC0_BASE + 0xa00)
152 
153 #define GPIO_BANK0_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x10)
154 #define GPIO_BANK0_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x14)
155 #define GPIO_BANK0_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x18)
156 #define GPIO_BANK0_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x1c)
157 #define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
158 #define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
159 #define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
160 #define GPIO_BANK2_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x44)
161 #define GPIO_BANK6_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x88)
162 #define GPIO_BANK6_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x8c)
163 #define GPIO_BANK6_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x90)
164 #define GPIO_BANK6_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x94)
165 #endif /* CONFIG_SOC_DA8XX */
166 
167 /* Power and Sleep Controller (PSC) Domains */
168 #define DAVINCI_GPSC_ARMDOMAIN		0
169 #define DAVINCI_GPSC_DSPDOMAIN		1
170 
171 #ifndef CONFIG_SOC_DA8XX
172 
173 #define DAVINCI_LPSC_VPSSMSTR		0
174 #define DAVINCI_LPSC_VPSSSLV		1
175 #define DAVINCI_LPSC_TPCC		2
176 #define DAVINCI_LPSC_TPTC0		3
177 #define DAVINCI_LPSC_TPTC1		4
178 #define DAVINCI_LPSC_EMAC		5
179 #define DAVINCI_LPSC_EMAC_WRAPPER	6
180 #define DAVINCI_LPSC_MDIO		7
181 #define DAVINCI_LPSC_IEEE1394		8
182 #define DAVINCI_LPSC_USB		9
183 #define DAVINCI_LPSC_ATA		10
184 #define DAVINCI_LPSC_VLYNQ		11
185 #define DAVINCI_LPSC_UHPI		12
186 #define DAVINCI_LPSC_DDR_EMIF		13
187 #define DAVINCI_LPSC_AEMIF		14
188 #define DAVINCI_LPSC_MMC_SD		15
189 #define DAVINCI_LPSC_MEMSTICK		16
190 #define DAVINCI_LPSC_McBSP		17
191 #define DAVINCI_LPSC_I2C		18
192 #define DAVINCI_LPSC_UART0		19
193 #define DAVINCI_LPSC_UART1		20
194 #define DAVINCI_LPSC_UART2		21
195 #define DAVINCI_LPSC_SPI		22
196 #define DAVINCI_LPSC_PWM0		23
197 #define DAVINCI_LPSC_PWM1		24
198 #define DAVINCI_LPSC_PWM2		25
199 #define DAVINCI_LPSC_GPIO		26
200 #define DAVINCI_LPSC_TIMER0		27
201 #define DAVINCI_LPSC_TIMER1		28
202 #define DAVINCI_LPSC_TIMER2		29
203 #define DAVINCI_LPSC_SYSTEM_SUBSYS	30
204 #define DAVINCI_LPSC_ARM		31
205 #define DAVINCI_LPSC_SCR2		32
206 #define DAVINCI_LPSC_SCR3		33
207 #define DAVINCI_LPSC_SCR4		34
208 #define DAVINCI_LPSC_CROSSBAR		35
209 #define DAVINCI_LPSC_CFG27		36
210 #define DAVINCI_LPSC_CFG3		37
211 #define DAVINCI_LPSC_CFG5		38
212 #define DAVINCI_LPSC_GEM		39
213 #define DAVINCI_LPSC_IMCOP		40
214 #define DAVINCI_LPSC_VPSSMASTER		47
215 #define DAVINCI_LPSC_MJCP		50
216 #define DAVINCI_LPSC_HDVICP		51
217 
218 #define DAVINCI_DM646X_LPSC_EMAC	14
219 #define DAVINCI_DM646X_LPSC_UART0	26
220 #define DAVINCI_DM646X_LPSC_I2C		31
221 #define DAVINCI_DM646X_LPSC_TIMER0	34
222 
223 #else /* CONFIG_SOC_DA8XX */
224 
225 #define DAVINCI_LPSC_TPCC		0
226 #define DAVINCI_LPSC_TPTC0		1
227 #define DAVINCI_LPSC_TPTC1		2
228 #define DAVINCI_LPSC_AEMIF		3
229 #define DAVINCI_LPSC_SPI0		4
230 #define DAVINCI_LPSC_MMC_SD		5
231 #define DAVINCI_LPSC_AINTC		6
232 #define DAVINCI_LPSC_ARM_RAM_ROM	7
233 #define DAVINCI_LPSC_SECCTL_KEYMGR	8
234 #define DAVINCI_LPSC_UART0		9
235 #define DAVINCI_LPSC_SCR0		10
236 #define DAVINCI_LPSC_SCR1		11
237 #define DAVINCI_LPSC_SCR2		12
238 #define DAVINCI_LPSC_DMAX		13
239 #define DAVINCI_LPSC_ARM		14
240 #define DAVINCI_LPSC_GEM		15
241 
242 /* for LPSCs in PSC1, offset from 32 for differentiation */
243 #define DAVINCI_LPSC_PSC1_BASE		32
244 #define DAVINCI_LPSC_USB20		(DAVINCI_LPSC_PSC1_BASE + 1)
245 #define DAVINCI_LPSC_USB11		(DAVINCI_LPSC_PSC1_BASE + 2)
246 #define DAVINCI_LPSC_GPIO		(DAVINCI_LPSC_PSC1_BASE + 3)
247 #define DAVINCI_LPSC_UHPI		(DAVINCI_LPSC_PSC1_BASE + 4)
248 #define DAVINCI_LPSC_EMAC		(DAVINCI_LPSC_PSC1_BASE + 5)
249 #define DAVINCI_LPSC_DDR_EMIF		(DAVINCI_LPSC_PSC1_BASE + 6)
250 #define DAVINCI_LPSC_McASP0		(DAVINCI_LPSC_PSC1_BASE + 7)
251 #define DAVINCI_LPSC_SPI1		(DAVINCI_LPSC_PSC1_BASE + 10)
252 #define DAVINCI_LPSC_I2C1		(DAVINCI_LPSC_PSC1_BASE + 11)
253 #define DAVINCI_LPSC_UART1		(DAVINCI_LPSC_PSC1_BASE + 12)
254 #define DAVINCI_LPSC_UART2		(DAVINCI_LPSC_PSC1_BASE + 13)
255 #define DAVINCI_LPSC_LCDC		(DAVINCI_LPSC_PSC1_BASE + 16)
256 #define DAVINCI_LPSC_ePWM		(DAVINCI_LPSC_PSC1_BASE + 17)
257 #define DAVINCI_LPSC_MMCSD1		(DAVINCI_LPSC_PSC1_BASE + 18)
258 #define DAVINCI_LPSC_eCAP		(DAVINCI_LPSC_PSC1_BASE + 20)
259 #define DAVINCI_LPSC_L3_CBA_RAM		(DAVINCI_LPSC_PSC1_BASE + 31)
260 
261 /* DA830-specific peripherals */
262 #define DAVINCI_LPSC_McASP1		(DAVINCI_LPSC_PSC1_BASE + 8)
263 #define DAVINCI_LPSC_McASP2		(DAVINCI_LPSC_PSC1_BASE + 9)
264 #define DAVINCI_LPSC_eQEP		(DAVINCI_LPSC_PSC1_BASE + 21)
265 #define DAVINCI_LPSC_SCR8		(DAVINCI_LPSC_PSC1_BASE + 24)
266 #define DAVINCI_LPSC_SCR7		(DAVINCI_LPSC_PSC1_BASE + 25)
267 #define DAVINCI_LPSC_SCR12		(DAVINCI_LPSC_PSC1_BASE + 26)
268 
269 /* DA850-specific peripherals */
270 #define DAVINCI_LPSC_TPCC1		(DAVINCI_LPSC_PSC1_BASE + 0)
271 #define DAVINCI_LPSC_SATA		(DAVINCI_LPSC_PSC1_BASE + 8)
272 #define DAVINCI_LPSC_VPIF		(DAVINCI_LPSC_PSC1_BASE + 9)
273 #define DAVINCI_LPSC_McBSP0		(DAVINCI_LPSC_PSC1_BASE + 14)
274 #define DAVINCI_LPSC_McBSP1		(DAVINCI_LPSC_PSC1_BASE + 15)
275 #define DAVINCI_LPSC_MMC_SD1		(DAVINCI_LPSC_PSC1_BASE + 18)
276 #define DAVINCI_LPSC_uPP		(DAVINCI_LPSC_PSC1_BASE + 19)
277 #define DAVINCI_LPSC_TPTC2		(DAVINCI_LPSC_PSC1_BASE + 21)
278 #define DAVINCI_LPSC_SCR_F0		(DAVINCI_LPSC_PSC1_BASE + 24)
279 #define DAVINCI_LPSC_SCR_F1		(DAVINCI_LPSC_PSC1_BASE + 25)
280 #define DAVINCI_LPSC_SCR_F2		(DAVINCI_LPSC_PSC1_BASE + 26)
281 #define DAVINCI_LPSC_SCR_F6		(DAVINCI_LPSC_PSC1_BASE + 27)
282 #define DAVINCI_LPSC_SCR_F7		(DAVINCI_LPSC_PSC1_BASE + 28)
283 #define DAVINCI_LPSC_SCR_F8		(DAVINCI_LPSC_PSC1_BASE + 29)
284 #define DAVINCI_LPSC_BR_F7		(DAVINCI_LPSC_PSC1_BASE + 30)
285 
286 #endif /* CONFIG_SOC_DA8XX */
287 
288 void lpsc_on(unsigned int id);
289 void lpsc_syncreset(unsigned int id);
290 void lpsc_disable(unsigned int id);
291 void dsp_on(void);
292 
293 void davinci_enable_uart0(void);
294 void davinci_enable_emac(void);
295 void davinci_enable_i2c(void);
296 void davinci_errata_workarounds(void);
297 
298 #ifndef CONFIG_SOC_DA8XX
299 
300 /* Some PSC defines */
301 #define PSC_CHP_SHRTSW			(0x01c40038)
302 #define PSC_GBLCTL			(0x01c41010)
303 #define PSC_EPCPR			(0x01c41070)
304 #define PSC_EPCCR			(0x01c41078)
305 #define PSC_PTCMD			(0x01c41120)
306 #define PSC_PTSTAT			(0x01c41128)
307 #define PSC_PDSTAT			(0x01c41200)
308 #define PSC_PDSTAT1			(0x01c41204)
309 #define PSC_PDCTL			(0x01c41300)
310 #define PSC_PDCTL1			(0x01c41304)
311 
312 #define PSC_MDCTL_BASE			(0x01c41a00)
313 #define PSC_MDSTAT_BASE			(0x01c41800)
314 
315 #define VDD3P3V_PWDN			(0x01c40048)
316 #define UART0_PWREMU_MGMT		(0x01c20030)
317 
318 #define PSC_SILVER_BULLET		(0x01c41a20)
319 
320 #else /* CONFIG_SOC_DA8XX */
321 
322 #define	PSC_ENABLE		0x3
323 #define	PSC_DISABLE		0x2
324 #define	PSC_SYNCRESET		0x1
325 #define	PSC_SWRSTDISABLE	0x0
326 
327 #define PSC_PSC0_MODULE_ID_CNT		16
328 #define PSC_PSC1_MODULE_ID_CNT		32
329 
330 #define UART0_PWREMU_MGMT		(0x01c42030)
331 
332 struct davinci_psc_regs {
333 	dv_reg	revid;
334 	dv_reg	rsvd0[71];
335 	dv_reg	ptcmd;
336 	dv_reg	rsvd1;
337 	dv_reg	ptstat;
338 	dv_reg	rsvd2[437];
339 	union {
340 		struct {
341 			dv_reg	mdstat[PSC_PSC0_MODULE_ID_CNT];
342 			dv_reg	rsvd3[112];
343 			dv_reg	mdctl[PSC_PSC0_MODULE_ID_CNT];
344 		} psc0;
345 		struct {
346 			dv_reg	mdstat[PSC_PSC1_MODULE_ID_CNT];
347 			dv_reg	rsvd3[96];
348 			dv_reg	mdctl[PSC_PSC1_MODULE_ID_CNT];
349 		} psc1;
350 	};
351 };
352 
353 #define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
354 #define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
355 
356 #endif /* CONFIG_SOC_DA8XX */
357 
358 #define PSC_MDSTAT_STATE		0x3f
359 #define PSC_MDCTL_NEXT			0x07
360 
361 #ifndef CONFIG_SOC_DA8XX
362 
363 /* Miscellania... */
364 #define VBPR				(0x20000020)
365 
366 /* NOTE:  system control modules are *highly* chip-specific, both
367  * as to register content (e.g. for muxing) and which registers exist.
368  */
369 #define PINMUX0				0x01c40000
370 #define PINMUX1				0x01c40004
371 #define PINMUX2				0x01c40008
372 #define PINMUX3				0x01c4000c
373 #define PINMUX4				0x01c40010
374 
375 struct davinci_uart_ctrl_regs {
376 	dv_reg	revid1;
377 	dv_reg	res;
378 	dv_reg	pwremu_mgmt;
379 	dv_reg	mdr;
380 };
381 
382 #define DAVINCI_UART_CTRL_BASE 0x28
383 
384 /* UART PWREMU_MGMT definitions */
385 #define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
386 #define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
387 #define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
388 
389 #else /* CONFIG_SOC_DA8XX */
390 
391 struct davinci_pllc_regs {
392 	dv_reg	revid;
393 	dv_reg	rsvd1[56];
394 	dv_reg	rstype;
395 	dv_reg	rsvd2[6];
396 	dv_reg	pllctl;
397 	dv_reg	ocsel;
398 	dv_reg	rsvd3[2];
399 	dv_reg	pllm;
400 	dv_reg	prediv;
401 	dv_reg	plldiv1;
402 	dv_reg	plldiv2;
403 	dv_reg	plldiv3;
404 	dv_reg	oscdiv;
405 	dv_reg	postdiv;
406 	dv_reg	rsvd4[3];
407 	dv_reg	pllcmd;
408 	dv_reg	pllstat;
409 	dv_reg	alnctl;
410 	dv_reg	dchange;
411 	dv_reg	cken;
412 	dv_reg	ckstat;
413 	dv_reg	systat;
414 	dv_reg	rsvd5[3];
415 	dv_reg	plldiv4;
416 	dv_reg	plldiv5;
417 	dv_reg	plldiv6;
418 	dv_reg	plldiv7;
419 	dv_reg	rsvd6[32];
420 	dv_reg	emucnt0;
421 	dv_reg	emucnt1;
422 };
423 
424 #define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
425 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
426 #define DAVINCI_PLLC_DIV_MASK	0x1f
427 
428 /*
429  * A clock ID is a 32-bit number where bit 16 represents the PLL controller
430  * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
431  * counting from 1. Clock IDs may be passed to clk_get().
432  */
433 
434 /* flags to select PLL controller */
435 #define DAVINCI_PLLC0_FLAG			(0)
436 #define DAVINCI_PLLC1_FLAG			(1 << 16)
437 
438 enum davinci_clk_ids {
439 	/*
440 	 * Clock IDs for PLL outputs. Each may be switched on/off
441 	 * independently, and each may map to one or more peripherals.
442 	 */
443 	DAVINCI_PLL0_SYSCLK2			= DAVINCI_PLLC0_FLAG | 2,
444 	DAVINCI_PLL0_SYSCLK4			= DAVINCI_PLLC0_FLAG | 4,
445 	DAVINCI_PLL0_SYSCLK6			= DAVINCI_PLLC0_FLAG | 6,
446 	DAVINCI_PLL1_SYSCLK1			= DAVINCI_PLLC1_FLAG | 1,
447 	DAVINCI_PLL1_SYSCLK2			= DAVINCI_PLLC1_FLAG | 2,
448 
449 	/* map peripherals to clock IDs */
450 	DAVINCI_ARM_CLKID			= DAVINCI_PLL0_SYSCLK6,
451 	DAVINCI_DDR_CLKID			= DAVINCI_PLL1_SYSCLK1,
452 	DAVINCI_MDIO_CLKID			= DAVINCI_PLL0_SYSCLK4,
453 	DAVINCI_MMC_CLKID			= DAVINCI_PLL0_SYSCLK2,
454 	DAVINCI_SPI0_CLKID			= DAVINCI_PLL0_SYSCLK2,
455 	DAVINCI_MMCSD_CLKID			= DAVINCI_PLL0_SYSCLK2,
456 
457 	/* special clock ID - output of PLL multiplier */
458 	DAVINCI_PLLM_CLKID			= 0x0FF,
459 
460 	/* special clock ID - output of PLL post divisor */
461 	DAVINCI_PLLC_CLKID			= 0x100,
462 
463 	/* special clock ID - PLL bypass */
464 	DAVINCI_AUXCLK_CLKID			= 0x101,
465 };
466 
467 #define DAVINCI_UART2_CLKID	(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
468 						: get_async3_src())
469 
470 #define DAVINCI_SPI1_CLKID	(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
471 						: get_async3_src())
472 
473 int clk_get(enum davinci_clk_ids id);
474 
475 /* Boot config */
476 struct davinci_syscfg_regs {
477 	dv_reg	revid;
478 	dv_reg	rsvd[7];
479 	dv_reg	bootcfg;
480 	dv_reg	chiprevidr;
481 	dv_reg	rsvd2[4];
482 	dv_reg	kick0;
483 	dv_reg	kick1;
484 	dv_reg	rsvd1[52];
485 	dv_reg	mstpri[3];
486 	dv_reg  rsvd3;
487 	dv_reg	pinmux[20];
488 	dv_reg	suspsrc;
489 	dv_reg	chipsig;
490 	dv_reg	chipsig_clr;
491 	dv_reg	cfgchip0;
492 	dv_reg	cfgchip1;
493 	dv_reg	cfgchip2;
494 	dv_reg	cfgchip3;
495 	dv_reg	cfgchip4;
496 };
497 
498 #define davinci_syscfg_regs \
499 	((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
500 
501 enum {
502 	DAVINCI_NAND8_BOOT	= 0b001110,
503 	DAVINCI_NAND16_BOOT	= 0b010000,
504 	DAVINCI_SD_OR_MMC_BOOT	= 0b011100,
505 	DAVINCI_MMC_ONLY_BOOT	= 0b111100,
506 	DAVINCI_SPI0_FLASH_BOOT	= 0b001010,
507 	DAVINCI_SPI1_FLASH_BOOT	= 0b001100,
508 };
509 
510 #define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
511 
512 /* Emulation suspend bits */
513 #define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
514 #define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
515 #define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
516 #define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
517 #define DAVINCI_SYSCFG_SUSPSRC_UART0		(1 << 18)
518 #define DAVINCI_SYSCFG_SUSPSRC_UART1		(1 << 19)
519 #define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
520 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
521 
522 struct davinci_syscfg1_regs {
523 	dv_reg	vtpio_ctl;
524 	dv_reg	ddr_slew;
525 	dv_reg	deepsleep;
526 	dv_reg	pupd_ena;
527 	dv_reg	pupd_sel;
528 	dv_reg	rxactive;
529 	dv_reg	pwrdwn;
530 };
531 
532 #define davinci_syscfg1_regs \
533 	((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
534 
535 #define DDR_SLEW_CMOSEN_BIT	4
536 #define DDR_SLEW_DDR_PDENA_BIT	5
537 
538 #define VTP_POWERDWN		(1 << 6)
539 #define VTP_LOCK		(1 << 7)
540 #define VTP_CLKRZ		(1 << 13)
541 #define VTP_READY		(1 << 15)
542 #define VTP_IOPWRDWN		(1 << 14)
543 
544 #define DV_SYSCFG_KICK0_UNLOCK	0x83e70b13
545 #define DV_SYSCFG_KICK1_UNLOCK	0x95a4f1e0
546 
547 /* Interrupt controller */
548 struct davinci_aintc_regs {
549 	dv_reg	revid;
550 	dv_reg	cr;
551 	dv_reg	dummy0[2];
552 	dv_reg	ger;
553 	dv_reg	dummy1[219];
554 	dv_reg	ecr1;
555 	dv_reg	ecr2;
556 	dv_reg	ecr3;
557 	dv_reg	dummy2[1117];
558 	dv_reg	hier;
559 };
560 
561 #define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
562 
563 struct davinci_uart_ctrl_regs {
564 	dv_reg	revid1;
565 	dv_reg	revid2;
566 	dv_reg	pwremu_mgmt;
567 	dv_reg	mdr;
568 };
569 
570 #define DAVINCI_UART_CTRL_BASE 0x28
571 #define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
572 #define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
573 #define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
574 
575 #define davinci_uart0_ctrl_regs \
576 	((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
577 #define davinci_uart1_ctrl_regs \
578 	((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
579 #define davinci_uart2_ctrl_regs \
580 	((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
581 
582 /* UART PWREMU_MGMT definitions */
583 #define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
584 #define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
585 #define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
586 
587 static inline int cpu_is_da830(void)
588 {
589 	unsigned int jtag_id	= REG(JTAG_ID_REG);
590 	unsigned short part_no	= (jtag_id >> 12) & 0xffff;
591 
592 	return ((part_no == 0xb7df) ? 1 : 0);
593 }
594 static inline int cpu_is_da850(void)
595 {
596 	unsigned int jtag_id    = REG(JTAG_ID_REG);
597 	unsigned short part_no  = (jtag_id >> 12) & 0xffff;
598 
599 	return ((part_no == 0xb7d1) ? 1 : 0);
600 }
601 
602 static inline enum davinci_clk_ids get_async3_src(void)
603 {
604 	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
605 			DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
606 }
607 
608 #endif /* CONFIG_SOC_DA8XX */
609 
610 #if defined(CONFIG_SOC_DM365)
611 #include <asm/arch/aintc_defs.h>
612 #include <asm/arch/ddr2_defs.h>
613 #include <asm/arch/gpio.h>
614 #include <asm/arch/pll_defs.h>
615 #include <asm/arch/psc_defs.h>
616 #include <asm/arch/syscfg_defs.h>
617 #include <asm/arch/timer_defs.h>
618 
619 #define TMPBUF			0x00017ff8
620 #define TMPSTATUS		0x00017ff0
621 #define DV_TMPBUF_VAL		0x591b3ed7
622 #define FLAG_PORRST		0x00000001
623 #define FLAG_WDTRST		0x00000002
624 #define FLAG_FLGON		0x00000004
625 #define FLAG_FLGOFF		0x00000010
626 
627 #endif
628 
629 #endif /* __ASM_ARCH_HARDWARE_H */
630