1 /*
2  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
3  * Copyright (c) 2016 Andreas Färber
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/armv8/mmu.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/cru_rk3368.h>
13 #include <asm/arch/grf_rk3368.h>
14 #include <syscon.h>
15 
16 DECLARE_GLOBAL_DATA_PTR;
17 
18 #define IMEM_BASE                  0xFF8C0000
19 
20 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
21 #define MCU_SRAM_BASE			(IMEM_BASE + 1024 * 4)
22 #define MCU_SRAM_BASE_BIT31_BIT28	((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
23 #define MCU_SRAM_BASE_BIT27_BIT12	((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
24 /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
25 #define MCU_EXSRAM_BASE    (0)
26 #define MCU_EXSRAM_BASE_BIT31_BIT28       ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
27 #define MCU_EXSRAM_BASE_BIT27_BIT12       ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
28 /* experi no used, reserved value = 0 */
29 #define MCU_EXPERI_BASE    (0)
30 #define MCU_EXPERI_BASE_BIT31_BIT28       ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
31 #define MCU_EXPERI_BASE_BIT27_BIT12       ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
32 
33 static struct mm_region rk3368_mem_map[] = {
34 	{
35 		.virt = 0x0UL,
36 		.phys = 0x0UL,
37 		.size = 0x80000000UL,
38 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
39 			 PTE_BLOCK_INNER_SHARE
40 	}, {
41 		.virt = 0xf0000000UL,
42 		.phys = 0xf0000000UL,
43 		.size = 0x10000000UL,
44 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
45 			 PTE_BLOCK_NON_SHARE |
46 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
47 	}, {
48 		/* List terminator */
49 		0,
50 	}
51 };
52 
53 struct mm_region *mem_map = rk3368_mem_map;
54 
55 int dram_init_banksize(void)
56 {
57 	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
58 
59 	/* Reserve 0x200000 for ATF bl31 */
60 	gd->bd->bi_dram[0].start = 0x200000;
61 	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
62 
63 	return 0;
64 }
65 
66 #ifdef CONFIG_ARCH_EARLY_INIT_R
67 static int mcu_init(void)
68 {
69 	struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
70 	struct rk3368_cru *cru = rockchip_get_cru();
71 
72 	rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
73 		     MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
74 	rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
75 		     MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
76 	rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
77 		     MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
78 	rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
79 		     MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
80 	rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
81 		     MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
82 	rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
83 		     MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
84 
85 	rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
86 		     (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
87 		     (5 << MCU_CLK_DIV_SHIFT));
88 
89 	 /* mcu dereset, for start running */
90 	rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
91 
92 	return 0;
93 }
94 
95 int arch_early_init_r(void)
96 {
97 	return mcu_init();
98 }
99 #endif
100