1 /*
2  * (C) Copyright 2010 - 2011
3  * NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/emc.h>
13 #include <asm/arch/gp_padctrl.h>
14 #include <asm/arch/pinmux.h>
15 #include <asm/arch/sdram_param.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/apb_misc.h>
19 #include <asm/arch-tegra/clk_rst.h>
20 #include <asm/arch-tegra/pmc.h>
21 #include <asm/arch-tegra/fuse.h>
22 #include <asm/arch-tegra/warmboot.h>
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 #ifndef CONFIG_TEGRA_CLOCK_SCALING
27 #error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
28 #endif
29 
30 /*
31  * This is the place in SRAM where the SDRAM parameters are stored. There
32  * are 4 blocks, one for each RAM code
33  */
34 #define SDRAM_PARAMS_BASE	(NV_PA_BASE_SRAM + 0x188)
35 
36 /* TODO: If we later add support for the Misc GP controller, refactor this */
37 union xm2cfga_reg {
38 	struct {
39 		u32 reserved0:2;
40 		u32 hsm_en:1;
41 		u32 reserved1:2;
42 		u32 preemp_en:1;
43 		u32 vref_en:1;
44 		u32 reserved2:5;
45 		u32 cal_drvdn:5;
46 		u32 reserved3:3;
47 		u32 cal_drvup:5;
48 		u32 reserved4:3;
49 		u32 cal_drvdn_slwr:2;
50 		u32 cal_drvup_slwf:2;
51 	};
52 	u32 word;
53 };
54 
55 union xm2cfgd_reg {
56 	struct {
57 		u32 reserved0:2;
58 		u32 hsm_en:1;
59 		u32 schmt_en:1;
60 		u32 lpmd:2;
61 		u32 vref_en:1;
62 		u32 reserved1:5;
63 		u32 cal_drvdn:5;
64 		u32 reserved2:3;
65 		u32 cal_drvup:5;
66 		u32 reserved3:3;
67 		u32 cal_drvdn_slwr:2;
68 		u32 cal_drvup_slwf:2;
69 	};
70 	u32 word;
71 };
72 
73 /*
74  * TODO: This register is not documented in the TRM yet. We could move this
75  * into the EMC and give it a proper interface, but not while it is
76  * undocumented.
77  */
78 union fbio_spare_reg {
79 	struct {
80 		u32 reserved:24;
81 		u32 cfg_wb0:8;
82 	};
83 	u32 word;
84 };
85 
86 /* We pack the resume information into these unions for later */
87 union scratch2_reg {
88 	struct {
89 		u32 pllm_base_divm:5;
90 		u32 pllm_base_divn:10;
91 		u32 pllm_base_divp:3;
92 		u32 pllm_misc_lfcon:4;
93 		u32 pllm_misc_cpcon:4;
94 		u32 gp_xm2cfga_padctrl_preemp:1;
95 		u32 gp_xm2cfgd_padctrl_schmt:1;
96 		u32 osc_ctrl_xobp:1;
97 		u32 memory_type:3;
98 	};
99 	u32 word;
100 };
101 
102 union scratch4_reg {
103 	struct {
104 		u32 emc_clock_divider:8;
105 		u32 pllm_stable_time:8;
106 		u32 pllx_stable_time:8;
107 		u32 emc_fbio_spare_cfg_wb0:8;
108 	};
109 	u32 word;
110 };
111 
112 union scratch24_reg {
113 	struct {
114 		u32 emc_auto_cal_wait:8;
115 		u32 emc_pin_program_wait:8;
116 		u32 warmboot_wait:8;
117 		u32 reserved:8;
118 	};
119 	u32 word;
120 };
121 
122 int warmboot_save_sdram_params(void)
123 {
124 	u32 ram_code;
125 	struct sdram_params sdram;
126 	struct apb_misc_pp_ctlr *apb_misc =
127 				(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
128 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
129 	struct apb_misc_gp_ctlr *gp =
130 			(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
131 	struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
132 	union scratch2_reg scratch2;
133 	union scratch4_reg scratch4;
134 	union scratch24_reg scratch24;
135 	union xm2cfga_reg xm2cfga;
136 	union xm2cfgd_reg xm2cfgd;
137 	union fbio_spare_reg fbio_spare;
138 
139 	/* get ram code that is used as index to array sdram_params in BCT */
140 	ram_code = (readl(&apb_misc->strapping_opt_a) >>
141 			  STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
142 	memcpy(&sdram,
143 	       (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
144 	       sizeof(sdram));
145 
146 	xm2cfga.word = readl(&gp->xm2cfga);
147 	xm2cfgd.word = readl(&gp->xm2cfgd);
148 
149 	scratch2.word = 0;
150 	scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
151 
152 	/* Get the memory PLL settings */
153 	{
154 		u32 divm, divn, divp, cpcon, lfcon;
155 
156 		if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
157 					&cpcon, &lfcon))
158 			return -1;
159 		scratch2.pllm_base_divm = divm;
160 		scratch2.pllm_base_divn = divn;
161 		scratch2.pllm_base_divp = divp;
162 		scratch2.pllm_misc_cpcon = cpcon;
163 		scratch2.pllm_misc_lfcon = lfcon;
164 	}
165 
166 	scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
167 	scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
168 	scratch2.memory_type = sdram.memory_type;
169 	writel(scratch2.word, &pmc->pmc_scratch2);
170 
171 	/* collect data from various sources for pmc_scratch4 */
172 	fbio_spare.word = readl(&emc->fbio_spare);
173 	scratch4.word = 0;
174 	scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
175 	scratch4.emc_clock_divider = sdram.emc_clock_divider;
176 	scratch4.pllm_stable_time = -1;
177 	scratch4.pllx_stable_time = -1;
178 	writel(scratch4.word, &pmc->pmc_scratch4);
179 
180 	/* collect various data from sdram for pmc_scratch24 */
181 	scratch24.word = 0;
182 	scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
183 	scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
184 	scratch24.warmboot_wait = sdram.warm_boot_wait;
185 	writel(scratch24.word, &pmc->pmc_scratch24);
186 
187 	return 0;
188 }
189 
190 static u32 get_major_version(void)
191 {
192 	u32 major_id;
193 	struct apb_misc_gp_ctlr *gp =
194 		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
195 
196 	major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
197 			HIDREV_MAJORPREV_SHIFT;
198 	return major_id;
199 }
200 
201 static int is_production_mode_fuse_set(struct fuse_regs *fuse)
202 {
203 	return readl(&fuse->production_mode);
204 }
205 
206 static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
207 {
208 	return readl(&fuse->security_mode);
209 }
210 
211 static int is_failure_analysis_mode(struct fuse_regs *fuse)
212 {
213 	return readl(&fuse->fa);
214 }
215 
216 static int ap20_is_odm_production_mode(void)
217 {
218 	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
219 
220 	if (!is_failure_analysis_mode(fuse) &&
221 	    is_odm_production_mode_fuse_set(fuse))
222 		return 1;
223 	else
224 		return 0;
225 }
226 
227 static int ap20_is_production_mode(void)
228 {
229 	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
230 
231 	if (get_major_version() == 0)
232 		return 1;
233 
234 	if (!is_failure_analysis_mode(fuse) &&
235 	    is_production_mode_fuse_set(fuse) &&
236 	    !is_odm_production_mode_fuse_set(fuse))
237 		return 1;
238 	else
239 		return 0;
240 }
241 
242 static enum fuse_operating_mode fuse_get_operation_mode(void)
243 {
244 	u32 chip_id;
245 	struct apb_misc_gp_ctlr *gp =
246 		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
247 
248 	chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
249 			HIDREV_CHIPID_SHIFT;
250 	if (chip_id == CHIPID_TEGRA20) {
251 		if (ap20_is_odm_production_mode()) {
252 			printf("!! odm_production_mode is not supported !!\n");
253 			return MODE_UNDEFINED;
254 		} else
255 			if (ap20_is_production_mode())
256 				return MODE_PRODUCTION;
257 			else
258 				return MODE_UNDEFINED;
259 	}
260 	return MODE_UNDEFINED;
261 }
262 
263 static void determine_crypto_options(int *is_encrypted, int *is_signed,
264 				     int *use_zero_key)
265 {
266 	switch (fuse_get_operation_mode()) {
267 	case MODE_PRODUCTION:
268 		*is_encrypted = 0;
269 		*is_signed = 1;
270 		*use_zero_key = 1;
271 		break;
272 	case MODE_UNDEFINED:
273 	default:
274 		*is_encrypted = 0;
275 		*is_signed = 0;
276 		*use_zero_key  = 0;
277 		break;
278 	}
279 }
280 
281 static int sign_wb_code(u32 start, u32 length, int use_zero_key)
282 {
283 	int err;
284 	u8 *source;		/* Pointer to source */
285 	u8 *hash;
286 
287 	/* Calculate AES block parameters. */
288 	source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
289 	length -= offsetof(struct wb_header, random_aes_block);
290 	hash = (u8 *)(start + offsetof(struct wb_header, hash));
291 	err = sign_data_block(source, length, hash);
292 
293 	return err;
294 }
295 
296 int warmboot_prepare_code(u32 seg_address, u32 seg_length)
297 {
298 	int err = 0;
299 	u32 length;			/* length of the signed/encrypt code */
300 	struct wb_header *dst_header;	/* Pointer to dest WB header */
301 	int is_encrypted;		/* Segment is encrypted */
302 	int is_signed;			/* Segment is signed */
303 	int use_zero_key;		/* Use key of all zeros */
304 
305 	/* Determine crypto options. */
306 	determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
307 
308 	/* Get the actual code limits. */
309 	length = roundup(((u32)wb_end - (u32)wb_start), 16);
310 
311 	/*
312 	 * The region specified by seg_address must be in SDRAM and must be
313 	 * nonzero in length.
314 	 */
315 	if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
316 		seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
317 		err = -EFAULT;
318 		goto fail;
319 	}
320 
321 	/* Things must be 16-byte aligned. */
322 	if ((seg_length & 0xF) || (seg_address & 0xF)) {
323 		err = -EINVAL;
324 		goto fail;
325 	}
326 
327 	/* Will the code fit? (destination includes wb_header + wb code) */
328 	if (seg_length < (length + sizeof(struct wb_header))) {
329 		err = -EINVAL;
330 		goto fail;
331 	}
332 
333 	dst_header = (struct wb_header *)seg_address;
334 	memset((char *)dst_header, 0, sizeof(struct wb_header));
335 
336 	/* Populate the random_aes_block as requested. */
337 	{
338 		u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
339 		u32 *end = (u32 *)(((u32)aes_block) +
340 				   sizeof(dst_header->random_aes_block));
341 
342 		do {
343 			*aes_block++ = 0;
344 		} while (aes_block < end);
345 	}
346 
347 	/* Populate the header. */
348 	dst_header->length_insecure = length + sizeof(struct wb_header);
349 	dst_header->length_secure = length + sizeof(struct wb_header);
350 	dst_header->destination = NV_WB_RUN_ADDRESS;
351 	dst_header->entry_point = NV_WB_RUN_ADDRESS;
352 	dst_header->code_length = length;
353 
354 	if (is_encrypted) {
355 		printf("!!!! Encryption is not supported !!!!\n");
356 		dst_header->length_insecure = 0;
357 		err = -EACCES;
358 		goto fail;
359 	} else
360 		/* copy the wb code directly following dst_header. */
361 		memcpy((char *)(dst_header+1), (char *)wb_start, length);
362 
363 	if (is_signed)
364 		err = sign_wb_code(seg_address, dst_header->length_insecure,
365 				   use_zero_key);
366 
367 fail:
368 	if (err)
369 		printf("Warning: warmboot code copy failed (error=%d)\n", err);
370 
371 	return err;
372 }
373