1 /*
2  * Copyright (C) 2013 Samsung Electronics
3  *
4  * Configuration settings for the SAMSUNG EXYNOS5 board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
11 
12 #define CONFIG_EXYNOS5			/* Exynos5 Family */
13 
14 #include "exynos-common.h"
15 
16 #define CONFIG_SYS_CACHELINE_SIZE	64
17 #define CONFIG_EXYNOS_SPL
18 
19 #ifdef FTRACE
20 #define CONFIG_TRACE
21 #define CONFIG_CMD_TRACE
22 #define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
23 #define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
24 #define CONFIG_TRACE_EARLY
25 #define CONFIG_TRACE_EARLY_ADDR		0x50000000
26 #endif
27 
28 /* Enable ACE acceleration for SHA1 and SHA256 */
29 #define CONFIG_EXYNOS_ACE_SHA
30 #define CONFIG_SHA_HW_ACCEL
31 
32 /* Power Down Modes */
33 #define S5P_CHECK_SLEEP			0x00000BAD
34 #define S5P_CHECK_DIDLE			0xBAD00000
35 #define S5P_CHECK_LPA			0xABAD0000
36 
37 /* Offset for inform registers */
38 #define INFORM0_OFFSET			0x800
39 #define INFORM1_OFFSET			0x804
40 #define INFORM2_OFFSET			0x808
41 #define INFORM3_OFFSET			0x80c
42 
43 /* select serial console configuration */
44 #define CONFIG_BAUDRATE			115200
45 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
46 #define CONFIG_SILENT_CONSOLE
47 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
48 #define CONFIG_CONSOLE_MUX
49 
50 #define CONFIG_CMD_HASH
51 
52 /* Thermal Management Unit */
53 #define CONFIG_EXYNOS_TMU
54 #define CONFIG_CMD_DTT
55 #define CONFIG_TMU_CMD_DTT
56 
57 /* MMC SPL */
58 #define COPY_BL2_FNPTR_ADDR	0x02020030
59 #define CONFIG_SUPPORT_EMMC_BOOT
60 
61 #define CONFIG_SPL_LIBCOMMON_SUPPORT
62 #define CONFIG_SPL_GPIO_SUPPORT
63 #define CONFIG_SPL_LIBGENERIC_SUPPORT
64 
65 /* specific .lds file */
66 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
67 
68 /* Boot Argument Buffer Size */
69 /* memtest works on */
70 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
71 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
72 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
73 
74 #define CONFIG_RD_LVL
75 
76 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
77 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
78 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
79 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
80 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
81 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
82 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
83 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
84 #define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
85 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
86 #define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
87 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
88 #define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
89 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
90 #define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
91 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
92 
93 #define CONFIG_SYS_MONITOR_BASE	0x00000000
94 
95 #define CONFIG_SYS_MMC_ENV_DEV		0
96 
97 #define CONFIG_SECURE_BL1_ONLY
98 
99 /* Secure FW size configuration */
100 #ifdef CONFIG_SECURE_BL1_ONLY
101 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
102 #else
103 #define CONFIG_SEC_FW_SIZE 0
104 #endif
105 
106 /* Configuration of BL1, BL2, ENV Blocks on mmc */
107 #define CONFIG_RES_BLOCK_SIZE	(512)
108 #define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
109 #define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
110 #define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
111 
112 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
113 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
114 
115 /* U-Boot copy size from boot Media to DRAM.*/
116 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
117 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
118 
119 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
120 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
121 
122 /* I2C */
123 #define CONFIG_SYS_I2C_S3C24X0
124 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
125 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
126 
127 /* SPI */
128 #ifdef CONFIG_SPI_FLASH
129 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
130 #define CONFIG_SF_DEFAULT_SPEED		50000000
131 #endif
132 
133 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
134 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
135 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
136 #define CONFIG_ENV_SPI_BUS	1
137 #define CONFIG_ENV_SPI_MAX_HZ	50000000
138 #endif
139 
140 /* Ethernet Controllor Driver */
141 #ifdef CONFIG_CMD_NET
142 #define CONFIG_SMC911X
143 #define CONFIG_SMC911X_BASE		0x5000000
144 #define CONFIG_SMC911X_16_BIT
145 #define CONFIG_ENV_SROM_BANK		1
146 #endif /*CONFIG_CMD_NET*/
147 
148 /* SHA hashing */
149 #define CONFIG_CMD_HASH
150 #define CONFIG_HASH_VERIFY
151 #define CONFIG_SHA1
152 #define CONFIG_SHA256
153 
154 /* Enable Time Command */
155 
156 /* USB */
157 #define CONFIG_USB_STORAGE
158 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
159 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
160 
161 #define CONFIG_USB_HOST_ETHER
162 #define CONFIG_USB_ETHER_ASIX
163 #define CONFIG_USB_ETHER_SMSC95XX
164 #define CONFIG_USB_ETHER_RTL8152
165 
166 /* USB boot mode */
167 #define CONFIG_USB_BOOTING
168 #define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
169 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
170 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
171 
172 #define BOOT_TARGET_DEVICES(func) \
173 	func(MMC, mmc, 1) \
174 	func(MMC, mmc, 0) \
175 	func(PXE, pxe, na) \
176 	func(DHCP, dhcp, na)
177 
178 #include <config_distro_bootcmd.h>
179 
180 #ifndef MEM_LAYOUT_ENV_SETTINGS
181 /* 2GB RAM, bootm size of 256M, load scripts after that */
182 #define MEM_LAYOUT_ENV_SETTINGS \
183 	"bootm_size=0x10000000\0" \
184 	"kernel_addr_r=0x42000000\0" \
185 	"fdt_addr_r=0x43000000\0" \
186 	"ramdisk_addr_r=0x43300000\0" \
187 	"scriptaddr=0x50000000\0" \
188 	"pxefile_addr_r=0x51000000\0"
189 #endif
190 
191 #ifndef EXYNOS_DEVICE_SETTINGS
192 #define EXYNOS_DEVICE_SETTINGS \
193 	"stdin=serial\0" \
194 	"stdout=serial\0" \
195 	"stderr=serial\0"
196 #endif
197 
198 #ifndef EXYNOS_FDTFILE_SETTING
199 #define EXYNOS_FDTFILE_SETTING
200 #endif
201 
202 #define CONFIG_EXTRA_ENV_SETTINGS \
203 	EXYNOS_DEVICE_SETTINGS \
204 	EXYNOS_FDTFILE_SETTING \
205 	MEM_LAYOUT_ENV_SETTINGS \
206 	BOOTENV
207 
208 #endif	/* __CONFIG_EXYNOS5_COMMON_H */
209