1 /* 2 * Copyright (c) 2012-2016 Toradex, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch-tegra/tegra_i2c.h> 10 #include "as3722_init.h" 11 12 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */ 13 14 void tegra_i2c_ll_write_addr(uint addr, uint config) 15 { 16 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 17 18 writel(addr, ®->cmd_addr0); 19 writel(config, ®->cnfg); 20 } 21 22 void tegra_i2c_ll_write_data(uint data, uint config) 23 { 24 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; 25 26 writel(data, ®->cmd_data1); 27 writel(config, ®->cnfg); 28 } 29 30 void pmic_enable_cpu_vdd(void) 31 { 32 debug("%s entry\n", __func__); 33 34 #ifdef AS3722_SD1VOLTAGE_DATA 35 /* Set up VDD_CORE, for boards where OTP is incorrect*/ 36 debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__); 37 /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */ 38 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 39 tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES); 40 /* 41 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 42 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES); 43 */ 44 udelay(10 * 1000); 45 #endif 46 47 debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); 48 /* 49 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. 50 * First set VDD to 1.0V, then enable the VDD regulator. 51 */ 52 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 53 tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES); 54 /* 55 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 56 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES); 57 */ 58 udelay(10 * 1000); 59 60 debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__); 61 /* 62 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. 63 * First set VDD to 1.0V, then enable the VDD regulator. 64 */ 65 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 66 tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES); 67 /* 68 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. 69 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES); 70 */ 71 udelay(10 * 1000); 72 73 debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__); 74 /* 75 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. 76 * First set VDD to 1.2V, then enable the VDD regulator. 77 */ 78 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 79 tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES); 80 /* 81 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. 82 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES); 83 */ 84 udelay(10 * 1000); 85 86 debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__); 87 /* 88 * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus. 89 * First set it to value closest to 3.3V, then enable the regulator 90 * 91 * NOTE: We do this early because doing it later seems to hose the CPU 92 * power rail/partition startup. Need to debug. 93 */ 94 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 95 tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES); 96 /* 97 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. 98 * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES); 99 */ 100 udelay(10 * 1000); 101 102 debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__); 103 /* 104 * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus. 105 * First set it to bypass 3.3V straight thru, then enable the regulator 106 * 107 * NOTE: We do this early because doing it later seems to hose the CPU 108 * power rail/partition startup. Need to debug. 109 */ 110 tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); 111 tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES); 112 /* 113 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. 114 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES); 115 */ 116 udelay(10 * 1000); 117 } 118