1 /*
2  * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
3  * Copyright (c) 2015 Google, Inc
4  * Copyright 2014 Rockchip Inc.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <clk.h>
11 #include <display.h>
12 #include <dm.h>
13 #include <dw_hdmi.h>
14 #include <edid.h>
15 #include <regmap.h>
16 #include <syscon.h>
17 #include <asm/gpio.h>
18 #include <asm/hardware.h>
19 #include <asm/io.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/hardware.h>
22 #include "rk_hdmi.h"
23 #include "rk_vop.h" /* for rk_vop_probe_regulators */
24 
25 static const struct hdmi_phy_config rockchip_phy_config[] = {
26 	{
27 		.mpixelclock = 74250000,
28 		.sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
29 	}, {
30 		.mpixelclock = 148500000,
31 		.sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
32 	}, {
33 		.mpixelclock = 297000000,
34 		.sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
35 	}, {
36 		.mpixelclock = 584000000,
37 		.sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
38 	}, {
39 		.mpixelclock = ~0ul,
40 		.sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
41 	}
42 };
43 
44 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
45 	{
46 		.mpixelclock = 40000000,
47 		.cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
48 	}, {
49 		.mpixelclock = 65000000,
50 		.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
51 	}, {
52 		.mpixelclock = 66000000,
53 		.cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
54 	}, {
55 		.mpixelclock = 83500000,
56 		.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
57 	}, {
58 		.mpixelclock = 146250000,
59 		.cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
60 	}, {
61 		.mpixelclock = 148500000,
62 		.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
63 	}, {
64 		.mpixelclock = 272000000,
65 		.cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
66 	}, {
67 		.mpixelclock = 340000000,
68 		.cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
69 	}, {
70 		.mpixelclock = ~0ul,
71 		.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
72 	}
73 };
74 
75 int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
76 {
77 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
78 
79 	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
80 }
81 
82 int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
83 {
84 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
85 	struct dw_hdmi *hdmi = &priv->hdmi;
86 
87 	hdmi->ioaddr = (ulong)devfdt_get_addr(dev);
88 	hdmi->mpll_cfg = rockchip_mpll_cfg;
89 	hdmi->phy_cfg = rockchip_phy_config;
90 
91 	/* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
92 
93 	hdmi->reg_io_width = 4;
94 	hdmi->phy_set = dw_hdmi_phy_cfg;
95 
96 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
97 
98 	return 0;
99 }
100 
101 void rk_hdmi_probe_regulators(struct udevice *dev,
102 			      const char * const *names, int cnt)
103 {
104 	rk_vop_probe_regulators(dev, names, cnt);
105 }
106 
107 int rk_hdmi_probe(struct udevice *dev)
108 {
109 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
110 	struct dw_hdmi *hdmi = &priv->hdmi;
111 	int ret;
112 
113 	ret = dw_hdmi_phy_wait_for_hpd(hdmi);
114 	if (ret < 0) {
115 		debug("hdmi can not get hpd signal\n");
116 		return -1;
117 	}
118 
119 	dw_hdmi_init(hdmi);
120 	dw_hdmi_phy_init(hdmi);
121 
122 	return 0;
123 }
124