1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <spl.h> 10 #include <asm/io.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/soc.h> 13 14 #include "high_speed_env_spec.h" 15 16 MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = { 17 /* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */ 18 { 19 /* PEX: Change of Slew Rate port0 */ 20 SERDES_UNIT_PEX, 0x0, 21 (0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21 22 }, { 23 /* PEX: Change PLL BW port0 */ 24 SERDES_UNIT_PEX, 0x0, 25 (0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219 26 }, { 27 /* SATA: Slew rate change port 0 */ 28 SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31 29 }, { 30 /* SATA: Slew rate change port 0 */ 31 SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928 32 }, { 33 /* SATA: Slew rate change port 0 */ 34 SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0 35 }, { 36 /* SATA: Slew rate change port 0 */ 37 SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5 38 }, { 39 /* SGMII: FFE setting Port0 */ 40 SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F 41 }, { 42 /* SGMII: SELMUP and SELMUF Port0 */ 43 SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA 44 }, { 45 /* SGMII: Amplitude new setting gen2 Port3 */ 46 SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C 47 }, { 48 /* QSGMII: Amplitude and slew rate change */ 49 SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58 50 }, { 51 /* QSGMII: SELMUP and SELMUF */ 52 SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF 53 }, { 54 /* QSGMII: 0x72e18 */ 55 SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC 56 }, { 57 /* Null terminated */ 58 SERDES_UNIT_UNCONNECTED, 0, 0 59 } 60 }; 61 62 MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = { 63 /* Z1B */ 64 {MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111, 65 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 66 0x0030, serdes_change_m_phy}, /* Default */ 67 {MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111, 68 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 69 0x0030, serdes_change_m_phy}, /* PEX module */ 70 /* Z1A */ 71 {MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000, 72 {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, 73 PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */ 74 {MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000, 75 {PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 76 0x0030, serdes_change_m_phy} /* PEX module - Z1A */ 77 }; 78 79 MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = { 80 /* A0 */ 81 {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111, 82 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 83 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */ 84 {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111, 85 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 86 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */ 87 {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111, 88 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 89 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */ 90 {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111, 91 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 92 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */ 93 {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111, 94 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 95 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */ 96 {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111, 97 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 98 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */ 99 }; 100 101 MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = { 102 {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111, 103 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 104 0x0030, serdes_change_m_phy}, /* Default */ 105 {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111, 106 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 107 0x00f4, serdes_change_m_phy}, /* Switch module */ 108 }; 109 110 MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = { 111 {MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000, 112 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 113 0x0010, serdes_change_m_phy}, /* CPU0 */ 114 {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000, 115 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 116 0x0010, serdes_change_m_phy} /* CPU1-3 */ 117 }; 118 119 MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = { 120 {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000, 121 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 122 0x0010, serdes_change_m_phy}, /* CPU0 */ 123 {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000, 124 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 125 0x0010, serdes_change_m_phy} /* CPU1-3 */ 126 }; 127 128 MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = { 129 {MV_PEX_END_POINT, 0x22321111, 0x00000000, 130 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 131 0x0010, serdes_change_m_phy} /* Default */ 132 }; 133 134 MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = { 135 {MV_PEX_END_POINT, 0x23321111, 0x00000000, 136 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 137 0x0010, serdes_change_m_phy} /* Default */ 138 }; 139 140 MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = { 141 {MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000, 142 {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED}, 143 0x0000, serdes_change_m_phy} /* No PEX in FPGA */ 144 }; 145 146 MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = { 147 {MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001, 148 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1}, 149 0x0030, serdes_change_m_phy} /* Default */ 150 }; 151 152 /* 153 * ARMADA-XP CUSTOMER BOARD 154 */ 155 MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = { 156 {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111, 157 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 158 0x00000030, serdes_change_m_phy}, /* Default */ 159 {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111, 160 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 161 0x00000030, serdes_change_m_phy}, /* Switch module */ 162 }; 163 164 MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = { 165 {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111, 166 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4}, 167 0x0030, serdes_change_m_phy} /* Default */ 168 }; 169 170 MV_BIN_SERDES_CFG *serdes_info_tbl[] = { 171 db88f78xx0_serdes_cfg, 172 rd78460_serdes_cfg, 173 db78X60pcac_serdes_cfg, 174 fpga88f78xx0_serdes_cfg, 175 db88f78xx0rev2_serdes_cfg, 176 rd78460nas_serdes_cfg, 177 db78X60amc_serdes_cfg, 178 db78X60pcacrev2_serdes_cfg, 179 rd78460server_rev2_serdes_cfg, 180 rd78460AXP_GP_serdes_cfg, 181 rd78460customer_serdes_cfg 182 }; 183 184 u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E }; 185 u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F }; 186