1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5329EVB_H 15 #define _M5329EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29 /* Command line configuration */ 30 #include <config_cmd_default.h> 31 32 #define CONFIG_CMD_CACHE 33 #define CONFIG_CMD_DATE 34 #define CONFIG_CMD_ELF 35 #define CONFIG_CMD_FLASH 36 #define CONFIG_CMD_I2C 37 #define CONFIG_CMD_MEMORY 38 #define CONFIG_CMD_MISC 39 #define CONFIG_CMD_MII 40 #define CONFIG_CMD_NET 41 #define CONFIG_CMD_PING 42 #define CONFIG_CMD_REGINFO 43 44 #ifdef CONFIG_NANDFLASH_SIZE 45 # define CONFIG_CMD_NAND 46 #endif 47 48 #define CONFIG_SYS_UNIFY_CACHE 49 50 #define CONFIG_MCFFEC 51 #ifdef CONFIG_MCFFEC 52 # define CONFIG_MII 1 53 # define CONFIG_MII_INIT 1 54 # define CONFIG_SYS_DISCOVER_PHY 55 # define CONFIG_SYS_RX_ETH_BUFFER 8 56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57 58 # define CONFIG_SYS_FEC0_PINMUX 0 59 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 60 # define MCFFEC_TOUT_LOOP 50000 61 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 62 # ifndef CONFIG_SYS_DISCOVER_PHY 63 # define FECDUPLEX FULL 64 # define FECSPEED _100BASET 65 # else 66 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 68 # endif 69 # endif /* CONFIG_SYS_DISCOVER_PHY */ 70 #endif 71 72 #define CONFIG_MCFRTC 73 #undef RTC_DEBUG 74 75 /* Timer */ 76 #define CONFIG_MCFTMR 77 #undef CONFIG_MCFPIT 78 79 /* I2C */ 80 #define CONFIG_SYS_I2C 81 #define CONFIG_SYS_I2C_FSL 82 #define CONFIG_SYS_FSL_I2C_SPEED 80000 83 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 84 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 85 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 86 87 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 88 #define CONFIG_UDP_CHECKSUM 89 90 #ifdef CONFIG_MCFFEC 91 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 92 # define CONFIG_IPADDR 192.162.1.2 93 # define CONFIG_NETMASK 255.255.255.0 94 # define CONFIG_SERVERIP 192.162.1.1 95 # define CONFIG_GATEWAYIP 192.162.1.1 96 # define CONFIG_OVERWRITE_ETHADDR_ONCE 97 #endif /* FEC_ENET */ 98 99 #define CONFIG_HOSTNAME M5329EVB 100 #define CONFIG_EXTRA_ENV_SETTINGS \ 101 "netdev=eth0\0" \ 102 "loadaddr=40010000\0" \ 103 "u-boot=u-boot.bin\0" \ 104 "load=tftp ${loadaddr) ${u-boot}\0" \ 105 "upd=run load; run prog\0" \ 106 "prog=prot off 0 3ffff;" \ 107 "era 0 3ffff;" \ 108 "cp.b ${loadaddr} 0 ${filesize};" \ 109 "save\0" \ 110 "" 111 112 #define CONFIG_PRAM 512 /* 512 KB */ 113 #define CONFIG_SYS_PROMPT "-> " 114 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 115 116 #ifdef CONFIG_CMD_KGDB 117 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 118 #else 119 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 120 #endif 121 122 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 123 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 124 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 125 #define CONFIG_SYS_LOAD_ADDR 0x40010000 126 127 #define CONFIG_SYS_CLK 80000000 128 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 129 130 #define CONFIG_SYS_MBAR 0xFC000000 131 132 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 133 134 /* 135 * Low Level Configuration Settings 136 * (address mappings, register initial values, etc.) 137 * You should know what you are doing if you make changes here. 138 */ 139 /*----------------------------------------------------------------------- 140 * Definitions for initial stack pointer and data area (in DPRAM) 141 */ 142 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 143 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 144 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 145 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 147 148 /*----------------------------------------------------------------------- 149 * Start addresses for the final memory configuration 150 * (Set up by the startup code) 151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 152 */ 153 #define CONFIG_SYS_SDRAM_BASE 0x40000000 154 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 155 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 156 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 157 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 158 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 159 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 160 161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 162 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 163 164 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 165 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 166 167 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 168 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 169 170 /* 171 * For booting Linux, the board info and command line data 172 * have to be in the first 8 MB of memory, since this is 173 * the maximum mapped by the Linux kernel during initialization ?? 174 */ 175 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 176 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 177 178 /*----------------------------------------------------------------------- 179 * FLASH organization 180 */ 181 #define CONFIG_SYS_FLASH_CFI 182 #ifdef CONFIG_SYS_FLASH_CFI 183 # define CONFIG_FLASH_CFI_DRIVER 1 184 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 185 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 186 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 187 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 188 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 189 #endif 190 191 #ifdef CONFIG_NANDFLASH_SIZE 192 # define CONFIG_SYS_MAX_NAND_DEVICE 1 193 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 194 # define CONFIG_SYS_NAND_SIZE 1 195 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 196 # define NAND_ALLOW_ERASE_ALL 1 197 # define CONFIG_JFFS2_NAND 1 198 # define CONFIG_JFFS2_DEV "nand0" 199 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 200 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 201 #endif 202 203 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 204 205 /* Configuration for environment 206 * Environment is embedded in u-boot in the second sector of the flash 207 */ 208 #define CONFIG_ENV_OFFSET 0x4000 209 #define CONFIG_ENV_SECT_SIZE 0x2000 210 #define CONFIG_ENV_IS_IN_FLASH 1 211 212 #define LDS_BOARD_TEXT \ 213 . = DEFINED(env_offset) ? env_offset : .; \ 214 common/env_embedded.o (.text*); 215 216 /*----------------------------------------------------------------------- 217 * Cache Configuration 218 */ 219 #define CONFIG_SYS_CACHELINE_SIZE 16 220 221 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 222 CONFIG_SYS_INIT_RAM_SIZE - 8) 223 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 224 CONFIG_SYS_INIT_RAM_SIZE - 4) 225 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 226 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 227 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 228 CF_ACR_EN | CF_ACR_SM_ALL) 229 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 230 CF_CACR_DCM_P) 231 232 /*----------------------------------------------------------------------- 233 * Chipselect bank definitions 234 */ 235 /* 236 * CS0 - NOR Flash 1, 2, 4, or 8MB 237 * CS1 - CompactFlash and registers 238 * CS2 - NAND Flash 16, 32, or 64MB 239 * CS3 - Available 240 * CS4 - Available 241 * CS5 - Available 242 */ 243 #define CONFIG_SYS_CS0_BASE 0 244 #define CONFIG_SYS_CS0_MASK 0x007f0001 245 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 246 247 #define CONFIG_SYS_CS1_BASE 0x10000000 248 #define CONFIG_SYS_CS1_MASK 0x001f0001 249 #define CONFIG_SYS_CS1_CTRL 0x002A3780 250 251 #ifdef CONFIG_NANDFLASH_SIZE 252 #define CONFIG_SYS_CS2_BASE 0x20000000 253 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 254 #define CONFIG_SYS_CS2_CTRL 0x00001f60 255 #endif 256 257 #endif /* _M5329EVB_H */ 258