1 /*
2  * This header provides Tegra210-specific constants for binding
3  * nvidia,tegra210-car.
4  */
5 
6 #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
7 #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
8 
9 /* 0 */
10 /* 1 */
11 /* 2 */
12 #define TEGRA210_CLK_ISPB 3
13 #define TEGRA210_CLK_RTC 4
14 #define TEGRA210_CLK_TIMER 5
15 #define TEGRA210_CLK_UARTA 6
16 /* 7 (register bit affects uartb and vfir) */
17 /* 8 */
18 #define TEGRA210_CLK_SDMMC2 9
19 /* 10 (register bit affects spdif_in and spdif_out) */
20 #define TEGRA210_CLK_I2S1 11
21 #define TEGRA210_CLK_I2C1 12
22 /* 13 */
23 #define TEGRA210_CLK_SDMMC1 14
24 #define TEGRA210_CLK_SDMMC4 15
25 /* 16 */
26 #define TEGRA210_CLK_PWM 17
27 #define TEGRA210_CLK_I2S2 18
28 /* 20 (register bit affects vi and vi_sensor) */
29 /* 21 */
30 #define TEGRA210_CLK_USBD 22
31 #define TEGRA210_CLK_ISP 23
32 /* 26 */
33 /* 25 */
34 #define TEGRA210_CLK_DISP2 26
35 #define TEGRA210_CLK_DISP1 27
36 #define TEGRA210_CLK_HOST1X 28
37 #define TEGRA210_CLK_VCP 29
38 #define TEGRA210_CLK_I2S0 30
39 /* 31 */
40 
41 #define TEGRA210_CLK_MC 32
42 /* 33 */
43 #define TEGRA210_CLK_APBDMA 34
44 /* 35 */
45 #define TEGRA210_CLK_KBC 36
46 /* 37 */
47 /* 38 */
48 /* 39 (register bit affects fuse and fuse_burn) */
49 #define TEGRA210_CLK_KFUSE 40
50 #define TEGRA210_CLK_SBC1 41
51 #define TEGRA210_CLK_NOR 42
52 /* 43 */
53 #define TEGRA210_CLK_SBC2 44
54 /* 45 */
55 #define TEGRA210_CLK_SBC3 46
56 #define TEGRA210_CLK_I2C5 47
57 #define TEGRA210_CLK_DSIA 48
58 /* 49 */
59 #define TEGRA210_CLK_MIPI 50
60 #define TEGRA210_CLK_HDMI 51
61 #define TEGRA210_CLK_CSI 52
62 /* 53 */
63 #define TEGRA210_CLK_I2C2 54
64 #define TEGRA210_CLK_UARTC 55
65 #define TEGRA210_CLK_MIPI_CAL 56
66 #define TEGRA210_CLK_EMC 57
67 #define TEGRA210_CLK_USB2 58
68 #define TEGRA210_CLK_USB3 59
69 /* 60 */
70 #define TEGRA210_CLK_VDE 61
71 #define TEGRA210_CLK_BSEA 62
72 #define TEGRA210_CLK_BSEV 63
73 
74 /* 64 */
75 #define TEGRA210_CLK_UARTD 65
76 /* 66 */
77 #define TEGRA210_CLK_I2C3 67
78 #define TEGRA210_CLK_SBC4 68
79 #define TEGRA210_CLK_SDMMC3 69
80 #define TEGRA210_CLK_PCIE 70
81 #define TEGRA210_CLK_OWR 71
82 #define TEGRA210_CLK_AFI 72
83 #define TEGRA210_CLK_CSITE 73
84 /* 74 */
85 /* 75 */
86 #define TEGRA210_CLK_LA 76
87 #define TEGRA210_CLK_TRACE 77
88 #define TEGRA210_CLK_SOC_THERM 78
89 #define TEGRA210_CLK_DTV 79
90 /* 80 */
91 #define TEGRA210_CLK_I2CSLOW 81
92 #define TEGRA210_CLK_DSIB 82
93 #define TEGRA210_CLK_TSEC 83
94 /* 84 */
95 /* 85 */
96 /* 86 */
97 /* 87 */
98 /* 88 */
99 #define TEGRA210_CLK_XUSB_HOST 89
100 /* 90 */
101 #define TEGRA210_CLK_MSENC 91
102 #define TEGRA210_CLK_CSUS 92
103 /* 93 */
104 /* 94 */
105 /* 95 (bit affects xusb_dev and xusb_dev_src) */
106 
107 /* 96 */
108 /* 97 */
109 /* 98 */
110 #define TEGRA210_CLK_MSELECT 99
111 #define TEGRA210_CLK_TSENSOR 100
112 #define TEGRA210_CLK_I2S3 101
113 #define TEGRA210_CLK_I2S4 102
114 #define TEGRA210_CLK_I2C4 103
115 #define TEGRA210_CLK_SBC5 104
116 #define TEGRA210_CLK_SBC6 105
117 #define TEGRA210_CLK_D_AUDIO 106
118 #define TEGRA210_CLK_APBIF 107
119 #define TEGRA210_CLK_DAM0 108
120 #define TEGRA210_CLK_DAM1 109
121 #define TEGRA210_CLK_DAM2 110
122 #define TEGRA210_CLK_HDA2CODEC_2X 111
123 /* 112 */
124 #define TEGRA210_CLK_AUDIO0_2X 113
125 #define TEGRA210_CLK_AUDIO1_2X 114
126 #define TEGRA210_CLK_AUDIO2_2X 115
127 #define TEGRA210_CLK_AUDIO3_2X 116
128 #define TEGRA210_CLK_AUDIO4_2X 117
129 #define TEGRA210_CLK_SPDIF_2X 118
130 #define TEGRA210_CLK_ACTMON 119
131 #define TEGRA210_CLK_EXTERN1 120
132 #define TEGRA210_CLK_EXTERN2 121
133 #define TEGRA210_CLK_EXTERN3 122
134 #define TEGRA210_CLK_SATA_OOB 123
135 #define TEGRA210_CLK_SATA 124
136 #define TEGRA210_CLK_HDA 125
137 /* 126 */
138 #define TEGRA210_CLK_SE 127
139 
140 #define TEGRA210_CLK_HDA2HDMI 128
141 #define TEGRA210_CLK_SATA_COLD 129
142 /* 130 */
143 /* 131 */
144 /* 132 */
145 /* 133 */
146 /* 134 */
147 /* 135 */
148 /* 136 */
149 /* 137 */
150 /* 138 */
151 /* 139 */
152 /* 140 */
153 /* 141 */
154 /* 142 */
155 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
156 /*      xusb_host_src and xusb_ss_src) */
157 #define TEGRA210_CLK_CILAB 144
158 #define TEGRA210_CLK_CILCD 145
159 #define TEGRA210_CLK_CILE 146
160 #define TEGRA210_CLK_DSIALP 147
161 #define TEGRA210_CLK_DSIBLP 148
162 #define TEGRA210_CLK_ENTROPY 149
163 #define TEGRA210_CLK_DDS 150
164 /* 151 */
165 #define TEGRA210_CLK_DP2 152
166 #define TEGRA210_CLK_AMX 153
167 #define TEGRA210_CLK_ADX 154
168 /* 155 (bit affects dfll_ref and dfll_soc) */
169 #define TEGRA210_CLK_XUSB_SS 156
170 /* 157 */
171 /* 158 */
172 /* 159 */
173 
174 /* 160 */
175 /* 161 */
176 /* 162 */
177 /* 163 */
178 /* 164 */
179 /* 165 */
180 #define TEGRA210_CLK_I2C6 166
181 /* 167 */
182 /* 168 */
183 /* 169 */
184 /* 170 */
185 #define TEGRA210_CLK_VIM2_CLK 171
186 /* 172 */
187 /* 173 */
188 /* 174 */
189 /* 175 */
190 #define TEGRA210_CLK_HDMI_AUDIO 176
191 #define TEGRA210_CLK_CLK72MHZ 177
192 #define TEGRA210_CLK_VIC03 178
193 /* 179 */
194 #define TEGRA210_CLK_ADX1 180
195 #define TEGRA210_CLK_DPAUX 181
196 #define TEGRA210_CLK_SOR0 182
197 /* 183 */
198 #define TEGRA210_CLK_GPU 184
199 #define TEGRA210_CLK_AMX1 185
200 /* 186 */
201 /* 187 */
202 /* 188 */
203 /* 189 */
204 /* 190 */
205 /* 191 */
206 #define TEGRA210_CLK_UARTB 192
207 #define TEGRA210_CLK_VFIR 193
208 #define TEGRA210_CLK_SPDIF_IN 194
209 #define TEGRA210_CLK_SPDIF_OUT 195
210 #define TEGRA210_CLK_VI 196
211 #define TEGRA210_CLK_VI_SENSOR 197
212 #define TEGRA210_CLK_FUSE 198
213 #define TEGRA210_CLK_FUSE_BURN 199
214 #define TEGRA210_CLK_CLK_32K 200
215 #define TEGRA210_CLK_CLK_M 201
216 #define TEGRA210_CLK_CLK_M_DIV2 202
217 #define TEGRA210_CLK_CLK_M_DIV4 203
218 #define TEGRA210_CLK_PLL_REF 204
219 #define TEGRA210_CLK_PLL_C 205
220 #define TEGRA210_CLK_PLL_C_OUT1 206
221 #define TEGRA210_CLK_PLL_C2 207
222 #define TEGRA210_CLK_PLL_C3 208
223 #define TEGRA210_CLK_PLL_M 209
224 #define TEGRA210_CLK_PLL_M_OUT1 210
225 #define TEGRA210_CLK_PLL_P 211
226 #define TEGRA210_CLK_PLL_P_OUT1 212
227 #define TEGRA210_CLK_PLL_P_OUT2 213
228 #define TEGRA210_CLK_PLL_P_OUT3 214
229 #define TEGRA210_CLK_PLL_P_OUT4 215
230 #define TEGRA210_CLK_PLL_A 216
231 #define TEGRA210_CLK_PLL_A_OUT0 217
232 #define TEGRA210_CLK_PLL_D 218
233 #define TEGRA210_CLK_PLL_D_OUT0 219
234 #define TEGRA210_CLK_PLL_D2 220
235 #define TEGRA210_CLK_PLL_D2_OUT0 221
236 #define TEGRA210_CLK_PLL_U 222
237 #define TEGRA210_CLK_PLL_U_480M 223
238 
239 #define TEGRA210_CLK_PLL_U_60M 224
240 #define TEGRA210_CLK_PLL_U_48M 225
241 #define TEGRA210_CLK_PLL_U_12M 226
242 /* 227 */
243 /* 228 */
244 #define TEGRA210_CLK_PLL_RE_VCO 229
245 #define TEGRA210_CLK_PLL_RE_OUT 230
246 #define TEGRA210_CLK_PLL_E 231
247 #define TEGRA210_CLK_SPDIF_IN_SYNC 232
248 #define TEGRA210_CLK_I2S0_SYNC 233
249 #define TEGRA210_CLK_I2S1_SYNC 234
250 #define TEGRA210_CLK_I2S2_SYNC 235
251 #define TEGRA210_CLK_I2S3_SYNC 236
252 #define TEGRA210_CLK_I2S4_SYNC 237
253 #define TEGRA210_CLK_VIMCLK_SYNC 238
254 #define TEGRA210_CLK_AUDIO0 239
255 #define TEGRA210_CLK_AUDIO1 240
256 #define TEGRA210_CLK_AUDIO2 241
257 #define TEGRA210_CLK_AUDIO3 242
258 #define TEGRA210_CLK_AUDIO4 243
259 #define TEGRA210_CLK_SPDIF 244
260 #define TEGRA210_CLK_CLK_OUT_1 245
261 #define TEGRA210_CLK_CLK_OUT_2 246
262 #define TEGRA210_CLK_CLK_OUT_3 247
263 #define TEGRA210_CLK_BLINK 248
264 /* 249 */
265 /* 250 */
266 /* 251 */
267 #define TEGRA210_CLK_XUSB_HOST_SRC 252
268 #define TEGRA210_CLK_XUSB_FALCON_SRC 253
269 #define TEGRA210_CLK_XUSB_FS_SRC 254
270 #define TEGRA210_CLK_XUSB_SS_SRC 255
271 
272 #define TEGRA210_CLK_XUSB_DEV_SRC 256
273 #define TEGRA210_CLK_XUSB_DEV 257
274 #define TEGRA210_CLK_XUSB_HS_SRC 258
275 #define TEGRA210_CLK_SCLK 259
276 #define TEGRA210_CLK_HCLK 260
277 #define TEGRA210_CLK_PCLK 261
278 /* 262 */
279 /* 263 */
280 #define TEGRA210_CLK_DFLL_REF 264
281 #define TEGRA210_CLK_DFLL_SOC 265
282 #define TEGRA210_CLK_VI_SENSOR2 266
283 #define TEGRA210_CLK_PLL_P_OUT5 267
284 #define TEGRA210_CLK_CML0 268
285 #define TEGRA210_CLK_CML1 269
286 #define TEGRA210_CLK_PLL_C4 270
287 #define TEGRA210_CLK_PLL_DP 271
288 #define TEGRA210_CLK_PLL_E_MUX 272
289 #define TEGRA210_CLK_PLLD_DSI 273
290 /* 274 */
291 /* 275 */
292 /* 276 */
293 /* 277 */
294 /* 278 */
295 /* 279 */
296 /* 280 */
297 /* 281 */
298 /* 282 */
299 /* 283 */
300 /* 284 */
301 /* 285 */
302 /* 286 */
303 /* 287 */
304 
305 /* 288 */
306 /* 289 */
307 /* 290 */
308 /* 291 */
309 /* 292 */
310 /* 293 */
311 /* 294 */
312 /* 295 */
313 /* 296 */
314 /* 297 */
315 /* 298 */
316 /* 299 */
317 #define TEGRA210_CLK_AUDIO0_MUX 300
318 #define TEGRA210_CLK_AUDIO1_MUX 301
319 #define TEGRA210_CLK_AUDIO2_MUX 302
320 #define TEGRA210_CLK_AUDIO3_MUX 303
321 #define TEGRA210_CLK_AUDIO4_MUX 304
322 #define TEGRA210_CLK_SPDIF_MUX 305
323 #define TEGRA210_CLK_CLK_OUT_1_MUX 306
324 #define TEGRA210_CLK_CLK_OUT_2_MUX 307
325 #define TEGRA210_CLK_CLK_OUT_3_MUX 308
326 /* 309 */
327 /* 310 */
328 #define TEGRA210_CLK_SOR0_LVDS 311
329 #define TEGRA210_CLK_XUSB_SS_DIV2 312
330 
331 #define TEGRA210_CLK_PLL_M_UD 313
332 #define TEGRA210_CLK_PLL_C_UD 314
333 
334 #define TEGRA210_CLK_PLL_X		227
335 #define TEGRA210_CLK_PLL_X_OUT0		228
336 
337 #define TEGRA210_CLK_CCLK_G		262
338 #define TEGRA210_CLK_CCLK_LP		263
339 
340 #define TEGRA210_CLK_CLK_MAX		315
341 
342 #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
343