1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #ifndef _ASM_ARCH_GRF_RK322X_H
7 #define _ASM_ARCH_GRF_RK322X_H
8 
9 #include <common.h>
10 
11 struct rk322x_grf {
12 	unsigned int gpio0a_iomux;
13 	unsigned int gpio0b_iomux;
14 	unsigned int gpio0c_iomux;
15 	unsigned int gpio0d_iomux;
16 
17 	unsigned int gpio1a_iomux;
18 	unsigned int gpio1b_iomux;
19 	unsigned int gpio1c_iomux;
20 	unsigned int gpio1d_iomux;
21 
22 	unsigned int gpio2a_iomux;
23 	unsigned int gpio2b_iomux;
24 	unsigned int gpio2c_iomux;
25 	unsigned int gpio2d_iomux;
26 
27 	unsigned int gpio3a_iomux;
28 	unsigned int gpio3b_iomux;
29 	unsigned int gpio3c_iomux;
30 	unsigned int gpio3d_iomux;
31 
32 	unsigned int reserved1[4];
33 	unsigned int con_iomux;
34 	unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
35 	unsigned int gpio0_p[4];
36 	unsigned int gpio1_p[4];
37 	unsigned int gpio2_p[4];
38 	unsigned int gpio3_p[4];
39 	unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
40 	unsigned int gpio0_e[4];
41 	unsigned int gpio1_e[4];
42 	unsigned int gpio2_e[4];
43 	unsigned int gpio3_e[4];
44 	unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
45 	unsigned int soc_con[7];
46 	unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
47 	unsigned int soc_status[3];
48 	unsigned int chip_id;
49 	unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
50 	unsigned int cpu_con[4];
51 	unsigned int reserved7[4];
52 	unsigned int cpu_status[2];
53 	unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
54 	unsigned int os_reg[8];
55 	unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
56 	unsigned int ddrc_stat;
57 	unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
58 	unsigned int sig_detect_con[2];
59 	unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
60 	unsigned int sig_detect_status[2];
61 	unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
62 	unsigned int sig_detect_clr[2];
63 	unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
64 	unsigned int emmc_det;
65 	unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
66 	unsigned int host0_con[3];
67 	unsigned int reserved15;
68 	unsigned int host1_con[3];
69 	unsigned int reserved16;
70 	unsigned int host2_con[3];
71 	unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
72 	unsigned int usbphy0_con[27];
73 	unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
74 	unsigned int usbphy1_con[27];
75 	unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
76 	unsigned int otg_con0;
77 	unsigned int uoc_status0;
78 	unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
79 	unsigned int mac_con[2];
80 	unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
81 	unsigned int macphy_con[4];
82 	unsigned int macphy_status;
83 };
84 check_member(rk322x_grf, ddrc_stat, 0x604);
85 
86 struct rk322x_sgrf {
87 	unsigned int soc_con[11];
88 	unsigned int busdmac_con[4];
89 };
90 
91 /* GRF_GPIO0A_IOMUX */
92 enum {
93 	GPIO0A7_SHIFT		= 14,
94 	GPIO0A7_MASK		= 3 << GPIO0A7_SHIFT,
95 	GPIO0A7_GPIO		= 0,
96 	GPIO0A7_I2C3_SDA,
97 	GPIO0A7_HDMI_DDCSDA,
98 
99 	GPIO0A6_SHIFT		= 12,
100 	GPIO0A6_MASK		= 3 << GPIO0A6_SHIFT,
101 	GPIO0A6_GPIO		= 0,
102 	GPIO0A6_I2C3_SCL,
103 	GPIO0A6_HDMI_DDCSCL,
104 
105 	GPIO0A3_SHIFT		= 6,
106 	GPIO0A3_MASK		= 3 << GPIO0A3_SHIFT,
107 	GPIO0A3_GPIO		= 0,
108 	GPIO0A3_I2C1_SDA,
109 	GPIO0A3_SDIO_CMD,
110 
111 	GPIO0A2_SHIFT		= 4,
112 	GPIO0A2_MASK		= 3 << GPIO0A2_SHIFT,
113 	GPIO0A2_GPIO		= 0,
114 	GPIO0A2_I2C1_SCL,
115 
116 	GPIO0A1_SHIFT		= 2,
117 	GPIO0A1_MASK		= 3 << GPIO0A1_SHIFT,
118 	GPIO0A1_GPIO		= 0,
119 	GPIO0A1_I2C0_SDA,
120 
121 	GPIO0A0_SHIFT		= 0,
122 	GPIO0A0_MASK		= 3 << GPIO0A0_SHIFT,
123 	GPIO0A0_GPIO		= 0,
124 	GPIO0A0_I2C0_SCL,
125 };
126 
127 /* GRF_GPIO0B_IOMUX */
128 enum {
129 	GPIO0B7_SHIFT		= 14,
130 	GPIO0B7_MASK		= 3 << GPIO0B7_SHIFT,
131 	GPIO0B7_GPIO		= 0,
132 	GPIO0B7_HDMI_HDP,
133 
134 	GPIO0B6_SHIFT		= 12,
135 	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
136 	GPIO0B6_GPIO		= 0,
137 	GPIO0B6_I2S_SDI,
138 	GPIO0B6_SPI_CSN0,
139 
140 	GPIO0B5_SHIFT		= 10,
141 	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
142 	GPIO0B5_GPIO		= 0,
143 	GPIO0B5_I2S_SDO,
144 	GPIO0B5_SPI_RXD,
145 
146 	GPIO0B3_SHIFT		= 6,
147 	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
148 	GPIO0B3_GPIO		= 0,
149 	GPIO0B3_I2S1_LRCKRX,
150 	GPIO0B3_SPI_TXD,
151 
152 	GPIO0B1_SHIFT		= 2,
153 	GPIO0B1_MASK		= 3 << GPIO0B1_SHIFT,
154 	GPIO0B1_GPIO		= 0,
155 	GPIO0B1_I2S_SCLK,
156 	GPIO0B1_SPI_CLK,
157 
158 	GPIO0B0_SHIFT		= 0,
159 	GPIO0B0_MASK		= 3,
160 	GPIO0B0_GPIO		= 0,
161 	GPIO0B0_I2S_MCLK,
162 };
163 
164 /* GRF_GPIO0C_IOMUX */
165 enum {
166 	GPIO0C4_SHIFT		= 8,
167 	GPIO0C4_MASK		= 3 << GPIO0C4_SHIFT,
168 	GPIO0C4_GPIO		= 0,
169 	GPIO0C4_HDMI_CECSDA,
170 
171 	GPIO0C1_SHIFT		= 2,
172 	GPIO0C1_MASK		= 3 << GPIO0C1_SHIFT,
173 	GPIO0C1_GPIO		= 0,
174 	GPIO0C1_UART0_RSTN,
175 	GPIO0C1_CLK_OUT1,
176 };
177 
178 /* GRF_GPIO0D_IOMUX */
179 enum {
180 	GPIO0D6_SHIFT		= 12,
181 	GPIO0D6_MASK		= 3 << GPIO0D6_SHIFT,
182 	GPIO0D6_GPIO		= 0,
183 	GPIO0D6_SDIO_PWREN,
184 	GPIO0D6_PWM11,
185 
186 
187 	GPIO0D4_SHIFT		= 8,
188 	GPIO0D4_MASK		= 3 << GPIO0D4_SHIFT,
189 	GPIO0D4_GPIO		= 0,
190 	GPIO0D4_PWM2,
191 
192 	GPIO0D3_SHIFT		= 6,
193 	GPIO0D3_MASK		= 3 << GPIO0D3_SHIFT,
194 	GPIO0D3_GPIO		= 0,
195 	GPIO0D3_PWM1,
196 
197 	GPIO0D2_SHIFT		= 4,
198 	GPIO0D2_MASK		= 3 << GPIO0D2_SHIFT,
199 	GPIO0D2_GPIO		= 0,
200 	GPIO0D2_PWM0,
201 };
202 
203 /* GRF_GPIO1A_IOMUX */
204 enum {
205 	GPIO1A7_SHIFT		= 14,
206 	GPIO1A7_MASK		= 1,
207 	GPIO1A7_GPIO		= 0,
208 	GPIO1A7_SDMMC_WRPRT,
209 };
210 
211 /* GRF_GPIO1B_IOMUX */
212 enum {
213 	GPIO1B7_SHIFT		= 14,
214 	GPIO1B7_MASK		= 3 << GPIO1B7_SHIFT,
215 	GPIO1B7_GPIO		= 0,
216 	GPIO1B7_SDMMC_CMD,
217 
218 	GPIO1B6_SHIFT		= 12,
219 	GPIO1B6_MASK		= 3 << GPIO1B6_SHIFT,
220 	GPIO1B6_GPIO		= 0,
221 	GPIO1B6_SDMMC_PWREN,
222 
223 	GPIO1B4_SHIFT		= 8,
224 	GPIO1B4_MASK		= 3 << GPIO1B4_SHIFT,
225 	GPIO1B4_GPIO		= 0,
226 	GPIO1B4_SPI_CSN1,
227 	GPIO1B4_PWM12,
228 
229 	GPIO1B3_SHIFT		= 6,
230 	GPIO1B3_MASK		= 3 << GPIO1B3_SHIFT,
231 	GPIO1B3_GPIO		= 0,
232 	GPIO1B3_UART1_RSTN,
233 	GPIO1B3_PWM13,
234 
235 	GPIO1B2_SHIFT		= 4,
236 	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
237 	GPIO1B2_GPIO		= 0,
238 	GPIO1B2_UART1_SIN,
239 	GPIO1B2_UART21_SIN,
240 
241 	GPIO1B1_SHIFT		= 2,
242 	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
243 	GPIO1B1_GPIO		= 0,
244 	GPIO1B1_UART1_SOUT,
245 	GPIO1B1_UART21_SOUT,
246 };
247 
248 /* GRF_GPIO1C_IOMUX */
249 enum {
250 	GPIO1C7_SHIFT		= 14,
251 	GPIO1C7_MASK		= 3 << GPIO1C7_SHIFT,
252 	GPIO1C7_GPIO		= 0,
253 	GPIO1C7_NAND_CS3,
254 	GPIO1C7_EMMC_RSTNOUT,
255 
256 	GPIO1C6_SHIFT		= 12,
257 	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
258 	GPIO1C6_GPIO		= 0,
259 	GPIO1C6_NAND_CS2,
260 	GPIO1C6_EMMC_CMD,
261 
262 
263 	GPIO1C5_SHIFT		= 10,
264 	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
265 	GPIO1C5_GPIO		= 0,
266 	GPIO1C5_SDMMC_D3,
267 	GPIO1C5_JTAG_TMS,
268 
269 	GPIO1C4_SHIFT		= 8,
270 	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
271 	GPIO1C4_GPIO		= 0,
272 	GPIO1C4_SDMMC_D2,
273 	GPIO1C4_JTAG_TCK,
274 
275 	GPIO1C3_SHIFT		= 6,
276 	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
277 	GPIO1C3_GPIO		= 0,
278 	GPIO1C3_SDMMC_D1,
279 	GPIO1C3_UART2_SIN,
280 
281 	GPIO1C2_SHIFT		= 4,
282 	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT ,
283 	GPIO1C2_GPIO		= 0,
284 	GPIO1C2_SDMMC_D0,
285 	GPIO1C2_UART2_SOUT,
286 
287 	GPIO1C1_SHIFT		= 2,
288 	GPIO1C1_MASK		= 3 << GPIO1C1_SHIFT,
289 	GPIO1C1_GPIO		= 0,
290 	GPIO1C1_SDMMC_DETN,
291 
292 	GPIO1C0_SHIFT		= 0,
293 	GPIO1C0_MASK		= 3 << GPIO1C0_SHIFT,
294 	GPIO1C0_GPIO		= 0,
295 	GPIO1C0_SDMMC_CLKOUT,
296 };
297 
298 /* GRF_GPIO1D_IOMUX */
299 enum {
300 	GPIO1D7_SHIFT		= 14,
301 	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
302 	GPIO1D7_GPIO		= 0,
303 	GPIO1D7_NAND_D7,
304 	GPIO1D7_EMMC_D7,
305 
306 	GPIO1D6_SHIFT		= 12,
307 	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
308 	GPIO1D6_GPIO		= 0,
309 	GPIO1D6_NAND_D6,
310 	GPIO1D6_EMMC_D6,
311 
312 	GPIO1D5_SHIFT		= 10,
313 	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
314 	GPIO1D5_GPIO		= 0,
315 	GPIO1D5_NAND_D5,
316 	GPIO1D5_EMMC_D5,
317 
318 	GPIO1D4_SHIFT		= 8,
319 	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
320 	GPIO1D4_GPIO		= 0,
321 	GPIO1D4_NAND_D4,
322 	GPIO1D4_EMMC_D4,
323 
324 	GPIO1D3_SHIFT		= 6,
325 	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
326 	GPIO1D3_GPIO		= 0,
327 	GPIO1D3_NAND_D3,
328 	GPIO1D3_EMMC_D3,
329 
330 	GPIO1D2_SHIFT		= 4,
331 	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
332 	GPIO1D2_GPIO		= 0,
333 	GPIO1D2_NAND_D2,
334 	GPIO1D2_EMMC_D2,
335 
336 	GPIO1D1_SHIFT		= 2,
337 	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
338 	GPIO1D1_GPIO		= 0,
339 	GPIO1D1_NAND_D1,
340 	GPIO1D1_EMMC_D1,
341 
342 	GPIO1D0_SHIFT		= 0,
343 	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
344 	GPIO1D0_GPIO		= 0,
345 	GPIO1D0_NAND_D0,
346 	GPIO1D0_EMMC_D0,
347 };
348 
349 /* GRF_GPIO2A_IOMUX */
350 enum {
351 	GPIO2A7_SHIFT		= 14,
352 	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
353 	GPIO2A7_GPIO		= 0,
354 	GPIO2A7_NAND_DQS,
355 	GPIO2A7_EMMC_CLKOUT,
356 
357 	GPIO2A5_SHIFT		= 10,
358 	GPIO2A5_MASK		= 3 << GPIO2A5_SHIFT,
359 	GPIO2A5_GPIO		= 0,
360 	GPIO2A5_NAND_WP,
361 	GPIO2A5_EMMC_PWREN,
362 
363 	GPIO2A4_SHIFT		= 8,
364 	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
365 	GPIO2A4_GPIO		= 0,
366 	GPIO2A4_NAND_RDY,
367 	GPIO2A4_EMMC_CMD,
368 
369 	GPIO2A3_SHIFT		= 6,
370 	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
371 	GPIO2A3_GPIO		= 0,
372 	GPIO2A3_NAND_RDN,
373 	GPIO2A4_SPI1_CSN1,
374 
375 	GPIO2A2_SHIFT		= 4,
376 	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
377 	GPIO2A2_GPIO		= 0,
378 	GPIO2A2_NAND_WRN,
379 	GPIO2A4_SPI1_CSN0,
380 
381 	GPIO2A1_SHIFT		= 2,
382 	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
383 	GPIO2A1_GPIO		= 0,
384 	GPIO2A1_NAND_CLE,
385 	GPIO2A1_SPI1_TXD,
386 
387 	GPIO2A0_SHIFT		= 0,
388 	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
389 	GPIO2A0_GPIO		= 0,
390 	GPIO2A0_NAND_ALE,
391 	GPIO2A0_SPI1_RXD,
392 };
393 
394 /* GRF_GPIO2B_IOMUX */
395 enum {
396 	GPIO2B7_SHIFT		= 14,
397 	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
398 	GPIO2B7_GPIO		= 0,
399 	GPIO2B7_GMAC_RXER,
400 
401 	GPIO2B6_SHIFT		= 12,
402 	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
403 	GPIO2B6_GPIO		= 0,
404 	GPIO2B6_GMAC_CLK,
405 	GPIO2B6_MAC_LINK,
406 
407 	GPIO2B5_SHIFT		= 10,
408 	GPIO2B5_MASK		= 3 << GPIO2B5_SHIFT,
409 	GPIO2B5_GPIO		= 0,
410 	GPIO2B5_GMAC_TXEN,
411 
412 	GPIO2B4_SHIFT		= 8,
413 	GPIO2B4_MASK		= 3 << GPIO2B4_SHIFT,
414 	GPIO2B4_GPIO		= 0,
415 	GPIO2B4_GMAC_MDIO,
416 
417 	GPIO2B3_SHIFT		= 6,
418 	GPIO2B3_MASK		= 3 << GPIO2B3_SHIFT,
419 	GPIO2B3_GPIO		= 0,
420 	GPIO2B3_GMAC_RXCLK,
421 
422 	GPIO2B2_SHIFT		= 4,
423 	GPIO2B2_MASK		= 3 << GPIO2B2_SHIFT,
424 	GPIO2B2_GPIO		= 0,
425 	GPIO2B2_GMAC_CRS,
426 
427 	GPIO2B1_SHIFT		= 2,
428 	GPIO2B1_MASK		= 3 << GPIO2B1_SHIFT,
429 	GPIO2B1_GPIO		= 0,
430 	GPIO2B1_GMAC_TXCLK,
431 
432 
433 	GPIO2B0_SHIFT		= 0,
434 	GPIO2B0_MASK		= 3 << GPIO2B0_SHIFT,
435 	GPIO2B0_GPIO		= 0,
436 	GPIO2B0_GMAC_RXDV,
437 	GPIO2B0_MAC_SPEED_IOUT,
438 };
439 
440 /* GRF_GPIO2C_IOMUX */
441 enum {
442 	GPIO2C7_SHIFT		= 14,
443 	GPIO2C7_MASK		= 3 << GPIO2C7_SHIFT,
444 	GPIO2C7_GPIO		= 0,
445 	GPIO2C7_GMAC_TXD3,
446 
447 	GPIO2C6_SHIFT		= 12,
448 	GPIO2C6_MASK		= 3 << GPIO2C6_SHIFT,
449 	GPIO2C6_GPIO		= 0,
450 	GPIO2C6_GMAC_TXD2,
451 
452 	GPIO2C5_SHIFT		= 10,
453 	GPIO2C5_MASK		= 3 << GPIO2C5_SHIFT,
454 	GPIO2C5_GPIO		= 0,
455 	GPIO2C5_I2C2_SCL,
456 	GPIO2C5_GMAC_RXD2,
457 
458 	GPIO2C4_SHIFT		= 8,
459 	GPIO2C4_MASK		= 3 << GPIO2C4_SHIFT,
460 	GPIO2C4_GPIO		= 0,
461 	GPIO2C4_I2C2_SDA,
462 	GPIO2C4_GMAC_RXD3,
463 
464 	GPIO2C3_SHIFT		= 6,
465 	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
466 	GPIO2C3_GPIO		= 0,
467 	GPIO2C3_GMAC_TXD0,
468 
469 	GPIO2C2_SHIFT		= 4,
470 	GPIO2C2_MASK		= 3 << GPIO2C2_SHIFT,
471 	GPIO2C2_GPIO		= 0,
472 	GPIO2C2_GMAC_TXD1,
473 
474 	GPIO2C1_SHIFT		= 2,
475 	GPIO2C1_MASK		= 3 << GPIO2C1_SHIFT,
476 	GPIO2C1_GPIO		= 0,
477 	GPIO2C1_GMAC_RXD0,
478 
479 	GPIO2C0_SHIFT		= 0,
480 	GPIO2C0_MASK		= 3 << GPIO2C0_SHIFT,
481 	GPIO2C0_GPIO		= 0,
482 	GPIO2C0_GMAC_RXD1,
483 };
484 
485 /* GRF_GPIO2D_IOMUX */
486 enum {
487 	GPIO2D1_SHIFT		= 2,
488 	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
489 	GPIO2D1_GPIO		= 0,
490 	GPIO2D1_GMAC_MDC,
491 
492 	GPIO2D0_SHIFT		= 0,
493 	GPIO2D0_MASK		= 3,
494 	GPIO2D0_GPIO		= 0,
495 	GPIO2D0_GMAC_COL,
496 };
497 
498 /* GRF_GPIO3C_IOMUX */
499 enum {
500 	GPIO3C6_SHIFT		= 12,
501 	GPIO3C6_MASK		= 3 << GPIO3C6_SHIFT,
502 	GPIO3C6_GPIO		= 0,
503 	GPIO3C6_DRV_VBUS1,
504 
505 	GPIO3C5_SHIFT		= 10,
506 	GPIO3C5_MASK		= 3 << GPIO3C5_SHIFT,
507 	GPIO3C5_GPIO		= 0,
508 	GPIO3C5_PWM10,
509 
510 	GPIO3C1_SHIFT		= 2,
511 	GPIO3C1_MASK		= 3 << GPIO3C1_SHIFT,
512 	GPIO3C1_GPIO		= 0,
513 	GPIO3C1_DRV_VBUS,
514 };
515 
516 /* GRF_GPIO3D_IOMUX */
517 enum {
518 	GPIO3D2_SHIFT	= 4,
519 	GPIO3D2_MASK	= 3 << GPIO3D2_SHIFT,
520 	GPIO3D2_GPIO	= 0,
521 	GPIO3D2_PWM3,
522 };
523 
524 /* GRF_CON_IOMUX */
525 enum {
526 	CON_IOMUX_GMAC_SHIFT		= 15,
527 	CON_IOMUX_GMAC_MASK	= 1 << CON_IOMUX_GMAC_SHIFT,
528 	CON_IOMUX_UART1SEL_SHIFT	= 11,
529 	CON_IOMUX_UART1SEL_MASK	= 1 << CON_IOMUX_UART1SEL_SHIFT,
530 	CON_IOMUX_UART2SEL_SHIFT	= 8,
531 	CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
532 	CON_IOMUX_UART2SEL_2	= 0,
533 	CON_IOMUX_UART2SEL_21,
534 	CON_IOMUX_EMMCSEL_SHIFT	= 7,
535 	CON_IOMUX_EMMCSEL_MASK	= 1 << CON_IOMUX_EMMCSEL_SHIFT,
536 	CON_IOMUX_PWM3SEL_SHIFT	= 3,
537 	CON_IOMUX_PWM3SEL_MASK	= 1 << CON_IOMUX_PWM3SEL_SHIFT,
538 	CON_IOMUX_PWM2SEL_SHIFT	= 2,
539 	CON_IOMUX_PWM2SEL_MASK	= 1 << CON_IOMUX_PWM2SEL_SHIFT,
540 	CON_IOMUX_PWM1SEL_SHIFT	= 1,
541 	CON_IOMUX_PWM1SEL_MASK	= 1 << CON_IOMUX_PWM1SEL_SHIFT,
542 	CON_IOMUX_PWM0SEL_SHIFT	= 0,
543 	CON_IOMUX_PWM0SEL_MASK	= 1 << CON_IOMUX_PWM0SEL_SHIFT,
544 };
545 
546 /* GRF_MACPHY_CON0 */
547 enum {
548 	MACPHY_CFG_ENABLE_SHIFT = 0,
549 	MACPHY_CFG_ENABLE_MASK  = 1 << MACPHY_CFG_ENABLE_SHIFT,
550 };
551 #endif
552