1 /* 2 * Freescale i.MX28 SSP Register Definitions 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * Based on code from LTIB: 7 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __MX28_REGS_SSP_H__ 13 #define __MX28_REGS_SSP_H__ 14 15 #include <asm/mach-imx/regs-common.h> 16 17 #ifndef __ASSEMBLY__ 18 #if defined(CONFIG_MX23) 19 struct mxs_ssp_regs { 20 mxs_reg_32(hw_ssp_ctrl0) 21 mxs_reg_32(hw_ssp_cmd0) 22 mxs_reg_32(hw_ssp_cmd1) 23 mxs_reg_32(hw_ssp_compref) 24 mxs_reg_32(hw_ssp_compmask) 25 mxs_reg_32(hw_ssp_timing) 26 mxs_reg_32(hw_ssp_ctrl1) 27 mxs_reg_32(hw_ssp_data) 28 mxs_reg_32(hw_ssp_sdresp0) 29 mxs_reg_32(hw_ssp_sdresp1) 30 mxs_reg_32(hw_ssp_sdresp2) 31 mxs_reg_32(hw_ssp_sdresp3) 32 mxs_reg_32(hw_ssp_status) 33 34 uint32_t reserved1[12]; 35 36 mxs_reg_32(hw_ssp_debug) 37 mxs_reg_32(hw_ssp_version) 38 }; 39 #elif defined(CONFIG_MX28) 40 struct mxs_ssp_regs { 41 mxs_reg_32(hw_ssp_ctrl0) 42 mxs_reg_32(hw_ssp_cmd0) 43 mxs_reg_32(hw_ssp_cmd1) 44 mxs_reg_32(hw_ssp_xfer_size) 45 mxs_reg_32(hw_ssp_block_size) 46 mxs_reg_32(hw_ssp_compref) 47 mxs_reg_32(hw_ssp_compmask) 48 mxs_reg_32(hw_ssp_timing) 49 mxs_reg_32(hw_ssp_ctrl1) 50 mxs_reg_32(hw_ssp_data) 51 mxs_reg_32(hw_ssp_sdresp0) 52 mxs_reg_32(hw_ssp_sdresp1) 53 mxs_reg_32(hw_ssp_sdresp2) 54 mxs_reg_32(hw_ssp_sdresp3) 55 mxs_reg_32(hw_ssp_ddr_ctrl) 56 mxs_reg_32(hw_ssp_dll_ctrl) 57 mxs_reg_32(hw_ssp_status) 58 mxs_reg_32(hw_ssp_dll_sts) 59 mxs_reg_32(hw_ssp_debug) 60 mxs_reg_32(hw_ssp_version) 61 }; 62 #endif 63 64 static inline int mxs_ssp_bus_id_valid(int bus) 65 { 66 #if defined(CONFIG_MX23) 67 const unsigned int mxs_ssp_chan_count = 2; 68 #elif defined(CONFIG_MX28) 69 const unsigned int mxs_ssp_chan_count = 4; 70 #endif 71 72 if (bus >= mxs_ssp_chan_count) 73 return 0; 74 75 if (bus < 0) 76 return 0; 77 78 return 1; 79 } 80 81 static inline int mxs_ssp_clock_by_bus(unsigned int clock) 82 { 83 #if defined(CONFIG_MX23) 84 return 0; 85 #elif defined(CONFIG_MX28) 86 return clock; 87 #endif 88 } 89 90 static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) 91 { 92 switch (port) { 93 case 0: 94 return (struct mxs_ssp_regs *)MXS_SSP0_BASE; 95 case 1: 96 return (struct mxs_ssp_regs *)MXS_SSP1_BASE; 97 #ifdef CONFIG_MX28 98 case 2: 99 return (struct mxs_ssp_regs *)MXS_SSP2_BASE; 100 case 3: 101 return (struct mxs_ssp_regs *)MXS_SSP3_BASE; 102 #endif 103 default: 104 return NULL; 105 } 106 } 107 #endif 108 109 #define SSP_CTRL0_SFTRST (1 << 31) 110 #define SSP_CTRL0_CLKGATE (1 << 30) 111 #define SSP_CTRL0_RUN (1 << 29) 112 #define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 113 #define SSP_CTRL0_LOCK_CS (1 << 27) 114 #define SSP_CTRL0_IGNORE_CRC (1 << 26) 115 #define SSP_CTRL0_READ (1 << 25) 116 #define SSP_CTRL0_DATA_XFER (1 << 24) 117 #define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) 118 #define SSP_CTRL0_BUS_WIDTH_OFFSET 22 119 #define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) 120 #define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) 121 #define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) 122 #define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 123 #define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) 124 #define SSP_CTRL0_LONG_RESP (1 << 19) 125 #define SSP_CTRL0_CHECK_RESP (1 << 18) 126 #define SSP_CTRL0_GET_RESP (1 << 17) 127 #define SSP_CTRL0_ENABLE (1 << 16) 128 129 #ifdef CONFIG_MX23 130 #define SSP_CTRL0_XFER_COUNT_OFFSET 0 131 #define SSP_CTRL0_XFER_COUNT_MASK 0xffff 132 #endif 133 134 #define SSP_CMD0_SOFT_TERMINATE (1 << 26) 135 #define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 136 #define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) 137 #define SSP_CMD0_BOOT_ACK_EN (1 << 23) 138 #define SSP_CMD0_SLOW_CLKING_EN (1 << 22) 139 #define SSP_CMD0_CONT_CLKING_EN (1 << 21) 140 #define SSP_CMD0_APPEND_8CYC (1 << 20) 141 #if defined(CONFIG_MX23) 142 #define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) 143 #define SSP_CMD0_BLOCK_SIZE_OFFSET 16 144 #define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) 145 #define SSP_CMD0_BLOCK_COUNT_OFFSET 8 146 #endif 147 #define SSP_CMD0_CMD_MASK 0xff 148 #define SSP_CMD0_CMD_OFFSET 0 149 #define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 150 #define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 151 #define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 152 #define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 153 #define SSP_CMD0_CMD_MMC_SET_DSR 0x04 154 #define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 155 #define SSP_CMD0_CMD_MMC_SWITCH 0x06 156 #define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 157 #define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 158 #define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 159 #define SSP_CMD0_CMD_MMC_SEND_CID 0x0a 160 #define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b 161 #define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c 162 #define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d 163 #define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e 164 #define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f 165 #define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 166 #define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 167 #define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 168 #define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 169 #define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 170 #define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 171 #define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 172 #define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 173 #define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a 174 #define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b 175 #define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c 176 #define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d 177 #define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e 178 #define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 179 #define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 180 #define SSP_CMD0_CMD_MMC_ERASE 0x26 181 #define SSP_CMD0_CMD_MMC_FAST_IO 0x27 182 #define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 183 #define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a 184 #define SSP_CMD0_CMD_MMC_APP_CMD 0x37 185 #define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 186 #define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 187 #define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 188 #define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 189 #define SSP_CMD0_CMD_SD_SET_DSR 0x04 190 #define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 191 #define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 192 #define SSP_CMD0_CMD_SD_SEND_CSD 0x09 193 #define SSP_CMD0_CMD_SD_SEND_CID 0x0a 194 #define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c 195 #define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d 196 #define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f 197 #define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 198 #define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 199 #define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 200 #define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 201 #define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 202 #define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b 203 #define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c 204 #define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d 205 #define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e 206 #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 207 #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 208 #define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 209 #define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 210 #define SSP_CMD0_CMD_SD_ERASE 0x26 211 #define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a 212 #define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 213 #define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 214 #define SSP_CMD0_CMD_SD_APP_CMD 0x37 215 #define SSP_CMD0_CMD_SD_GEN_CMD 0x38 216 217 #define SSP_CMD1_CMD_ARG_MASK 0xffffffff 218 #define SSP_CMD1_CMD_ARG_OFFSET 0 219 220 #if defined(CONFIG_MX28) 221 #define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff 222 #define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 223 224 #define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) 225 #define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 226 #define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf 227 #define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 228 #endif 229 230 #define SSP_COMPREF_REFERENCE_MASK 0xffffffff 231 #define SSP_COMPREF_REFERENCE_OFFSET 0 232 233 #define SSP_COMPMASK_MASK_MASK 0xffffffff 234 #define SSP_COMPMASK_MASK_OFFSET 0 235 236 #define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) 237 #define SSP_TIMING_TIMEOUT_OFFSET 16 238 #define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) 239 #define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 240 #define SSP_TIMING_CLOCK_RATE_MASK 0xff 241 #define SSP_TIMING_CLOCK_RATE_OFFSET 0 242 243 #define SSP_CTRL1_SDIO_IRQ (1 << 31) 244 #define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 245 #define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 246 #define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 247 #define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 248 #define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 249 #define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 250 #define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 251 #define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 252 #define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 253 #define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 254 #define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) 255 #define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) 256 #define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) 257 #define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 258 #define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 259 #define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 260 #define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 261 #define SSP_CTRL1_DMA_ENABLE (1 << 13) 262 #define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) 263 #define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) 264 #define SSP_CTRL1_PHASE (1 << 10) 265 #define SSP_CTRL1_POLARITY (1 << 9) 266 #define SSP_CTRL1_SLAVE_MODE (1 << 8) 267 #define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) 268 #define SSP_CTRL1_WORD_LENGTH_OFFSET 4 269 #define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) 270 #define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) 271 #define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) 272 #define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) 273 #define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) 274 #define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) 275 #define SSP_CTRL1_SSP_MODE_MASK 0xf 276 #define SSP_CTRL1_SSP_MODE_OFFSET 0 277 #define SSP_CTRL1_SSP_MODE_SPI 0x0 278 #define SSP_CTRL1_SSP_MODE_SSI 0x1 279 #define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 280 #define SSP_CTRL1_SSP_MODE_MS 0x4 281 282 #define SSP_DATA_DATA_MASK 0xffffffff 283 #define SSP_DATA_DATA_OFFSET 0 284 285 #define SSP_SDRESP0_RESP0_MASK 0xffffffff 286 #define SSP_SDRESP0_RESP0_OFFSET 0 287 288 #define SSP_SDRESP1_RESP1_MASK 0xffffffff 289 #define SSP_SDRESP1_RESP1_OFFSET 0 290 291 #define SSP_SDRESP2_RESP2_MASK 0xffffffff 292 #define SSP_SDRESP2_RESP2_OFFSET 0 293 294 #define SSP_SDRESP3_RESP3_MASK 0xffffffff 295 #define SSP_SDRESP3_RESP3_OFFSET 0 296 297 #define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) 298 #define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 299 #define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) 300 #define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) 301 302 #define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) 303 #define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 304 #define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) 305 #define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 306 #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) 307 #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 308 #define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) 309 #define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) 310 #define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) 311 #define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 312 #define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) 313 #define SSP_DLL_CTRL_RESET (1 << 1) 314 #define SSP_DLL_CTRL_ENABLE (1 << 0) 315 316 #define SSP_STATUS_PRESENT (1 << 31) 317 #define SSP_STATUS_MS_PRESENT (1 << 30) 318 #define SSP_STATUS_SD_PRESENT (1 << 29) 319 #define SSP_STATUS_CARD_DETECT (1 << 28) 320 #define SSP_STATUS_DMABURST (1 << 22) 321 #define SSP_STATUS_DMASENSE (1 << 21) 322 #define SSP_STATUS_DMATERM (1 << 20) 323 #define SSP_STATUS_DMAREQ (1 << 19) 324 #define SSP_STATUS_DMAEND (1 << 18) 325 #define SSP_STATUS_SDIO_IRQ (1 << 17) 326 #define SSP_STATUS_RESP_CRC_ERR (1 << 16) 327 #define SSP_STATUS_RESP_ERR (1 << 15) 328 #define SSP_STATUS_RESP_TIMEOUT (1 << 14) 329 #define SSP_STATUS_DATA_CRC_ERR (1 << 13) 330 #define SSP_STATUS_TIMEOUT (1 << 12) 331 #define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) 332 #define SSP_STATUS_CEATA_CCS_ERR (1 << 10) 333 #define SSP_STATUS_FIFO_OVRFLW (1 << 9) 334 #define SSP_STATUS_FIFO_FULL (1 << 8) 335 #define SSP_STATUS_FIFO_EMPTY (1 << 5) 336 #define SSP_STATUS_FIFO_UNDRFLW (1 << 4) 337 #define SSP_STATUS_CMD_BUSY (1 << 3) 338 #define SSP_STATUS_DATA_BUSY (1 << 2) 339 #define SSP_STATUS_BUSY (1 << 0) 340 341 #define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) 342 #define SSP_DLL_STS_REF_SEL_OFFSET 8 343 #define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) 344 #define SSP_DLL_STS_SLV_SEL_OFFSET 2 345 #define SSP_DLL_STS_REF_LOCK (1 << 1) 346 #define SSP_DLL_STS_SLV_LOCK (1 << 0) 347 348 #define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) 349 #define SSP_DEBUG_DATACRC_ERR_OFFSET 28 350 #define SSP_DEBUG_DATA_STALL (1 << 27) 351 #define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) 352 #define SSP_DEBUG_DAT_SM_OFFSET 24 353 #define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) 354 #define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) 355 #define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) 356 #define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) 357 #define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) 358 #define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) 359 #define SSP_DEBUG_MSTK_SM_OFFSET 20 360 #define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) 361 #define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) 362 #define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) 363 #define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) 364 #define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) 365 #define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) 366 #define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) 367 #define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) 368 #define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) 369 #define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) 370 #define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) 371 #define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) 372 #define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) 373 #define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) 374 #define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) 375 #define SSP_DEBUG_CMD_OE (1 << 19) 376 #define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) 377 #define SSP_DEBUG_DMA_SM_OFFSET 16 378 #define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) 379 #define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) 380 #define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) 381 #define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) 382 #define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) 383 #define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) 384 #define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) 385 #define SSP_DEBUG_MMC_SM_MASK (0xf << 12) 386 #define SSP_DEBUG_MMC_SM_OFFSET 12 387 #define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) 388 #define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) 389 #define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) 390 #define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) 391 #define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) 392 #define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) 393 #define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) 394 #define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) 395 #define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) 396 #define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) 397 #define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) 398 #define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) 399 #define SSP_DEBUG_CMD_SM_OFFSET 10 400 #define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) 401 #define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) 402 #define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) 403 #define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) 404 #define SSP_DEBUG_SSP_CMD (1 << 9) 405 #define SSP_DEBUG_SSP_RESP (1 << 8) 406 #define SSP_DEBUG_SSP_RXD_MASK 0xff 407 #define SSP_DEBUG_SSP_RXD_OFFSET 0 408 409 #define SSP_VERSION_MAJOR_MASK (0xff << 24) 410 #define SSP_VERSION_MAJOR_OFFSET 24 411 #define SSP_VERSION_MINOR_MASK (0xff << 16) 412 #define SSP_VERSION_MINOR_OFFSET 16 413 #define SSP_VERSION_STEP_MASK 0xffff 414 #define SSP_VERSION_STEP_OFFSET 0 415 416 #endif /* __MX28_REGS_SSP_H__ */ 417