1 /* 2 * (C) Copyright 2010 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_KM83XX_H 9 #define __CONFIG_KM83XX_H 10 11 /* include common defines/options for all Keymile boards */ 12 #include "keymile-common.h" 13 #include "km-powerpc.h" 14 15 #ifndef MTDIDS_DEFAULT 16 # define MTDIDS_DEFAULT "nor0=boot" 17 #endif /* MTDIDS_DEFAULT */ 18 19 #ifndef MTDPARTS_DEFAULT 20 # define MTDPARTS_DEFAULT "mtdparts=" \ 21 "boot:" \ 22 "768k(u-boot)," \ 23 "128k(env)," \ 24 "128k(envred)," \ 25 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 26 #endif /* MTDPARTS_DEFAULT */ 27 28 #define CONFIG_MISC_INIT_R 29 /* 30 * System Clock Setup 31 */ 32 #define CONFIG_83XX_CLKIN 66000000 33 #define CONFIG_SYS_CLK_FREQ 66000000 34 #define CONFIG_83XX_PCICLK 66000000 35 36 /* 37 * IMMR new address 38 */ 39 #define CONFIG_SYS_IMMR 0xE0000000 40 41 /* 42 * Bus Arbitration Configuration Register (ACR) 43 */ 44 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 45 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 46 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 47 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 48 49 /* 50 * DDR Setup 51 */ 52 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 53 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 54 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 55 56 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 57 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 58 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 59 60 #define CFG_83XX_DDR_USES_CS0 61 62 /* 63 * Manually set up DDR parameters 64 */ 65 #define CONFIG_DDR_II 66 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 67 68 /* 69 * The reserved memory 70 */ 71 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 72 #define CONFIG_SYS_FLASH_BASE 0xF0000000 73 74 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 75 #define CONFIG_SYS_RAMBOOT 76 #endif 77 78 /* Reserve 768 kB for Mon */ 79 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 80 81 /* 82 * Initial RAM Base Address Setup 83 */ 84 #define CONFIG_SYS_INIT_RAM_LOCK 85 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 86 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 87 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 88 GENERATED_GBL_DATA_SIZE) 89 90 /* 91 * Init Local Bus Memory Controller: 92 * 93 * Bank Bus Machine PortSz Size Device 94 * ---- --- ------- ------ ----- ------ 95 * 0 Local GPCM 16 bit 256MB FLASH 96 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 97 * 98 */ 99 /* 100 * FLASH on the Local Bus 101 */ 102 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 103 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 104 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 105 #define CONFIG_SYS_FLASH_PROTECTION 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 107 108 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 109 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 110 111 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 112 BR_PS_16 | /* 16 bit port size */ \ 113 BR_MS_GPCM | /* MSEL = GPCM */ \ 114 BR_V) 115 116 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 117 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 118 OR_GPCM_SCY_5 | \ 119 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 120 121 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 122 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 123 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 124 125 /* 126 * PRIO1/PIGGY on the local bus CS1 127 */ 128 /* Window base at flash base */ 129 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 130 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 131 132 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 133 BR_PS_8 | /* 8 bit port size */ \ 134 BR_MS_GPCM | /* MSEL = GPCM */ \ 135 BR_V) 136 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 137 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 138 OR_GPCM_SCY_2 | \ 139 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 140 141 /* 142 * Serial Port 143 */ 144 #define CONFIG_CONS_INDEX 1 145 #define CONFIG_SYS_NS16550_SERIAL 146 #define CONFIG_SYS_NS16550_REG_SIZE 1 147 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 148 149 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 150 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 151 152 /* 153 * QE UEC ethernet configuration 154 */ 155 #define CONFIG_UEC_ETH 156 #define CONFIG_ETHPRIME "UEC0" 157 158 #if !defined(CONFIG_MPC8309) 159 #define CONFIG_UEC_ETH1 /* GETH1 */ 160 #define UEC_VERBOSE_DEBUG 1 161 #endif 162 163 #ifdef CONFIG_UEC_ETH1 164 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 165 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 166 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 167 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 168 #define CONFIG_SYS_UEC1_PHY_ADDR 0 169 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 170 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 171 #endif 172 173 /* 174 * Environment 175 */ 176 177 #ifndef CONFIG_SYS_RAMBOOT 178 #define CONFIG_ENV_IS_IN_FLASH 179 #ifndef CONFIG_ENV_ADDR 180 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 181 CONFIG_SYS_MONITOR_LEN) 182 #endif 183 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 184 #ifndef CONFIG_ENV_OFFSET 185 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 186 #endif 187 188 /* Address and size of Redundant Environment Sector */ 189 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 190 CONFIG_ENV_SECT_SIZE) 191 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 192 193 #else /* CFG_SYS_RAMBOOT */ 194 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 195 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 196 #define CONFIG_ENV_SIZE 0x2000 197 #endif /* CFG_SYS_RAMBOOT */ 198 199 /* I2C */ 200 #define CONFIG_SYS_I2C 201 #define CONFIG_SYS_NUM_I2C_BUSES 4 202 #define CONFIG_SYS_I2C_MAX_HOPS 1 203 #define CONFIG_SYS_I2C_FSL 204 #define CONFIG_SYS_FSL_I2C_SPEED 200000 205 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 206 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 207 #define CONFIG_SYS_I2C_OFFSET 0x3000 208 #define CONFIG_SYS_FSL_I2C2_SPEED 200000 209 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 211 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ 212 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 213 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 214 {1, {I2C_NULL_HOP} } } 215 216 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ 217 218 /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 219 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 220 #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 221 #define CONFIG_SYS_DTT_MAX_TEMP 70 222 #define CONFIG_SYS_DTT_HYSTERESIS 3 223 #define CONFIG_SYS_DTT_BUS_NUM 1 224 225 #if defined(CONFIG_CMD_NAND) 226 #define CONFIG_NAND_KMETER1 227 #define CONFIG_SYS_MAX_NAND_DEVICE 1 228 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 229 #endif 230 231 #if defined(CONFIG_PCI) 232 #define CONFIG_CMD_PCI 233 #endif 234 235 /* 236 * For booting Linux, the board info and command line data 237 * have to be in the first 8 MB of memory, since this is 238 * the maximum mapped by the Linux kernel during initialization. 239 */ 240 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 241 242 /* 243 * Core HID Setup 244 */ 245 #define CONFIG_SYS_HID0_INIT 0x000000000 246 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 247 HID0_ENABLE_INSTRUCTION_CACHE) 248 #define CONFIG_SYS_HID2 HID2_HBE 249 250 /* 251 * MMU Setup 252 */ 253 254 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 255 256 /* DDR: cache cacheable */ 257 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 258 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 259 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 260 BATU_VS | BATU_VP) 261 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 262 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 263 264 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 265 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 266 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 267 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 268 | BATU_VP) 269 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 270 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 271 272 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 273 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 274 BATL_MEMCOHERENCE) 275 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 276 BATU_VS | BATU_VP) 277 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 278 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 279 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 280 281 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 282 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 283 BATL_MEMCOHERENCE) 284 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 285 BATU_VS | BATU_VP) 286 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 287 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 288 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 289 290 /* Stack in dcache: cacheable, no memory coherence */ 291 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 292 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 293 BATU_VS | BATU_VP) 294 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 295 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 296 297 /* 298 * Internal Definitions 299 */ 300 #define BOOTFLASH_START 0xF0000000 301 302 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 303 304 /* 305 * Environment Configuration 306 */ 307 #define CONFIG_ENV_OVERWRITE 308 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 309 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 310 #endif 311 312 #ifndef CONFIG_KM_DEF_ARCH 313 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 314 #endif 315 316 #define CONFIG_EXTRA_ENV_SETTINGS \ 317 CONFIG_KM_DEF_ENV \ 318 CONFIG_KM_DEF_ARCH \ 319 "newenv=" \ 320 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ 321 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ 322 "unlock=yes\0" \ 323 "" 324 325 #if defined(CONFIG_UEC_ETH) 326 #define CONFIG_HAS_ETH0 327 #endif 328 329 #endif /* __CONFIG_KM83XX_H */ 330