1 /* 2 * Copyright (c) 2014 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <inttypes.h> 13 #include <pci.h> 14 #include <dm/lists.h> 15 #include <dm/root.h> 16 #include <dm/device-internal.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 struct pci_controller *pci_bus_to_hose(int busnum) 21 { 22 struct udevice *bus; 23 int ret; 24 25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus); 26 if (ret) { 27 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); 28 return NULL; 29 } 30 return dev_get_uclass_priv(bus); 31 } 32 33 /** 34 * pci_get_bus_max() - returns the bus number of the last active bus 35 * 36 * @return last bus number, or -1 if no active buses 37 */ 38 static int pci_get_bus_max(void) 39 { 40 struct udevice *bus; 41 struct uclass *uc; 42 int ret = -1; 43 44 ret = uclass_get(UCLASS_PCI, &uc); 45 uclass_foreach_dev(bus, uc) { 46 if (bus->seq > ret) 47 ret = bus->seq; 48 } 49 50 debug("%s: ret=%d\n", __func__, ret); 51 52 return ret; 53 } 54 55 int pci_last_busno(void) 56 { 57 struct pci_controller *hose; 58 struct udevice *bus; 59 struct uclass *uc; 60 int ret; 61 62 debug("pci_last_busno\n"); 63 ret = uclass_get(UCLASS_PCI, &uc); 64 if (ret || list_empty(&uc->dev_head)) 65 return -1; 66 67 /* Probe the last bus */ 68 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); 69 debug("bus = %p, %s\n", bus, bus->name); 70 assert(bus); 71 ret = device_probe(bus); 72 if (ret) 73 return ret; 74 75 /* If that bus has bridges, we may have new buses now. Get the last */ 76 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); 77 hose = dev_get_uclass_priv(bus); 78 debug("bus = %s, hose = %p\n", bus->name, hose); 79 80 return hose->last_busno; 81 } 82 83 int pci_get_ff(enum pci_size_t size) 84 { 85 switch (size) { 86 case PCI_SIZE_8: 87 return 0xff; 88 case PCI_SIZE_16: 89 return 0xffff; 90 default: 91 return 0xffffffff; 92 } 93 } 94 95 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 96 struct udevice **devp) 97 { 98 struct udevice *dev; 99 100 for (device_find_first_child(bus, &dev); 101 dev; 102 device_find_next_child(&dev)) { 103 struct pci_child_platdata *pplat; 104 105 pplat = dev_get_parent_platdata(dev); 106 if (pplat && pplat->devfn == find_devfn) { 107 *devp = dev; 108 return 0; 109 } 110 } 111 112 return -ENODEV; 113 } 114 115 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp) 116 { 117 struct udevice *bus; 118 int ret; 119 120 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 121 if (ret) 122 return ret; 123 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp); 124 } 125 126 static int pci_device_matches_ids(struct udevice *dev, 127 struct pci_device_id *ids) 128 { 129 struct pci_child_platdata *pplat; 130 int i; 131 132 pplat = dev_get_parent_platdata(dev); 133 if (!pplat) 134 return -EINVAL; 135 for (i = 0; ids[i].vendor != 0; i++) { 136 if (pplat->vendor == ids[i].vendor && 137 pplat->device == ids[i].device) 138 return i; 139 } 140 141 return -EINVAL; 142 } 143 144 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 145 int *indexp, struct udevice **devp) 146 { 147 struct udevice *dev; 148 149 /* Scan all devices on this bus */ 150 for (device_find_first_child(bus, &dev); 151 dev; 152 device_find_next_child(&dev)) { 153 if (pci_device_matches_ids(dev, ids) >= 0) { 154 if ((*indexp)-- <= 0) { 155 *devp = dev; 156 return 0; 157 } 158 } 159 } 160 161 return -ENODEV; 162 } 163 164 int pci_find_device_id(struct pci_device_id *ids, int index, 165 struct udevice **devp) 166 { 167 struct udevice *bus; 168 169 /* Scan all known buses */ 170 for (uclass_first_device(UCLASS_PCI, &bus); 171 bus; 172 uclass_next_device(&bus)) { 173 if (!pci_bus_find_devices(bus, ids, &index, devp)) 174 return 0; 175 } 176 *devp = NULL; 177 178 return -ENODEV; 179 } 180 181 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 182 unsigned long value, enum pci_size_t size) 183 { 184 struct dm_pci_ops *ops; 185 186 ops = pci_get_ops(bus); 187 if (!ops->write_config) 188 return -ENOSYS; 189 return ops->write_config(bus, bdf, offset, value, size); 190 } 191 192 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, 193 enum pci_size_t size) 194 { 195 struct udevice *bus; 196 int ret; 197 198 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 199 if (ret) 200 return ret; 201 202 return pci_bus_write_config(bus, PCI_MASK_BUS(bdf), offset, value, 203 size); 204 } 205 206 int pci_write_config32(pci_dev_t bdf, int offset, u32 value) 207 { 208 return pci_write_config(bdf, offset, value, PCI_SIZE_32); 209 } 210 211 int pci_write_config16(pci_dev_t bdf, int offset, u16 value) 212 { 213 return pci_write_config(bdf, offset, value, PCI_SIZE_16); 214 } 215 216 int pci_write_config8(pci_dev_t bdf, int offset, u8 value) 217 { 218 return pci_write_config(bdf, offset, value, PCI_SIZE_8); 219 } 220 221 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 222 unsigned long *valuep, enum pci_size_t size) 223 { 224 struct dm_pci_ops *ops; 225 226 ops = pci_get_ops(bus); 227 if (!ops->read_config) 228 return -ENOSYS; 229 return ops->read_config(bus, bdf, offset, valuep, size); 230 } 231 232 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, 233 enum pci_size_t size) 234 { 235 struct udevice *bus; 236 int ret; 237 238 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 239 if (ret) 240 return ret; 241 242 return pci_bus_read_config(bus, PCI_MASK_BUS(bdf), offset, valuep, 243 size); 244 } 245 246 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) 247 { 248 unsigned long value; 249 int ret; 250 251 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); 252 if (ret) 253 return ret; 254 *valuep = value; 255 256 return 0; 257 } 258 259 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep) 260 { 261 unsigned long value; 262 int ret; 263 264 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16); 265 if (ret) 266 return ret; 267 *valuep = value; 268 269 return 0; 270 } 271 272 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep) 273 { 274 unsigned long value; 275 int ret; 276 277 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8); 278 if (ret) 279 return ret; 280 *valuep = value; 281 282 return 0; 283 } 284 285 int pci_auto_config_devices(struct udevice *bus) 286 { 287 struct pci_controller *hose = bus->uclass_priv; 288 unsigned int sub_bus; 289 struct udevice *dev; 290 int ret; 291 292 sub_bus = bus->seq; 293 debug("%s: start\n", __func__); 294 pciauto_config_init(hose); 295 for (ret = device_find_first_child(bus, &dev); 296 !ret && dev; 297 ret = device_find_next_child(&dev)) { 298 struct pci_child_platdata *pplat; 299 300 pplat = dev_get_parent_platdata(dev); 301 unsigned int max_bus; 302 pci_dev_t bdf; 303 304 bdf = PCI_ADD_BUS(bus->seq, pplat->devfn); 305 debug("%s: device %s\n", __func__, dev->name); 306 max_bus = pciauto_config_device(hose, bdf); 307 sub_bus = max(sub_bus, max_bus); 308 } 309 debug("%s: done\n", __func__); 310 311 return sub_bus; 312 } 313 314 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) 315 { 316 struct udevice *parent, *bus; 317 int sub_bus; 318 int ret; 319 320 debug("%s\n", __func__); 321 parent = hose->bus; 322 323 /* Find the bus within the parent */ 324 ret = pci_bus_find_devfn(parent, bdf, &bus); 325 if (ret) { 326 debug("%s: Cannot find device %x on bus %s: %d\n", __func__, 327 bdf, parent->name, ret); 328 return ret; 329 } 330 331 sub_bus = pci_get_bus_max() + 1; 332 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); 333 pciauto_prescan_setup_bridge(hose, bdf, bus->seq); 334 335 ret = device_probe(bus); 336 if (ret) { 337 debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name, 338 ret); 339 return ret; 340 } 341 if (sub_bus != bus->seq) { 342 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", 343 __func__, bus->name, bus->seq, sub_bus); 344 return -EPIPE; 345 } 346 sub_bus = pci_get_bus_max(); 347 pciauto_postscan_setup_bridge(hose, bdf, sub_bus); 348 349 return sub_bus; 350 } 351 352 int pci_bind_bus_devices(struct udevice *bus) 353 { 354 ulong vendor, device; 355 ulong header_type; 356 pci_dev_t devfn, end; 357 bool found_multi; 358 int ret; 359 360 found_multi = false; 361 end = PCI_DEVFN(PCI_MAX_PCI_DEVICES - 1, PCI_MAX_PCI_FUNCTIONS - 1); 362 for (devfn = PCI_DEVFN(0, 0); devfn < end; devfn += PCI_DEVFN(0, 1)) { 363 struct pci_child_platdata *pplat; 364 struct udevice *dev; 365 ulong class; 366 367 if (PCI_FUNC(devfn) && !found_multi) 368 continue; 369 /* Check only the first access, we don't expect problems */ 370 ret = pci_bus_read_config(bus, devfn, PCI_HEADER_TYPE, 371 &header_type, PCI_SIZE_8); 372 if (ret) 373 goto error; 374 pci_bus_read_config(bus, devfn, PCI_VENDOR_ID, &vendor, 375 PCI_SIZE_16); 376 if (vendor == 0xffff || vendor == 0x0000) 377 continue; 378 379 if (!PCI_FUNC(devfn)) 380 found_multi = header_type & 0x80; 381 382 debug("%s: bus %d/%s: found device %x, function %d\n", __func__, 383 bus->seq, bus->name, PCI_DEV(devfn), PCI_FUNC(devfn)); 384 pci_bus_read_config(bus, devfn, PCI_DEVICE_ID, &device, 385 PCI_SIZE_16); 386 pci_bus_read_config(bus, devfn, PCI_CLASS_DEVICE, &class, 387 PCI_SIZE_16); 388 389 /* Find this device in the device tree */ 390 ret = pci_bus_find_devfn(bus, devfn, &dev); 391 392 /* If nothing in the device tree, bind a generic device */ 393 if (ret == -ENODEV) { 394 char name[30], *str; 395 const char *drv; 396 397 sprintf(name, "pci_%x:%x.%x", bus->seq, 398 PCI_DEV(devfn), PCI_FUNC(devfn)); 399 str = strdup(name); 400 if (!str) 401 return -ENOMEM; 402 drv = class == PCI_CLASS_BRIDGE_PCI ? 403 "pci_bridge_drv" : "pci_generic_drv"; 404 ret = device_bind_driver(bus, drv, str, &dev); 405 } 406 if (ret) 407 return ret; 408 409 /* Update the platform data */ 410 pplat = dev_get_parent_platdata(dev); 411 pplat->devfn = devfn; 412 pplat->vendor = vendor; 413 pplat->device = device; 414 pplat->class = class; 415 } 416 417 return 0; 418 error: 419 printf("Cannot read bus configuration: %d\n", ret); 420 421 return ret; 422 } 423 424 static int pci_uclass_post_bind(struct udevice *bus) 425 { 426 /* 427 * Scan the device tree for devices. This does not probe the PCI bus, 428 * as this is not permitted while binding. It just finds devices 429 * mentioned in the device tree. 430 * 431 * Before relocation, only bind devices marked for pre-relocation 432 * use. 433 */ 434 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, 435 gd->flags & GD_FLG_RELOC ? false : true); 436 } 437 438 static int decode_regions(struct pci_controller *hose, const void *blob, 439 int parent_node, int node) 440 { 441 int pci_addr_cells, addr_cells, size_cells; 442 int cells_per_record; 443 const u32 *prop; 444 int len; 445 int i; 446 447 prop = fdt_getprop(blob, node, "ranges", &len); 448 if (!prop) 449 return -EINVAL; 450 pci_addr_cells = fdt_address_cells(blob, node); 451 addr_cells = fdt_address_cells(blob, parent_node); 452 size_cells = fdt_size_cells(blob, node); 453 454 /* PCI addresses are always 3-cells */ 455 len /= sizeof(u32); 456 cells_per_record = pci_addr_cells + addr_cells + size_cells; 457 hose->region_count = 0; 458 debug("%s: len=%d, cells_per_record=%d\n", __func__, len, 459 cells_per_record); 460 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) { 461 u64 pci_addr, addr, size; 462 int space_code; 463 u32 flags; 464 int type; 465 466 if (len < cells_per_record) 467 break; 468 flags = fdt32_to_cpu(prop[0]); 469 space_code = (flags >> 24) & 3; 470 pci_addr = fdtdec_get_number(prop + 1, 2); 471 prop += pci_addr_cells; 472 addr = fdtdec_get_number(prop, addr_cells); 473 prop += addr_cells; 474 size = fdtdec_get_number(prop, size_cells); 475 prop += size_cells; 476 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64 477 ", size=%" PRIx64 ", space_code=%d\n", __func__, 478 hose->region_count, pci_addr, addr, size, space_code); 479 if (space_code & 2) { 480 type = flags & (1U << 30) ? PCI_REGION_PREFETCH : 481 PCI_REGION_MEM; 482 } else if (space_code & 1) { 483 type = PCI_REGION_IO; 484 } else { 485 continue; 486 } 487 debug(" - type=%d\n", type); 488 pci_set_region(hose->regions + hose->region_count++, pci_addr, 489 addr, size, type); 490 } 491 492 /* Add a region for our local memory */ 493 pci_set_region(hose->regions + hose->region_count++, 0, 0, 494 gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 495 496 return 0; 497 } 498 499 static int pci_uclass_pre_probe(struct udevice *bus) 500 { 501 struct pci_controller *hose; 502 int ret; 503 504 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name, 505 bus->parent->name); 506 hose = bus->uclass_priv; 507 508 /* For bridges, use the top-level PCI controller */ 509 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) { 510 hose->ctlr = bus; 511 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset, 512 bus->of_offset); 513 if (ret) { 514 debug("%s: Cannot decode regions\n", __func__); 515 return ret; 516 } 517 } else { 518 struct pci_controller *parent_hose; 519 520 parent_hose = dev_get_uclass_priv(bus->parent); 521 hose->ctlr = parent_hose->bus; 522 } 523 hose->bus = bus; 524 hose->first_busno = bus->seq; 525 hose->last_busno = bus->seq; 526 527 return 0; 528 } 529 530 static int pci_uclass_post_probe(struct udevice *bus) 531 { 532 int ret; 533 534 /* Don't scan buses before relocation */ 535 if (!(gd->flags & GD_FLG_RELOC)) 536 return 0; 537 538 debug("%s: probing bus %d\n", __func__, bus->seq); 539 ret = pci_bind_bus_devices(bus); 540 if (ret) 541 return ret; 542 543 #ifdef CONFIG_PCI_PNP 544 ret = pci_auto_config_devices(bus); 545 #endif 546 547 return ret < 0 ? ret : 0; 548 } 549 550 static int pci_uclass_child_post_bind(struct udevice *dev) 551 { 552 struct pci_child_platdata *pplat; 553 struct fdt_pci_addr addr; 554 int ret; 555 556 if (dev->of_offset == -1) 557 return 0; 558 559 /* 560 * We could read vendor, device, class if available. But for now we 561 * just check the address. 562 */ 563 pplat = dev_get_parent_platdata(dev); 564 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, 565 FDT_PCI_SPACE_CONFIG, "reg", &addr); 566 567 if (ret) { 568 if (ret != -ENOENT) 569 return -EINVAL; 570 } else { 571 /* extract the bdf from fdt_pci_addr */ 572 pplat->devfn = addr.phys_hi & 0xffff00; 573 } 574 575 return 0; 576 } 577 578 int pci_bridge_read_config(struct udevice *bus, pci_dev_t devfn, uint offset, 579 ulong *valuep, enum pci_size_t size) 580 { 581 struct pci_controller *hose = bus->uclass_priv; 582 pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn); 583 584 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size); 585 } 586 587 int pci_bridge_write_config(struct udevice *bus, pci_dev_t devfn, uint offset, 588 ulong value, enum pci_size_t size) 589 { 590 struct pci_controller *hose = bus->uclass_priv; 591 pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn); 592 593 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size); 594 } 595 596 UCLASS_DRIVER(pci) = { 597 .id = UCLASS_PCI, 598 .name = "pci", 599 .post_bind = pci_uclass_post_bind, 600 .pre_probe = pci_uclass_pre_probe, 601 .post_probe = pci_uclass_post_probe, 602 .child_post_bind = pci_uclass_child_post_bind, 603 .per_device_auto_alloc_size = sizeof(struct pci_controller), 604 .per_child_platdata_auto_alloc_size = 605 sizeof(struct pci_child_platdata), 606 }; 607 608 static const struct dm_pci_ops pci_bridge_ops = { 609 .read_config = pci_bridge_read_config, 610 .write_config = pci_bridge_write_config, 611 }; 612 613 static const struct udevice_id pci_bridge_ids[] = { 614 { .compatible = "pci-bridge" }, 615 { } 616 }; 617 618 U_BOOT_DRIVER(pci_bridge_drv) = { 619 .name = "pci_bridge_drv", 620 .id = UCLASS_PCI, 621 .of_match = pci_bridge_ids, 622 .ops = &pci_bridge_ops, 623 }; 624 625 UCLASS_DRIVER(pci_generic) = { 626 .id = UCLASS_PCI_GENERIC, 627 .name = "pci_generic", 628 }; 629 630 static const struct udevice_id pci_generic_ids[] = { 631 { .compatible = "pci-generic" }, 632 { } 633 }; 634 635 U_BOOT_DRIVER(pci_generic_drv) = { 636 .name = "pci_generic_drv", 637 .id = UCLASS_PCI_GENERIC, 638 .of_match = pci_generic_ids, 639 }; 640