1 /* 2 * (C) Copyright 2007 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* This is a board specific file. It's OK to include board specific 10 * header files */ 11 12 #include <common.h> 13 #include <config.h> 14 #include <fdtdec.h> 15 #include <netdev.h> 16 #include <asm/processor.h> 17 #include <asm/microblaze_intc.h> 18 #include <asm/asm.h> 19 #include <asm/gpio.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #ifdef CONFIG_XILINX_GPIO 24 static int reset_pin = -1; 25 #endif 26 27 #ifdef CONFIG_OF_CONTROL 28 ulong ram_base; 29 30 void dram_init_banksize(void) 31 { 32 gd->bd->bi_dram[0].start = ram_base; 33 gd->bd->bi_dram[0].size = get_effective_memsize(); 34 } 35 36 int dram_init(void) 37 { 38 int node; 39 fdt_addr_t addr; 40 fdt_size_t size; 41 const void *blob = gd->fdt_blob; 42 43 node = fdt_node_offset_by_prop_value(blob, -1, "device_type", 44 "memory", 7); 45 if (node == -FDT_ERR_NOTFOUND) { 46 debug("DRAM: Can't get memory node\n"); 47 return 1; 48 } 49 addr = fdtdec_get_addr_size(blob, node, "reg", &size); 50 if (addr == FDT_ADDR_T_NONE || size == 0) { 51 debug("DRAM: Can't get base address or size\n"); 52 return 1; 53 } 54 ram_base = addr; 55 56 gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */ 57 gd->ram_size = size; 58 59 return 0; 60 }; 61 #else 62 int dram_init(void) 63 { 64 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 65 66 return 0; 67 } 68 #endif 69 70 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 71 { 72 #ifdef CONFIG_XILINX_GPIO 73 if (reset_pin != -1) 74 gpio_direction_output(reset_pin, 1); 75 #endif 76 77 #ifdef CONFIG_XILINX_TB_WATCHDOG 78 hw_watchdog_disable(); 79 #endif 80 81 puts ("Reseting board\n"); 82 __asm__ __volatile__ (" mts rmsr, r0;" \ 83 "bra r0"); 84 85 return 0; 86 } 87 88 int gpio_init (void) 89 { 90 #ifdef CONFIG_XILINX_GPIO 91 reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); 92 if (reset_pin != -1) 93 gpio_request(reset_pin, "reset_pin"); 94 #endif 95 return 0; 96 } 97 98 void board_init(void) 99 { 100 gpio_init(); 101 } 102 103 int board_eth_init(bd_t *bis) 104 { 105 int ret = 0; 106 107 #ifdef CONFIG_XILINX_AXIEMAC 108 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, 109 XILINX_AXIDMA_BASEADDR); 110 #endif 111 112 #if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) 113 u32 txpp = 0; 114 u32 rxpp = 0; 115 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 116 txpp = 1; 117 # endif 118 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 119 rxpp = 1; 120 # endif 121 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, 122 txpp, rxpp); 123 #endif 124 125 #ifdef CONFIG_XILINX_LL_TEMAC 126 # ifdef XILINX_LLTEMAC_BASEADDR 127 # ifdef XILINX_LLTEMAC_FIFO_BASEADDR 128 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, 129 XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR); 130 # elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 131 # if XILINX_LLTEMAC_SDMA_USE_DCR == 1 132 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, 133 XILINX_LL_TEMAC_M_SDMA_DCR, 134 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); 135 # else 136 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, 137 XILINX_LL_TEMAC_M_SDMA_PLB, 138 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); 139 # endif 140 # endif 141 # endif 142 # ifdef XILINX_LLTEMAC_BASEADDR1 143 # ifdef XILINX_LLTEMAC_FIFO_BASEADDR1 144 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, 145 XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1); 146 # elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 147 # if XILINX_LLTEMAC_SDMA_USE_DCR == 1 148 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, 149 XILINX_LL_TEMAC_M_SDMA_DCR, 150 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); 151 # else 152 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, 153 XILINX_LL_TEMAC_M_SDMA_PLB, 154 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); 155 # endif 156 # endif 157 # endif 158 #endif 159 160 return ret; 161 } 162