1 /*
2  * (C) Copyright 2016
3  * Vikas Manocha, <vikas.manocha@st.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <dm.h>
10 #include <ram.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #include <asm/armv7m.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/stm32_periph.h>
17 #include <asm/arch/stm32_defs.h>
18 #include <asm/arch/syscfg.h>
19 #include <asm/gpio.h>
20 
21 DECLARE_GLOBAL_DATA_PTR;
22 
23 int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
24 {
25 	int mr_node;
26 
27 	mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
28 	if (mr_node < 0)
29 		return mr_node;
30 	*mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
31 						      "reg", 0, mr_size, false);
32 	debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
33 
34 	return 0;
35 }
36 int dram_init(void)
37 {
38 	int rv;
39 	fdt_addr_t mr_base, mr_size;
40 
41 #ifndef CONFIG_SUPPORT_SPL
42 	struct udevice *dev;
43 	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
44 	if (rv) {
45 		debug("DRAM init failed: %d\n", rv);
46 		return rv;
47 	}
48 
49 #endif
50 	rv = get_memory_base_size(&mr_base, &mr_size);
51 	if (rv)
52 		return rv;
53 	gd->ram_size = mr_size;
54 	gd->ram_top = mr_base;
55 
56 	return rv;
57 }
58 
59 int dram_init_banksize(void)
60 {
61 	fdt_addr_t mr_base, mr_size;
62 	get_memory_base_size(&mr_base, &mr_size);
63 	/*
64 	 * Fill in global info with description of SRAM configuration
65 	 */
66 	gd->bd->bi_dram[0].start = mr_base;
67 	gd->bd->bi_dram[0].size  = mr_size;
68 
69 	return 0;
70 }
71 
72 #ifdef CONFIG_ETH_DESIGNWARE
73 static int stmmac_setup(void)
74 {
75 	clock_setup(SYSCFG_CLOCK_CFG);
76 	/* Set >RMII mode */
77 	STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
78 	clock_setup(STMMAC_CLOCK_CFG);
79 
80 	return 0;
81 }
82 
83 int board_early_init_f(void)
84 {
85 	stmmac_setup();
86 
87 	return 0;
88 }
89 #endif
90 
91 #ifdef CONFIG_SPL_BUILD
92 #ifdef CONFIG_SPL_OS_BOOT
93 int spl_start_uboot(void)
94 {
95 	debug("SPL: booting kernel\n");
96 	/* break into full u-boot on 'c' */
97 	return serial_tstc() && serial_getc() == 'c';
98 }
99 #endif
100 
101 int spl_dram_init(void)
102 {
103 	struct udevice *dev;
104 	int rv;
105 	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
106 	if (rv)
107 		debug("DRAM init failed: %d\n", rv);
108 	return rv;
109 }
110 void spl_board_init(void)
111 {
112 	spl_dram_init();
113 	preloader_console_init();
114 	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
115 }
116 u32 spl_boot_device(void)
117 {
118 	return BOOT_DEVICE_XIP;
119 }
120 
121 #endif
122 u32 get_board_rev(void)
123 {
124 	return 0;
125 }
126 
127 int board_late_init(void)
128 {
129 	struct gpio_desc gpio = {};
130 	int node;
131 
132 	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
133 	if (node < 0)
134 		return -1;
135 
136 	gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
137 				   GPIOD_IS_OUT);
138 
139 	if (dm_gpio_is_valid(&gpio)) {
140 		dm_gpio_set_value(&gpio, 0);
141 		mdelay(10);
142 		dm_gpio_set_value(&gpio, 1);
143 	}
144 
145 	/* read button 1*/
146 	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
147 	if (node < 0)
148 		return -1;
149 
150 	gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
151 				   &gpio, GPIOD_IS_IN);
152 
153 	if (dm_gpio_is_valid(&gpio)) {
154 		if (dm_gpio_get_value(&gpio))
155 			puts("usr button is at HIGH LEVEL\n");
156 		else
157 			puts("usr button is at LOW LEVEL\n");
158 	}
159 
160 	return 0;
161 }
162 
163 int board_init(void)
164 {
165 	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
166 	return 0;
167 }
168