1 /* 2 * (C) Copyright 2010 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/iomux-mx53.h> 14 #include <linux/errno.h> 15 #include <asm/mach-imx/boot_mode.h> 16 #include <netdev.h> 17 #include <i2c.h> 18 #include <mmc.h> 19 #include <fsl_esdhc.h> 20 #include <power/pmic.h> 21 #include <fsl_pmic.h> 22 #include <asm/gpio.h> 23 #include <mc13892.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 int dram_init(void) 28 { 29 /* dram_init must store complete ramsize in gd->ram_size */ 30 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 31 PHYS_SDRAM_1_SIZE); 32 return 0; 33 } 34 35 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 36 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 37 38 static void setup_iomux_uart(void) 39 { 40 static const iomux_v3_cfg_t uart_pads[] = { 41 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), 42 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), 43 }; 44 45 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 46 } 47 48 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 49 PAD_CTL_HYS | PAD_CTL_ODE) 50 51 static void setup_i2c(unsigned int port_number) 52 { 53 static const iomux_v3_cfg_t i2c1_pads[] = { 54 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), 55 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), 56 }; 57 58 static const iomux_v3_cfg_t i2c2_pads[] = { 59 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL), 60 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL), 61 }; 62 63 switch (port_number) { 64 case 0: 65 imx_iomux_v3_setup_multiple_pads(i2c1_pads, 66 ARRAY_SIZE(i2c1_pads)); 67 break; 68 case 1: 69 imx_iomux_v3_setup_multiple_pads(i2c2_pads, 70 ARRAY_SIZE(i2c2_pads)); 71 break; 72 default: 73 printf("Warning: Wrong I2C port number\n"); 74 break; 75 } 76 } 77 78 void power_init(void) 79 { 80 unsigned int val; 81 struct pmic *p; 82 int ret; 83 84 ret = pmic_init(I2C_0); 85 if (ret) 86 return; 87 88 p = pmic_get("FSL_PMIC"); 89 if (!p) 90 return; 91 92 /* Set VDDA to 1.25V */ 93 pmic_reg_read(p, REG_SW_2, &val); 94 val &= ~SWX_OUT_MASK; 95 val |= SWX_OUT_1_25; 96 pmic_reg_write(p, REG_SW_2, val); 97 98 /* 99 * Need increase VCC and VDDA to 1.3V 100 * according to MX53 IC TO2 datasheet. 101 */ 102 if (is_soc_rev(CHIP_REV_2_0) == 0) { 103 /* Set VCC to 1.3V for TO2 */ 104 pmic_reg_read(p, REG_SW_1, &val); 105 val &= ~SWX_OUT_MASK; 106 val |= SWX_OUT_1_30; 107 pmic_reg_write(p, REG_SW_1, val); 108 109 /* Set VDDA to 1.3V for TO2 */ 110 pmic_reg_read(p, REG_SW_2, &val); 111 val &= ~SWX_OUT_MASK; 112 val |= SWX_OUT_1_30; 113 pmic_reg_write(p, REG_SW_2, val); 114 } 115 } 116 117 static void setup_iomux_fec(void) 118 { 119 static const iomux_v3_cfg_t fec_pads[] = { 120 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 121 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), 122 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 123 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 124 PAD_CTL_HYS | PAD_CTL_PKE), 125 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 126 PAD_CTL_HYS | PAD_CTL_PKE), 127 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 128 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 129 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 130 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 131 PAD_CTL_HYS | PAD_CTL_PKE), 132 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 133 PAD_CTL_HYS | PAD_CTL_PKE), 134 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 135 PAD_CTL_HYS | PAD_CTL_PKE), 136 }; 137 138 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 139 } 140 141 #ifdef CONFIG_FSL_ESDHC 142 struct fsl_esdhc_cfg esdhc_cfg[2] = { 143 {MMC_SDHC1_BASE_ADDR}, 144 {MMC_SDHC3_BASE_ADDR}, 145 }; 146 147 int board_mmc_getcd(struct mmc *mmc) 148 { 149 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 150 int ret; 151 152 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); 153 gpio_direction_input(IMX_GPIO_NR(3, 11)); 154 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); 155 gpio_direction_input(IMX_GPIO_NR(3, 13)); 156 157 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 158 ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); 159 else 160 ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); 161 162 return ret; 163 } 164 165 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 166 PAD_CTL_PUS_100K_UP) 167 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 168 PAD_CTL_DSE_HIGH) 169 170 int board_mmc_init(bd_t *bis) 171 { 172 static const iomux_v3_cfg_t sd1_pads[] = { 173 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 174 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 175 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 176 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 177 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 178 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 179 MX53_PAD_EIM_DA13__GPIO3_13, 180 }; 181 182 static const iomux_v3_cfg_t sd2_pads[] = { 183 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, 184 SD_CMD_PAD_CTRL), 185 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), 186 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), 187 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), 188 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), 189 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), 190 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), 191 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), 192 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), 193 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), 194 MX53_PAD_EIM_DA11__GPIO3_11, 195 }; 196 197 u32 index; 198 int ret; 199 200 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 201 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 202 203 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 204 switch (index) { 205 case 0: 206 imx_iomux_v3_setup_multiple_pads(sd1_pads, 207 ARRAY_SIZE(sd1_pads)); 208 break; 209 case 1: 210 imx_iomux_v3_setup_multiple_pads(sd2_pads, 211 ARRAY_SIZE(sd2_pads)); 212 break; 213 default: 214 printf("Warning: you configured more ESDHC controller" 215 "(%d) as supported by the board(2)\n", 216 CONFIG_SYS_FSL_ESDHC_NUM); 217 return -EINVAL; 218 } 219 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 220 if (ret) 221 return ret; 222 } 223 224 return 0; 225 } 226 #endif 227 228 int board_early_init_f(void) 229 { 230 setup_iomux_uart(); 231 setup_iomux_fec(); 232 233 return 0; 234 } 235 236 int board_init(void) 237 { 238 /* address of boot parameters */ 239 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 240 241 return 0; 242 } 243 244 #ifdef CONFIG_CMD_BMODE 245 static const struct boot_mode board_boot_modes[] = { 246 /* 4 bit bus width */ 247 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, 248 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, 249 {NULL, 0}, 250 }; 251 #endif 252 253 int board_late_init(void) 254 { 255 setup_i2c(1); 256 power_init(); 257 258 #ifdef CONFIG_CMD_BMODE 259 add_board_boot_modes(board_boot_modes); 260 #endif 261 return 0; 262 } 263 264 int checkboard(void) 265 { 266 puts("Board: MX53EVK\n"); 267 268 return 0; 269 } 270