1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/processor.h> 9 #include <asm/mmu.h> 10 #include <asm/fsl_law.h> 11 #include <asm/io.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #ifdef CONFIG_A003399_NOR_WORKAROUND 16 void setup_ifc(void) 17 { 18 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; 19 u32 _mas0, _mas1, _mas2, _mas3, _mas7; 20 phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; 21 22 /* 23 * Adjust the TLB we were running out of to match the phys addr of the 24 * chip select we are adjusting and will return to. 25 */ 26 flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; 27 28 _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); 29 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | 30 MAS1_TSIZE(BOOKE_PAGESZ_4M); 31 _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); 32 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); 33 _mas7 = FSL_BOOKE_MAS7(flash_phys); 34 35 mtspr(MAS0, _mas0); 36 mtspr(MAS1, _mas1); 37 mtspr(MAS2, _mas2); 38 mtspr(MAS3, _mas3); 39 mtspr(MAS7, _mas7); 40 41 asm volatile("isync;msync;tlbwe;isync"); 42 43 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) 44 /* 45 * TLB entry for debuggging in AS1 46 * Create temporary TLB entry in AS0 to handle debug exception 47 * As on debug exception MSR is cleared i.e. Address space is changed 48 * to 0. A TLB entry (in AS0) is required to handle debug exception generated 49 * in AS1. 50 * 51 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 52 * bacause flash's physical address is going to change as 53 * CONFIG_SYS_FLASH_BASE_PHYS. 54 */ 55 _mas0 = MAS0_TLBSEL(1) | 56 MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); 57 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | 58 MAS1_TSIZE(BOOKE_PAGESZ_4M); 59 _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); 60 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); 61 _mas7 = FSL_BOOKE_MAS7(flash_phys); 62 63 mtspr(MAS0, _mas0); 64 mtspr(MAS1, _mas1); 65 mtspr(MAS2, _mas2); 66 mtspr(MAS3, _mas3); 67 mtspr(MAS7, _mas7); 68 69 asm volatile("isync;msync;tlbwe;isync"); 70 #endif 71 72 /* Change flash's physical address */ 73 ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); 74 ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0); 75 ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0); 76 77 return ; 78 } 79 #endif 80 81 /* We run cpu_init_early_f in AS = 1 */ 82 void cpu_init_early_f(void *fdt) 83 { 84 u32 mas0, mas1, mas2, mas3, mas7; 85 int i; 86 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 87 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88 #endif 89 #ifdef CONFIG_A003399_NOR_WORKAROUND 90 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 91 u32 *dst, *src; 92 void (*setup_ifc_sram)(void); 93 #endif 94 95 /* Pointer is writable since we allocated a register for it */ 96 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 97 98 /* 99 * Clear initial global data 100 * we don't use memset so we can share this code with NAND_SPL 101 */ 102 for (i = 0; i < sizeof(gd_t); i++) 103 ((char *)gd)[i] = 0; 104 105 #ifdef CONFIG_QEMU_E500 106 /* 107 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, 108 * so we need to populate it before it accesses it. 109 */ 110 gd->fdt_blob = fdt; 111 #endif 112 113 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); 114 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); 115 mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); 116 mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); 117 mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); 118 119 write_tlb(mas0, mas1, mas2, mas3, mas7); 120 121 /* 122 * Work Around for IFC Erratum A-003549. This issue is P1010 123 * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC 124 * Hence specifically selecting CS3. 125 */ 126 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 127 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); 128 #endif 129 130 init_laws(); 131 132 /* 133 * Work Around for IFC Erratum A003399, issue will hit only when execution 134 * from NOR Flash 135 */ 136 #ifdef CONFIG_A003399_NOR_WORKAROUND 137 #define SRAM_BASE_ADDR (0x00000000) 138 /* TLB for SRAM */ 139 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); 140 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | 141 MAS1_TSIZE(BOOKE_PAGESZ_1M); 142 mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); 143 mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); 144 mas7 = FSL_BOOKE_MAS7(0); 145 146 write_tlb(mas0, mas1, mas2, mas3, mas7); 147 148 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); 149 150 out_be32(&l2cache->l2errdis, 151 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); 152 153 out_be32(&l2cache->l2ctl, 154 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); 155 156 /* 157 * Copy the code in setup_ifc to L2SRAM. Do a word copy 158 * because NOR Flash on P1010 does not support byte 159 * access (Erratum IFC-A002769) 160 */ 161 setup_ifc_sram = (void *)SRAM_BASE_ADDR; 162 dst = (u32 *) SRAM_BASE_ADDR; 163 src = (u32 *) setup_ifc; 164 for (i = 0; i < 1024; i++) { 165 /* cppcheck-suppress nullPointer */ 166 *dst++ = *src++; 167 } 168 169 /* cppcheck-suppress nullPointer */ 170 setup_ifc_sram(); 171 172 /* CLEANUP */ 173 clrbits_be32(&l2cache->l2ctl, 174 (MPC85xx_L2CTL_L2E | 175 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 176 out_be32(&l2cache->l2srbar0, 0x0); 177 #endif 178 179 invalidate_tlb(1); 180 181 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \ 182 !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ 183 !defined(CONFIG_NAND_SPL) 184 disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); 185 #endif 186 187 init_tlbs(); 188 } 189