1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2011
4  * Marvell Semiconductor <www.marvell.com>
5  * Written-by: Lei Wen <leiwen@marvell.com>
6  */
7 
8 /*
9  * This file should be included in board config header file.
10  *
11  * It supports common definitions for Kirkwood platform
12  */
13 
14 #ifndef _KW_CONFIG_H
15 #define _KW_CONFIG_H
16 
17 #if defined (CONFIG_KW88F6281)
18 #include <asm/arch/kw88f6281.h>
19 #elif defined (CONFIG_KW88F6192)
20 #include <asm/arch/kw88f6192.h>
21 #else
22 #error "SOC Name not defined"
23 #endif /* CONFIG_KW88F6281 */
24 
25 #include <asm/arch/soc.h>
26 #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
27 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
28 #define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
29 
30 /*
31  * By default kwbimage.cfg from board specific folder is used
32  * If for some board, different configuration file need to be used,
33  * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
34  */
35 #ifndef CONFIG_SYS_KWD_CONFIG
36 #define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
37 #endif /* CONFIG_SYS_KWD_CONFIG */
38 
39 /* Kirkwood has 2k of Security SRAM, use it for SP */
40 #define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
41 
42 #define CONFIG_I2C_MVTWSI_BASE0	KW_TWSI_BASE
43 #define MV_UART_CONSOLE_BASE	KW_UART0_BASE
44 #define MV_SATA_BASE		KW_SATA_BASE
45 #define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
46 #define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET
47 
48 /*
49  * NAND configuration
50  */
51 #ifdef CONFIG_CMD_NAND
52 #define CONFIG_NAND_KIRKWOOD
53 #define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
54 #define NAND_ALLOW_ERASE_ALL		1
55 #endif
56 
57 /*
58  * SPI Flash configuration
59  */
60 #ifdef CONFIG_CMD_SF
61 #ifndef CONFIG_ENV_SPI_BUS
62 # define CONFIG_ENV_SPI_BUS		0
63 #endif
64 #ifndef CONFIG_ENV_SPI_CS
65 # define CONFIG_ENV_SPI_CS		0
66 #endif
67 #ifndef CONFIG_ENV_SPI_MAX_HZ
68 # define CONFIG_ENV_SPI_MAX_HZ		50000000
69 #endif
70 #endif
71 
72 /*
73  * Ethernet Driver configuration
74  */
75 #ifdef CONFIG_CMD_NET
76 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
77 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
78 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
79 #define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
80 #endif /* CONFIG_CMD_NET */
81 
82 /*
83  * USB/EHCI
84  */
85 #ifdef CONFIG_CMD_USB
86 #define CONFIG_EHCI_IS_TDI
87 #endif /* CONFIG_CMD_USB */
88 
89 /*
90  * IDE Support on SATA ports
91  */
92 #ifdef CONFIG_IDE
93 #define __io
94 #define CONFIG_IDE_PREINIT
95 #define CONFIG_MVSATA_IDE_USE_PORT1
96 /* Needs byte-swapping for ATA data register */
97 #define CONFIG_IDE_SWAP_IO
98 /* Data, registers and alternate blocks are at the same offset */
99 #define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
100 #define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
101 #define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
102 /* Each 8-bit ATA register is aligned to a 4-bytes address */
103 #define CONFIG_SYS_ATA_STRIDE		4
104 /* Controller supports 48-bits LBA addressing */
105 #define CONFIG_LBA48
106 /* CONFIG_IDE requires some #defines for ATA registers */
107 #define CONFIG_SYS_IDE_MAXBUS		2
108 #define CONFIG_SYS_IDE_MAXDEVICE	2
109 /* ATA registers base is at SATA controller base */
110 #define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
111 #endif /* CONFIG_IDE */
112 
113 /*
114  * I2C related stuff
115  */
116 #if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
117 #ifndef CONFIG_SYS_I2C_SOFT
118 #define CONFIG_SYS_I2C
119 #define CONFIG_SYS_I2C_MVTWSI
120 #endif
121 #define CONFIG_SYS_I2C_SLAVE		0x0
122 #define CONFIG_SYS_I2C_SPEED		100000
123 #endif
124 
125 /* Use common timer */
126 #define CONFIG_SYS_TIMER_COUNTS_DOWN
127 #define CONFIG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
128 #define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_TCLK
129 
130 #endif /* _KW_CONFIG_H */
131