1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <netdev.h> 11 #include <malloc.h> 12 #include <fsl_mdio.h> 13 #include <miiphy.h> 14 #include <phy.h> 15 #include <fm_eth.h> 16 #include <asm/io.h> 17 #include <exports.h> 18 #include <asm/arch/fsl_serdes.h> 19 #include <fsl-mc/fsl_mc.h> 20 #include <fsl-mc/ldpaa_wriop.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int board_eth_init(bd_t *bis) 25 { 26 #if defined(CONFIG_FSL_MC_ENET) 27 int i, interface; 28 struct memac_mdio_info mdio_info; 29 struct mii_dev *dev; 30 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 31 u32 srds_s1; 32 struct memac_mdio_controller *reg; 33 34 srds_s1 = in_le32(&gur->rcwsr[28]) & 35 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; 36 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; 37 38 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; 39 mdio_info.regs = reg; 40 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; 41 42 /* Register the EMI 1 */ 43 fm_memac_mdio_init(bis, &mdio_info); 44 45 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; 46 mdio_info.regs = reg; 47 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; 48 49 /* Register the EMI 2 */ 50 fm_memac_mdio_init(bis, &mdio_info); 51 52 switch (srds_s1) { 53 case 0x2A: 54 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); 55 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); 56 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); 57 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); 58 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); 59 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); 60 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); 61 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); 62 63 break; 64 case 0x4B: 65 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); 66 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); 67 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); 68 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); 69 70 break; 71 default: 72 printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", 73 srds_s1); 74 break; 75 } 76 77 for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) { 78 interface = wriop_get_enet_if(i); 79 switch (interface) { 80 case PHY_INTERFACE_MODE_XGMII: 81 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 82 wriop_set_mdio(i, dev); 83 break; 84 default: 85 break; 86 } 87 } 88 89 for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) { 90 switch (wriop_get_enet_if(i)) { 91 case PHY_INTERFACE_MODE_XGMII: 92 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 93 wriop_set_mdio(i, dev); 94 break; 95 default: 96 break; 97 } 98 } 99 100 cpu_eth_init(bis); 101 #endif /* CONFIG_FSL_MC_ENET */ 102 103 #ifdef CONFIG_PHY_AQUANTIA 104 /* 105 * Export functions to be used by AQ firmware 106 * upload application 107 */ 108 gd->jt->strcpy = strcpy; 109 gd->jt->mdelay = mdelay; 110 gd->jt->mdio_get_current_dev = mdio_get_current_dev; 111 gd->jt->phy_find_by_mask = phy_find_by_mask; 112 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; 113 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; 114 #endif 115 return pci_eth_init(bis); 116 } 117 118 #if defined(CONFIG_RESET_PHY_R) 119 void reset_phy(void) 120 { 121 mc_env_boot(); 122 } 123 #endif /* CONFIG_RESET_PHY_R */ 124