1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor 4 */ 5 6 #ifndef __LS1043A_COMMON_H 7 #define __LS1043A_COMMON_H 8 9 /* SPL build */ 10 #ifdef CONFIG_SPL_BUILD 11 #define SPL_NO_FMAN 12 #define SPL_NO_DSPI 13 #define SPL_NO_PCIE 14 #define SPL_NO_ENV 15 #define SPL_NO_MISC 16 #define SPL_NO_USB 17 #define SPL_NO_SATA 18 #define SPL_NO_QE 19 #define SPL_NO_EEPROM 20 #endif 21 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 22 #define SPL_NO_MMC 23 #endif 24 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) 25 #define SPL_NO_IFC 26 #endif 27 28 #define CONFIG_REMAKE_ELF 29 #define CONFIG_FSL_LAYERSCAPE 30 #define CONFIG_GICV2 31 32 #include <asm/arch/stream_id_lsch2.h> 33 #include <asm/arch/config.h> 34 35 /* Link Definitions */ 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 37 38 #define CONFIG_SKIP_LOWLEVEL_INIT 39 40 #define CONFIG_VERY_BIG_RAM 41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 42 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 44 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 45 46 #define CPU_RELEASE_ADDR secondary_boot_func 47 48 /* Generic Timer Definitions */ 49 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 50 51 /* Size of malloc() pool */ 52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 53 54 /* Serial Port */ 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE 1 57 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 58 59 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 60 61 /* SD boot SPL */ 62 #ifdef CONFIG_SD_BOOT 63 64 #define CONFIG_SPL_TEXT_BASE 0x10000000 65 #define CONFIG_SPL_MAX_SIZE 0x17000 66 #define CONFIG_SPL_STACK 0x1001e000 67 #define CONFIG_SPL_PAD_TO 0x1d000 68 69 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 70 CONFIG_SPL_BSS_MAX_SIZE) 71 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 72 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 73 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 74 75 #ifdef CONFIG_SECURE_BOOT 76 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 77 /* 78 * HDR would be appended at end of image and copied to DDR along 79 * with U-Boot image. Here u-boot max. size is 512K. So if binary 80 * size increases then increase this size in case of secure boot as 81 * it uses raw u-boot image instead of fit image. 82 */ 83 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 84 #else 85 #define CONFIG_SYS_MONITOR_LEN 0x100000 86 #endif /* ifdef CONFIG_SECURE_BOOT */ 87 #endif 88 89 /* NAND SPL */ 90 #ifdef CONFIG_NAND_BOOT 91 #define CONFIG_SPL_PBL_PAD 92 #define CONFIG_SPL_TEXT_BASE 0x10000000 93 #define CONFIG_SPL_MAX_SIZE 0x1a000 94 #define CONFIG_SPL_STACK 0x1001d000 95 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 96 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 97 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 98 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 99 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 100 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 101 102 #ifdef CONFIG_SECURE_BOOT 103 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 104 #endif /* ifdef CONFIG_SECURE_BOOT */ 105 106 #ifdef CONFIG_U_BOOT_HDR_SIZE 107 /* 108 * HDR would be appended at end of image and copied to DDR along 109 * with U-Boot image. Here u-boot max. size is 512K. So if binary 110 * size increases then increase this size in case of secure boot as 111 * it uses raw u-boot image instead of fit image. 112 */ 113 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 114 #else 115 #define CONFIG_SYS_MONITOR_LEN 0x100000 116 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 117 118 #endif 119 120 /* IFC */ 121 #ifndef SPL_NO_IFC 122 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 123 #define CONFIG_FSL_IFC 124 /* 125 * CONFIG_SYS_FLASH_BASE has the final address (core view) 126 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 127 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 128 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 129 */ 130 #define CONFIG_SYS_FLASH_BASE 0x60000000 131 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 132 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 133 134 #ifdef CONFIG_MTD_NOR_FLASH 135 #define CONFIG_SYS_FLASH_QUIET_TEST 136 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 137 #endif 138 #endif 139 #endif 140 141 /* I2C */ 142 #define CONFIG_SYS_I2C 143 144 /* PCIe */ 145 #ifndef SPL_NO_PCIE 146 #define CONFIG_PCIE1 /* PCIE controller 1 */ 147 #define CONFIG_PCIE2 /* PCIE controller 2 */ 148 #define CONFIG_PCIE3 /* PCIE controller 3 */ 149 150 #ifdef CONFIG_PCI 151 #define CONFIG_PCI_SCAN_SHOW 152 #endif 153 #endif 154 155 /* Command line configuration */ 156 157 /* MMC */ 158 #ifndef SPL_NO_MMC 159 #ifdef CONFIG_MMC 160 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 161 #endif 162 #endif 163 164 /* DSPI */ 165 #ifndef SPL_NO_DSPI 166 #define CONFIG_FSL_DSPI 167 #ifdef CONFIG_FSL_DSPI 168 #define CONFIG_DM_SPI_FLASH 169 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 170 #define CONFIG_SPI_FLASH_SST /* cs1 */ 171 #define CONFIG_SPI_FLASH_EON /* cs2 */ 172 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 173 #define CONFIG_SF_DEFAULT_BUS 1 174 #define CONFIG_SF_DEFAULT_CS 0 175 #endif 176 #endif 177 #endif 178 179 /* FMan ucode */ 180 #ifndef SPL_NO_FMAN 181 #define CONFIG_SYS_DPAA_FMAN 182 #ifdef CONFIG_SYS_DPAA_FMAN 183 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 184 185 #ifdef CONFIG_NAND_BOOT 186 /* Store Fman ucode at offeset 0x900000(72 blocks). */ 187 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 188 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) 189 #elif defined(CONFIG_SD_BOOT) 190 /* 191 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 192 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 193 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). 194 */ 195 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 196 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 197 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) 198 #elif defined(CONFIG_QSPI_BOOT) 199 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 200 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 201 #define CONFIG_ENV_SPI_BUS 0 202 #define CONFIG_ENV_SPI_CS 0 203 #define CONFIG_ENV_SPI_MAX_HZ 1000000 204 #define CONFIG_ENV_SPI_MODE 0x03 205 #else 206 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 207 /* FMan fireware Pre-load address */ 208 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 209 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 210 #endif 211 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 212 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 213 #endif 214 #endif 215 216 /* Miscellaneous configurable options */ 217 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 218 219 #define CONFIG_HWCONFIG 220 #define HWCONFIG_BUFFER_SIZE 128 221 222 #ifndef SPL_NO_MISC 223 #ifndef CONFIG_SPL_BUILD 224 #define BOOT_TARGET_DEVICES(func) \ 225 func(MMC, mmc, 0) \ 226 func(USB, usb, 0) 227 #include <config_distro_bootcmd.h> 228 #endif 229 230 /* Initial environment variables */ 231 #define CONFIG_EXTRA_ENV_SETTINGS \ 232 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 233 "fdt_high=0xffffffffffffffff\0" \ 234 "initrd_high=0xffffffffffffffff\0" \ 235 "fdt_addr=0x64f00000\0" \ 236 "kernel_addr=0x61000000\0" \ 237 "scriptaddr=0x80000000\0" \ 238 "scripthdraddr=0x80080000\0" \ 239 "fdtheader_addr_r=0x80100000\0" \ 240 "kernelheader_addr_r=0x80200000\0" \ 241 "kernel_addr_r=0x81000000\0" \ 242 "fdt_addr_r=0x90000000\0" \ 243 "load_addr=0xa0000000\0" \ 244 "kernelheader_addr=0x60800000\0" \ 245 "kernel_size=0x2800000\0" \ 246 "kernelheader_size=0x40000\0" \ 247 "kernel_addr_sd=0x8000\0" \ 248 "kernel_size_sd=0x14000\0" \ 249 "kernelhdr_addr_sd=0x4000\0" \ 250 "kernelhdr_size_sd=0x10\0" \ 251 "console=ttyS0,115200\0" \ 252 "boot_os=y\0" \ 253 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 254 BOOTENV \ 255 "boot_scripts=ls1043ardb_boot.scr\0" \ 256 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ 257 "scan_dev_for_boot_part=" \ 258 "part list ${devtype} ${devnum} devplist; " \ 259 "env exists devplist || setenv devplist 1; " \ 260 "for distro_bootpart in ${devplist}; do " \ 261 "if fstype ${devtype} " \ 262 "${devnum}:${distro_bootpart} " \ 263 "bootfstype; then " \ 264 "run scan_dev_for_boot; " \ 265 "fi; " \ 266 "done\0" \ 267 "scan_dev_for_boot=" \ 268 "echo Scanning ${devtype} " \ 269 "${devnum}:${distro_bootpart}...; " \ 270 "for prefix in ${boot_prefixes}; do " \ 271 "run scan_dev_for_scripts; " \ 272 "done;\0" \ 273 "boot_a_script=" \ 274 "load ${devtype} ${devnum}:${distro_bootpart} " \ 275 "${scriptaddr} ${prefix}${script}; " \ 276 "env exists secureboot && load ${devtype} " \ 277 "${devnum}:${distro_bootpart} " \ 278 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 279 "&& esbc_validate ${scripthdraddr};" \ 280 "source ${scriptaddr}\0" \ 281 "qspi_bootcmd=echo Trying load from qspi..;" \ 282 "sf probe && sf read $load_addr " \ 283 "$kernel_addr $kernel_size; env exists secureboot " \ 284 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 285 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 286 "bootm $load_addr#$board\0" \ 287 "nor_bootcmd=echo Trying load from nor..;" \ 288 "cp.b $kernel_addr $load_addr " \ 289 "$kernel_size; env exists secureboot " \ 290 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 291 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 292 "bootm $load_addr#$board\0" \ 293 "sd_bootcmd=echo Trying load from SD ..;" \ 294 "mmcinfo; mmc read $load_addr " \ 295 "$kernel_addr_sd $kernel_size_sd && " \ 296 "env exists secureboot && mmc read $kernelheader_addr_r " \ 297 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 298 " && esbc_validate ${kernelheader_addr_r};" \ 299 "bootm $load_addr#$board\0" 300 301 302 #undef CONFIG_BOOTCOMMAND 303 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 304 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 305 "env exists secureboot && esbc_halt;" 306 #elif defined(CONFIG_SD_BOOT) 307 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 308 "env exists secureboot && esbc_halt;" 309 #else 310 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 311 "env exists secureboot && esbc_halt;" 312 #endif 313 #endif 314 315 /* Monitor Command Prompt */ 316 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 317 318 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 319 320 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 321 322 #include <asm/arch/soc.h> 323 324 #endif /* __LS1043A_COMMON_H */ 325