1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc 5 */ 6 7 /** 8 * enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0) 9 * @SRDSCR0_DPPA: Bitmask for the DPPA (diff pk-pk swing for lane A) 10 * field of the SRCSCR0 11 * @SRDSCR0_DPPE: Bitmask for the DPPE (diff pk-pk swing for lane E) 12 * field of the SRCSCR0 13 * @SRDSCR0_DPP_1V2: Combined bitmask to set diff pk-pk swing for both lanes 14 * @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for 15 * lane A) field of the SRCSCR0 16 * @SRDSCR0_TXEQA_SATA: Bitmask to set the TXEQA to the value used for SATA 17 * @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for 18 * lane E) field of the SRCSCR0 19 * @SRDSCR0_TXEQE_SATA: Bitmask to set the TXEQE to the value used for SATA 20 */ 21 enum srdscr0_mask { 22 SRDSCR0_DPPA = BIT(31 - 16), 23 SRDSCR0_DPPE = BIT(31 - 20), 24 SRDSCR0_DPP_1V2 = SRDSCR0_DPPE | SRDSCR0_DPPA, 25 26 SRDSCR0_TXEQA_MASK = 0x00007000, 27 SRDSCR0_TXEQA_SATA = 0x00001000, 28 SRDSCR0_TXEQE_MASK = 0x00000700, 29 SRDSCR0_TXEQE_SATA = 0x00000100, 30 }; 31 32 /** 33 * enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1) 34 * @SRDSCR1_PLLBW: Bitmask for the PLLBW (PLL bandwidth) field of SRDSCR1 35 */ 36 enum srdscr1_mask { 37 SRDSCR1_PLLBW = BIT(31 - 25), 38 }; 39 40 /** 41 * enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2) 42 * @SRDSCR2_VDD_1V2: Bit mask to to set the VDD field of the SCRSCR2 43 * @SRDSCR2_SEICA_MASK: Bitmask for the SEICA (Receiver electrical idle 44 * detection control for lane A) field of the SRCSCR2 45 * @SRDSCR2_SEICE_MASK: Bitmask for the SEICE (Receiver electrical idle 46 * detection control for lane E) field of the SRCSCR2 47 * @SRDSCR2_SEIC_MASK: Combined bitmask to set the receiver electrical idle 48 * detection control for both lanes 49 * @SRDSCR2_SEICA_SATA: Bitmask to set the SEICA field to the value used for 50 * SATA 51 * @SRDSCR2_SEICE_SATA: Bitmask to set the SEICE field to the value used for 52 * SATA 53 * @SRDSCR2_SEIC_SATA: Combined bitmask to set the value of both SEIC fields 54 * to the value used for SATA 55 * @SRDSCR2_SEICA_PEX: Bitmask to set the SEICA field to the value used for 56 * PCI Express 57 * @SRDSCR2_SEICE_PEX: Bitmask to set the SEICE field to the value used for 58 * PCI Express 59 * @SRDSCR2_SEIC_PEX: Combined bitmask to set the value of both SEIC fields 60 * to the value used for PCI Express 61 * @SRDSCR2_SEICA_SGMII: Bitmask to set the SEICA field to the value used for 62 * SGMII 63 * @SRDSCR2_SEICE_SGMII: Bitmask to set the SEICE field to the value used for 64 * SGMII 65 * @SRDSCR2_SEIC_SGMII: Combined bitmask to set the value of both SEIC fields 66 * to the value used for SGMII 67 */ 68 enum srdscr2_mask { 69 SRDSCR2_VDD_1V2 = 0x00800000, 70 71 SRDSCR2_SEICA_MASK = 0x00001c00, 72 SRDSCR2_SEICE_MASK = 0x0000001c, 73 SRDSCR2_SEIC_MASK = SRDSCR2_SEICA_MASK | SRDSCR2_SEICE_MASK, 74 75 SRDSCR2_SEICA_SATA = 0x00001400, 76 SRDSCR2_SEICE_SATA = 0x00000014, 77 SRDSCR2_SEIC_SATA = SRDSCR2_SEICA_SATA | SRDSCR2_SEICE_SATA, 78 79 SRDSCR2_SEICA_PEX = 0x00001000, 80 SRDSCR2_SEICE_PEX = 0x00000010, 81 SRDSCR2_SEIC_PEX = SRDSCR2_SEICA_PEX | SRDSCR2_SEICE_PEX, 82 83 SRDSCR2_SEICA_SGMII = 0x00000100, 84 SRDSCR2_SEICE_SGMII = 0x00000001, 85 SRDSCR2_SEIC_SGMII = SRDSCR2_SEICA_SGMII | SRDSCR2_SEICE_SGMII, 86 }; 87 88 /** 89 * enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3) 90 * @SRDSCR3_KFRA_SATA: Bitmask to set the KFRA field of SRDSCR3 to the 91 * value used by SATA 92 * @SRDSCR3_KFRE_SATA: Bitmask to set the KFRE field of SRDSCR3 to the 93 * value used by SATA 94 * @SRDSCR3_KFR_SATA: Combined bitmask to set both KFR fields to the 95 * value used by SATA 96 * @SRDSCR3_KPHA_SATA: Bitmask to set the KPHA field of SRDSCR3 to the 97 * value used by SATA 98 * @SRDSCR3_KPHE_SATA: Bitmask to set the KPHE field of SRDSCR3 to the 99 * value used by SATA 100 * @SRDSCR3_KPH_SATA: Combined bitmask to set both KPH fields to the 101 * value used by SATA 102 * @SRDSCR3_SDFMA_SATA_PEX: Bitmask to set the SDFMA field of SRDSCR3 to the 103 * value used by SATA and PCI Express 104 * @SRDSCR3_SDFME_SATA_PEX: Bitmask to set the SDFME field of SRDSCR3 to the 105 * value used by SATA and PCI Express 106 * @SRDSCR3_SDFM_SATA_PEX: Combined bitmask to set both SDFM fields to the 107 * value used by SATA and PCI Express 108 * @SRDSCR3_SDTXLA_SATA: Bitmask to set the SDTXLA field of SRDSCR3 to the 109 * value used by SATA 110 * @SRDSCR3_SDTXLE_SATA: Bitmask to set the SDTXLE field of SRDSCR3 to the 111 * value used by SATA 112 * @SRDSCR3_SDTXL_SATA: Combined bitmask to set both SDTXL fields to the 113 * value used by SATA 114 * 115 * KFRA = 'Kfr' gain selection in the CDR for lane A 116 * KFRE = 'Kfr' gain selection in the CDR for lane E 117 * SDFMA = Bandwidth of digital filter for lane A 118 * SDFME = Bandwidth of digital filter for lane E 119 * SDTXLA = Lane A transmitter amplitude levels 120 * SDTXLE = Lane E transmitter amplitude levels 121 */ 122 enum srdscr3_mask { 123 SRDSCR3_KFRA_SATA = 0x10000000, 124 SRDSCR3_KFRE_SATA = 0x00100000, 125 SRDSCR3_KFR_SATA = SRDSCR3_KFRA_SATA | SRDSCR3_KFRE_SATA, 126 127 SRDSCR3_KPHA_SATA = 0x04000000, 128 SRDSCR3_KPHE_SATA = 0x00040000, 129 SRDSCR3_KPH_SATA = SRDSCR3_KPHA_SATA | SRDSCR3_KPHE_SATA, 130 131 SRDSCR3_SDFMA_SATA_PEX = 0x01000000, 132 SRDSCR3_SDFME_SATA_PEX = 0x00010000, 133 SRDSCR3_SDFM_SATA_PEX = SRDSCR3_SDFMA_SATA_PEX | SRDSCR3_SDFME_SATA_PEX, 134 135 SRDSCR3_SDTXLA_SATA = 0x00000500, 136 SRDSCR3_SDTXLE_SATA = 0x00000005, 137 SRDSCR3_SDTXL_SATA = SRDSCR3_SDTXLA_SATA | SRDSCR3_SDTXLE_SATA, 138 }; 139 140 /** 141 * enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4) 142 * @SRDSCR4_PROTA_SATA: Bitmask to set the PROTA field of SRDSCR4 to the 143 * value used by SATA 144 * @SRDSCR4_PROTE_SATA: Bitmask to set the PROTE field of SRDSCR4 to the 145 * value used by SATA 146 * @SRDSCR4_PROT_SATA: Combined bitmask to set both PROT fields to the 147 * value used by SATA 148 * @SRDSCR4_PROTA_PEX: Bitmask to set the PROTA field of SRDSCR4 to the 149 * value used by PCI Express 150 * @SRDSCR4_PROTE_PEX: Bitmask to set the PROTE field of SRDSCR4 to the 151 * value used by PCI Express 152 * @SRDSCR4_PROT_PEX: Combined bitmask to set both PROT fields to the 153 * value used by PCI Express 154 * @SRDSCR4_PROTA_SGMII: Bitmask to set the PROTA field of SRDSCR4 to the 155 * value used by SGMII 156 * @SRDSCR4_PROTE_SGMII: Bitmask to set the PROTE field of SRDSCR4 to the 157 * value used by SGMII 158 * @SRDSCR4_PROT_SGMII: Combined bitmask to set both PROT fields to the 159 * value used by SGMII 160 * @SRDSCR4_PLANE_X2: Bitmask to set the PLANE field of SRDSCR4 161 * @SRDSCR4_RFCKS_100: Bitmask to set the RFCKS field of SRDSCR4 to the 162 * value 100Mhz 163 * @SRDSCR4_RFCKS_125: Bitmask to set the RFCKS field of SRDSCR4 to the 164 * value 125Mhz 165 * @SRDSCR4_RFCKS_150: Bitmask to set the RFCKS field of SRDSCR4 to the 166 * value 150Mhz 167 * 168 * PROTA = Lane A protocol select 169 * PROTE = Lane E protocol select 170 * PLAME = Number of PCI Express lanes 171 */ 172 enum srdscr4_mask { 173 SRDSCR4_PROTA_SATA = 0x00000800, 174 SRDSCR4_PROTE_SATA = 0x00000008, 175 SRDSCR4_PROT_SATA = SRDSCR4_PROTA_SATA | SRDSCR4_PROTE_SATA, 176 177 SRDSCR4_PROTA_PEX = 0x00000100, 178 SRDSCR4_PROTE_PEX = 0x00000001, 179 SRDSCR4_PROT_PEX = SRDSCR4_PROTA_PEX | SRDSCR4_PROTE_PEX, 180 181 SRDSCR4_PROTA_SGMII = 0x00000500, 182 SRDSCR4_PROTE_SGMII = 0x00000005, 183 SRDSCR4_PROT_SGMII = SRDSCR4_PROTA_SGMII | SRDSCR4_PROTE_SGMII, 184 185 SRDSCR4_PLANE_X2 = 0x01000000, 186 187 SRDSCR4_RFCKS_100 = (0 << 28), 188 SRDSCR4_RFCKS_125 = (1 << 28), 189 SRDSCR4_RFCKS_150 = (3 << 28), 190 }; 191 192 /** 193 * enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register) 194 * @SRDSRSTCTL_RST: Bitmask for the RST (Software reset) field of the 195 * SRDSRSTCTL 196 * @SRDSRSTCTL_SATA_RESET: Bitmask for the SATA_RESET (SATA reset) field of the 197 * SRDSRSTCTL 198 */ 199 enum srdsrstctl_mask { 200 SRDSRSTCTL_RST = 0x80000000, 201 SRDSRSTCTL_SATA_RESET = 0xf, 202 }; 203 204 /** 205 * struct mpc83xx_serdes_regs - Register map of the SerDes controller 206 * @srdscr0: SerDes Control Register 0 207 * @srdscr1: SerDes Control Register 1 208 * @srdscr2: SerDes Control Register 2 209 * @srdscr3: SerDes Control Register 3 210 * @srdscr4: SerDes Control Register 4 211 * @fill0: Reserved space in the register map 212 * @srdsrstctl: SerDes Reset Control Register 213 */ 214 struct mpc83xx_serdes_regs { 215 u32 srdscr0; 216 u32 srdscr1; 217 u32 srdscr2; 218 u32 srdscr3; 219 u32 srdscr4; 220 u8 fill0[12]; 221 u32 srdsrstctl; 222 }; 223 224 /** 225 * enum pex_type - Types of PCI Express 226 * @PEX_X1: PCI Express in x1 mode 227 * @PEX_X2: PCI Express in x2 mode 228 */ 229 enum pex_type { 230 PEX_X1, 231 PEX_X2, 232 }; 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