1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <ioports.h> 11 #include <mpc83xx.h> 12 #include <i2c.h> 13 #include <miiphy.h> 14 #include <command.h> 15 #if defined(CONFIG_PCI) 16 #include <pci.h> 17 #endif 18 #include <asm/mmu.h> 19 #if defined(CONFIG_OF_LIBFDT) 20 #include <libfdt.h> 21 #endif 22 #if defined(CONFIG_PQ_MDS_PIB) 23 #include "../common/pq-mds-pib.h" 24 #endif 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 const qe_iop_conf_t qe_iop_conf_tab[] = { 29 /* ETH3 */ 30 {1, 0, 1, 0, 1}, /* TxD0 */ 31 {1, 1, 1, 0, 1}, /* TxD1 */ 32 {1, 2, 1, 0, 1}, /* TxD2 */ 33 {1, 3, 1, 0, 1}, /* TxD3 */ 34 {1, 9, 1, 0, 1}, /* TxER */ 35 {1, 12, 1, 0, 1}, /* TxEN */ 36 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ 37 38 {1, 4, 2, 0, 1}, /* RxD0 */ 39 {1, 5, 2, 0, 1}, /* RxD1 */ 40 {1, 6, 2, 0, 1}, /* RxD2 */ 41 {1, 7, 2, 0, 1}, /* RxD3 */ 42 {1, 8, 2, 0, 1}, /* RxER */ 43 {1, 10, 2, 0, 1}, /* RxDV */ 44 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ 45 {1, 11, 2, 0, 1}, /* COL */ 46 {1, 13, 2, 0, 1}, /* CRS */ 47 48 /* ETH4 */ 49 {1, 18, 1, 0, 1}, /* TxD0 */ 50 {1, 19, 1, 0, 1}, /* TxD1 */ 51 {1, 20, 1, 0, 1}, /* TxD2 */ 52 {1, 21, 1, 0, 1}, /* TxD3 */ 53 {1, 27, 1, 0, 1}, /* TxER */ 54 {1, 30, 1, 0, 1}, /* TxEN */ 55 {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ 56 57 {1, 22, 2, 0, 1}, /* RxD0 */ 58 {1, 23, 2, 0, 1}, /* RxD1 */ 59 {1, 24, 2, 0, 1}, /* RxD2 */ 60 {1, 25, 2, 0, 1}, /* RxD3 */ 61 {1, 26, 1, 0, 1}, /* RxER */ 62 {1, 28, 2, 0, 1}, /* Rx_DV */ 63 {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ 64 {1, 29, 2, 0, 1}, /* COL */ 65 {1, 31, 2, 0, 1}, /* CRS */ 66 67 {3, 4, 3, 0, 2}, /* MDIO */ 68 {3, 5, 1, 0, 2}, /* MDC */ 69 70 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 71 }; 72 73 int board_early_init_f(void) 74 { 75 volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR; 76 77 /* Enable flash write */ 78 bcsr[9] &= ~0x08; 79 80 return 0; 81 } 82 83 int board_early_init_r(void) 84 { 85 #ifdef CONFIG_PQ_MDS_PIB 86 pib_init(); 87 #endif 88 return 0; 89 } 90 91 int fixed_sdram(void); 92 93 int dram_init(void) 94 { 95 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 96 u32 msize = 0; 97 98 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 99 return -ENXIO; 100 101 /* DDR SDRAM - Main SODIMM */ 102 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 103 104 msize = fixed_sdram(); 105 106 /* set total bus SDRAM size(bytes) -- DDR */ 107 gd->ram_size = msize * 1024 * 1024; 108 109 return 0; 110 } 111 112 /************************************************************************* 113 * fixed sdram init -- doesn't use serial presence detect. 114 ************************************************************************/ 115 int fixed_sdram(void) 116 { 117 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 118 u32 msize = 0; 119 u32 ddr_size; 120 u32 ddr_size_log2; 121 122 msize = CONFIG_SYS_DDR_SIZE; 123 for (ddr_size = msize << 20, ddr_size_log2 = 0; 124 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { 125 if (ddr_size & 1) { 126 return -1; 127 } 128 } 129 im->sysconf.ddrlaw[0].ar = 130 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 131 #if (CONFIG_SYS_DDR_SIZE != 128) 132 #warning Currenly any ddr size other than 128 is not supported 133 #endif 134 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 135 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; 136 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 137 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 138 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 139 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 140 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 141 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 142 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 143 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 144 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 145 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 146 __asm__ __volatile__ ("sync"); 147 udelay(200); 148 149 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 150 __asm__ __volatile__ ("sync"); 151 return msize; 152 } 153 154 int checkboard(void) 155 { 156 puts("Board: Freescale MPC832XEMDS\n"); 157 return 0; 158 } 159 160 #if defined(CONFIG_OF_BOARD_SETUP) 161 int ft_board_setup(void *blob, bd_t *bd) 162 { 163 ft_cpu_setup(blob, bd); 164 #ifdef CONFIG_PCI 165 ft_pci_setup(blob, bd); 166 #endif 167 168 return 0; 169 } 170 #endif 171