1 /* 2 * Copyright (c) 2015 Google, Inc 3 * 4 * Copyright 2014 Rockchip Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef _ASM_ARCH_RK3288_SDRAM_H__ 10 #define _ASM_ARCH_RK3288_SDRAM_H__ 11 12 enum { 13 DDR3 = 3, 14 LPDDR3 = 6, 15 UNUSED = 0xFF, 16 }; 17 18 struct rk3288_sdram_channel { 19 /* 20 * bit width in address, eg: 21 * 8 banks using 3 bit to address, 22 * 2 cs using 1 bit to address. 23 */ 24 u8 rank; 25 u8 col; 26 u8 bk; 27 u8 bw; 28 u8 dbw; 29 u8 row_3_4; 30 u8 cs0_row; 31 u8 cs1_row; 32 #if CONFIG_IS_ENABLED(OF_PLATDATA) 33 /* 34 * For of-platdata, which would otherwise convert this into two 35 * byte-swapped integers. With a size of 9 bytes, this struct will 36 * appear in of-platdata as a byte array. 37 * 38 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) 39 */ 40 u8 dummy; 41 #endif 42 }; 43 44 struct rk3288_sdram_pctl_timing { 45 u32 togcnt1u; 46 u32 tinit; 47 u32 trsth; 48 u32 togcnt100n; 49 u32 trefi; 50 u32 tmrd; 51 u32 trfc; 52 u32 trp; 53 u32 trtw; 54 u32 tal; 55 u32 tcl; 56 u32 tcwl; 57 u32 tras; 58 u32 trc; 59 u32 trcd; 60 u32 trrd; 61 u32 trtp; 62 u32 twr; 63 u32 twtr; 64 u32 texsr; 65 u32 txp; 66 u32 txpdll; 67 u32 tzqcs; 68 u32 tzqcsi; 69 u32 tdqs; 70 u32 tcksre; 71 u32 tcksrx; 72 u32 tcke; 73 u32 tmod; 74 u32 trstl; 75 u32 tzqcl; 76 u32 tmrr; 77 u32 tckesr; 78 u32 tdpd; 79 }; 80 check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); 81 82 struct rk3288_sdram_phy_timing { 83 u32 dtpr0; 84 u32 dtpr1; 85 u32 dtpr2; 86 u32 mr[4]; 87 }; 88 89 struct rk3288_base_params { 90 u32 noc_timing; 91 u32 noc_activate; 92 u32 ddrconfig; 93 u32 ddr_freq; 94 u32 dramtype; 95 /* 96 * DDR Stride is address mapping for DRAM space 97 * Stride Ch 0 range Ch1 range Total 98 * 0x00 0-256MB 256MB-512MB 512MB 99 * 0x05 0-1GB 0-1GB 1GB 100 * 0x09 0-2GB 0-2GB 2GB 101 * 0x0d 0-4GB 0-4GB 4GB 102 * 0x17 N/A 0-4GB 4GB 103 * 0x1a 0-4GB 4GB-8GB 8GB 104 */ 105 u32 stride; 106 u32 odt; 107 }; 108 109 #endif 110