1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 #include <asm/hardware.h> 20 21 #define CONFIG_SYS_GENERIC_BOARD 22 23 /* ARM asynchronous clock */ 24 #define CONFIG_DISPLAY_CPUINFO 25 #define CONFIG_DISPLAY_BOARDINFO 26 27 #define MASTER_PLL_DIV 6 28 #define MASTER_PLL_MUL 65 29 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 30 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 31 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 32 33 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 34 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ 35 #define CONFIG_ARCH_CPU_INIT 36 #define CONFIG_SYS_TEXT_BASE 0 37 38 #define MACH_TYPE_PM9263 1475 39 #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 40 41 /* clocks */ 42 #define CONFIG_SYS_MOR_VAL \ 43 (AT91_PMC_MOR_MOSCEN | \ 44 (255 << 8)) /* Main Oscillator Start-up Time */ 45 #define CONFIG_SYS_PLLAR_VAL \ 46 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 47 AT91_PMC_PLLXR_OUT(3) | \ 48 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 49 (2 << 28) | /* PLL Clock Frequency Range */ \ 50 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 51 52 #if (MAIN_PLL_DIV == 2) 53 /* PCK/2 = MCK Master Clock from PLLA */ 54 #define CONFIG_SYS_MCKR1_VAL \ 55 (AT91_PMC_MCKR_CSS_SLOW | \ 56 AT91_PMC_MCKR_PRES_1 | \ 57 AT91_PMC_MCKR_MDIV_2) 58 /* PCK/2 = MCK Master Clock from PLLA */ 59 #define CONFIG_SYS_MCKR2_VAL \ 60 (AT91_PMC_MCKR_CSS_PLLA | \ 61 AT91_PMC_MCKR_PRES_1 | \ 62 AT91_PMC_MCKR_MDIV_2) 63 #else 64 /* PCK/4 = MCK Master Clock from PLLA */ 65 #define CONFIG_SYS_MCKR1_VAL \ 66 (AT91_PMC_MCKR_CSS_SLOW | \ 67 AT91_PMC_MCKR_PRES_1 | \ 68 AT91_PMC_MCKR_MDIV_4) 69 /* PCK/4 = MCK Master Clock from PLLA */ 70 #define CONFIG_SYS_MCKR2_VAL \ 71 (AT91_PMC_MCKR_CSS_PLLA | \ 72 AT91_PMC_MCKR_PRES_1 | \ 73 AT91_PMC_MCKR_MDIV_4) 74 #endif 75 /* define PDC[31:16] as DATA[31:16] */ 76 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 77 /* no pull-up for D[31:16] */ 78 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 79 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 80 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 81 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 82 AT91_MATRIX_CSA_EBI_CS1A) 83 84 /* SDRAM */ 85 /* SDRAMC_MR Mode register */ 86 #define CONFIG_SYS_SDRC_MR_VAL1 0 87 /* SDRAMC_TR - Refresh Timer register */ 88 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 89 /* SDRAMC_CR - Configuration register*/ 90 #define CONFIG_SYS_SDRC_CR_VAL \ 91 (AT91_SDRAMC_NC_9 | \ 92 AT91_SDRAMC_NR_13 | \ 93 AT91_SDRAMC_NB_4 | \ 94 AT91_SDRAMC_CAS_2 | \ 95 AT91_SDRAMC_DBW_32 | \ 96 (2 << 8) | /* tWR - Write Recovery Delay */ \ 97 (7 << 12) | /* tRC - Row Cycle Delay */ \ 98 (2 << 16) | /* tRP - Row Precharge Delay */ \ 99 (2 << 20) | /* tRCD - Row to Column Delay */ \ 100 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 101 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 102 103 /* Memory Device Register -> SDRAM */ 104 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 105 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 106 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 107 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 108 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 109 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 110 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 111 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 112 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 113 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 114 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 115 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 116 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 117 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 118 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 119 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 120 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 121 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 122 123 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 124 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 125 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 126 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 127 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 128 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 129 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 130 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 131 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 132 #define CONFIG_SYS_SMC0_MODE0_VAL \ 133 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 134 AT91_SMC_MODE_DBW_16 | \ 135 AT91_SMC_MODE_TDF | \ 136 AT91_SMC_MODE_TDF_CYCLE(6)) 137 138 /* user reset enable */ 139 #define CONFIG_SYS_RSTC_RMR_VAL \ 140 (AT91_RSTC_KEY | \ 141 AT91_RSTC_CR_PROCRST | \ 142 AT91_RSTC_MR_ERSTL(1) | \ 143 AT91_RSTC_MR_ERSTL(2)) 144 145 /* Disable Watchdog */ 146 #define CONFIG_SYS_WDTC_WDMR_VAL \ 147 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 148 AT91_WDT_MR_WDV(0xfff) | \ 149 AT91_WDT_MR_WDDIS | \ 150 AT91_WDT_MR_WDD(0xfff)) 151 152 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 153 #define CONFIG_SETUP_MEMORY_TAGS 1 154 #define CONFIG_INITRD_TAG 1 155 156 #undef CONFIG_SKIP_LOWLEVEL_INIT 157 #define CONFIG_USER_LOWLEVEL_INIT 1 158 #define CONFIG_BOARD_EARLY_INIT_F 159 160 /* 161 * Hardware drivers 162 */ 163 #define CONFIG_AT91_GPIO 1 164 #define CONFIG_ATMEL_USART 1 165 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 166 #define CONFIG_USART_ID ATMEL_ID_SYS 167 168 /* LCD */ 169 #define CONFIG_LCD 1 170 #define LCD_BPP LCD_COLOR8 171 #define CONFIG_LCD_LOGO 1 172 #undef LCD_TEST_PATTERN 173 #define CONFIG_LCD_INFO 1 174 #define CONFIG_LCD_INFO_BELOW_LOGO 1 175 #define CONFIG_SYS_WHITE_ON_BLACK 1 176 #define CONFIG_ATMEL_LCD 1 177 #define CONFIG_ATMEL_LCD_BGR555 1 178 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 179 180 #define CONFIG_LCD_IN_PSRAM 1 181 182 /* LED */ 183 #define CONFIG_AT91_LED 184 #define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */ 185 #define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */ 186 187 #define CONFIG_BOOTDELAY 3 188 189 /* 190 * BOOTP options 191 */ 192 #define CONFIG_BOOTP_BOOTFILESIZE 1 193 #define CONFIG_BOOTP_BOOTPATH 1 194 #define CONFIG_BOOTP_GATEWAY 1 195 #define CONFIG_BOOTP_HOSTNAME 1 196 197 /* 198 * Command line configuration. 199 */ 200 #define CONFIG_CMD_CACHE 201 #define CONFIG_CMD_PING 1 202 #define CONFIG_CMD_DHCP 1 203 #define CONFIG_CMD_NAND 1 204 #define CONFIG_CMD_USB 1 205 206 /* SDRAM */ 207 #define CONFIG_NR_DRAM_BANKS 1 208 #define PHYS_SDRAM 0x20000000 209 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 210 211 /* DataFlash */ 212 #define CONFIG_ATMEL_DATAFLASH_SPI 213 #define CONFIG_HAS_DATAFLASH 1 214 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 215 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 216 #define AT91_SPI_CLK 15000000 217 #define DATAFLASH_TCSS (0x1a << 16) 218 #define DATAFLASH_TCHS (0x1 << 24) 219 220 /* NOR flash, if populated */ 221 #define CONFIG_SYS_FLASH_CFI 1 222 #define CONFIG_FLASH_CFI_DRIVER 1 223 #define PHYS_FLASH_1 0x10000000 224 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 225 #define CONFIG_SYS_MAX_FLASH_SECT 256 226 #define CONFIG_SYS_MAX_FLASH_BANKS 1 227 228 /* NAND flash */ 229 #ifdef CONFIG_CMD_NAND 230 #define CONFIG_NAND_ATMEL 231 #define CONFIG_SYS_MAX_NAND_DEVICE 1 232 #define CONFIG_SYS_NAND_BASE 0x40000000 233 #define CONFIG_SYS_NAND_DBW_8 1 234 /* our ALE is AD21 */ 235 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 236 /* our CLE is AD22 */ 237 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 238 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 239 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) 240 241 #endif 242 243 #define CONFIG_CMD_JFFS2 1 244 #define CONFIG_JFFS2_CMDLINE 1 245 #define CONFIG_JFFS2_NAND 1 246 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 247 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 248 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 249 250 /* PSRAM */ 251 #define PHYS_PSRAM 0x70000000 252 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 253 /* Slave EBI1, PSRAM connected */ 254 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ 255 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ 256 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ 257 AT91_MATRIX_SCFG_SLOT_CYCLE(255)) 258 259 /* Ethernet */ 260 #define CONFIG_MACB 1 261 #define CONFIG_RMII 1 262 #define CONFIG_NET_RETRY_COUNT 20 263 #define CONFIG_RESET_PHY_R 1 264 265 /* USB */ 266 #define CONFIG_USB_ATMEL 267 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 268 #define CONFIG_USB_OHCI_NEW 1 269 #define CONFIG_DOS_PARTITION 1 270 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 271 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 272 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 273 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 274 #define CONFIG_USB_STORAGE 1 275 276 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 277 278 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 279 #define CONFIG_SYS_MEMTEST_END 0x23e00000 280 281 #define CONFIG_SYS_USE_FLASH 1 282 #undef CONFIG_SYS_USE_DATAFLASH 283 #undef CONFIG_SYS_USE_NANDFLASH 284 285 #ifdef CONFIG_SYS_USE_DATAFLASH 286 287 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 288 #define CONFIG_ENV_IS_IN_DATAFLASH 289 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 290 #define CONFIG_ENV_OFFSET 0x4200 291 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 292 #define CONFIG_ENV_SIZE 0x4200 293 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 294 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 295 "root=/dev/mtdblock0 " \ 296 "mtdparts=atmel_nand:-(root) "\ 297 "rw rootfstype=jffs2" 298 299 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 300 301 /* bootstrap + u-boot + env + linux in nandflash */ 302 #define CONFIG_ENV_IS_IN_NAND 303 #define CONFIG_ENV_OFFSET 0x60000 304 #define CONFIG_ENV_OFFSET_REDUND 0x80000 305 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 306 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 307 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 308 "root=/dev/mtdblock5 " \ 309 "mtdparts=atmel_nand:" \ 310 "128k(bootstrap)ro," \ 311 "256k(uboot)ro," \ 312 "128k(env1)ro," \ 313 "128k(env2)ro," \ 314 "2M(linux)," \ 315 "-(root) " \ 316 "rw rootfstype=jffs2" 317 318 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 319 320 #define CONFIG_ENV_IS_IN_FLASH 1 321 #define CONFIG_ENV_OFFSET 0x40000 322 #define CONFIG_ENV_SECT_SIZE 0x10000 323 #define CONFIG_ENV_SIZE 0x10000 324 #define CONFIG_ENV_OVERWRITE 1 325 326 /* JFFS Partition offset set */ 327 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 328 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 329 330 /* 512k reserved for u-boot */ 331 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 332 333 #define CONFIG_BOOTCOMMAND "run flashboot" 334 #define CONFIG_ROOTPATH "/ronetix/rootfs" 335 336 #define CONFIG_CON_ROT "fbcon=rotate:3 " 337 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ 338 CONFIG_CON_ROT 339 340 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 341 #define MTDPARTS_DEFAULT \ 342 "mtdparts=physmap-flash.0:" \ 343 "256k(u-boot)ro," \ 344 "64k(u-boot-env)ro," \ 345 "1408k(kernel)," \ 346 "-(rootfs);" \ 347 "nand:-(nand)" 348 349 #define CONFIG_EXTRA_ENV_SETTINGS \ 350 "mtdids=" MTDIDS_DEFAULT "\0" \ 351 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 352 "partition=nand0,0\0" \ 353 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 354 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 355 CONFIG_CON_ROT \ 356 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 357 "addip=setenv bootargs $(bootargs) " \ 358 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 359 ":$(hostname):eth0:off\0" \ 360 "ramboot=tftpboot 0x22000000 vmImage;" \ 361 "run ramargs;run addip;bootm 22000000\0" \ 362 "nfsboot=tftpboot 0x22000000 vmImage;" \ 363 "run nfsargs;run addip;bootm 22000000\0" \ 364 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 365 "" 366 367 #else 368 #error "Undefined memory device" 369 #endif 370 371 #define CONFIG_BAUDRATE 115200 372 373 #define CONFIG_SYS_CBSIZE 256 374 #define CONFIG_SYS_MAXARGS 16 375 #define CONFIG_SYS_PBSIZE \ 376 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 377 #define CONFIG_SYS_LONGHELP 1 378 #define CONFIG_CMDLINE_EDITING 1 379 380 /* 381 * Size of malloc() pool 382 */ 383 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 384 385 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 386 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 387 GENERATED_GBL_DATA_SIZE) 388 389 #endif 390