1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Based on davinci_dvevm.h. Original Copyrights follow: 6 * 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * Board 15 */ 16 #undef CONFIG_USE_SPIFLASH 17 #undef CONFIG_SYS_USE_NOR 18 19 /* 20 * Disable DM_* for SPL build and can be re-enabled after adding 21 * DM support in SPL 22 */ 23 #ifdef CONFIG_SPL_BUILD 24 #undef CONFIG_DM_I2C 25 #undef CONFIG_DM_I2C_COMPAT 26 #endif 27 /* 28 * SoC Configuration 29 */ 30 #define CONFIG_MACH_OMAPL138_LCDK 31 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 32 #define CONFIG_SYS_OSCIN_FREQ 24000000 33 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 34 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 35 #define CONFIG_SYS_HZ 1000 36 #define CONFIG_SKIP_LOWLEVEL_INIT 37 38 /* 39 * Memory Info 40 */ 41 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 42 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 43 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 44 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 45 46 /* memtest start addr */ 47 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 48 49 /* memtest will be run on 16MB */ 50 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 51 52 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 53 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 54 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 55 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 56 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 57 DAVINCI_SYSCFG_SUSPSRC_I2C) 58 59 /* 60 * PLL configuration 61 */ 62 63 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ 64 #define CONFIG_SYS_DA850_PLL0_PLLM 18 65 #define CONFIG_SYS_DA850_PLL1_PLLM 21 66 67 /* 68 * DDR2 memory configuration 69 */ 70 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 71 DV_DDR_PHY_EXT_STRBEN | \ 72 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 73 74 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 75 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 76 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 77 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 78 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 79 (4 << DV_DDR_SDCR_CL_SHIFT) | \ 80 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 81 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 82 83 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 84 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 85 86 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 87 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 88 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 89 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 90 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 91 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 92 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 93 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 94 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 95 96 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 97 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 98 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 99 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 100 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 101 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 102 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 103 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 104 105 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 106 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 107 108 /* 109 * Serial Driver info 110 */ 111 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 112 #if !defined(CONFIG_DM_SERIAL) 113 #define CONFIG_SYS_NS16550_SERIAL 114 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 115 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 116 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 117 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 118 #endif 119 120 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 121 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 122 #define CONFIG_SF_DEFAULT_SPEED 30000000 123 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 124 125 #ifdef CONFIG_USE_SPIFLASH 126 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 127 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 128 #endif 129 130 /* 131 * I2C Configuration 132 */ 133 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 134 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 135 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 136 137 /* 138 * Flash & Environment 139 */ 140 #ifdef CONFIG_NAND 141 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 142 #define CONFIG_ENV_SIZE (128 << 9) 143 #define CONFIG_SYS_NAND_USE_FLASH_BBT 144 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 145 #define CONFIG_SYS_NAND_PAGE_2K 146 #define CONFIG_SYS_NAND_CS 3 147 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 148 #define CONFIG_SYS_NAND_MASK_CLE 0x10 149 #define CONFIG_SYS_NAND_MASK_ALE 0x8 150 #undef CONFIG_SYS_NAND_HW_ECC 151 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 152 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 153 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 154 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 155 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 157 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K 158 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 159 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 160 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 161 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 162 CONFIG_SYS_MALLOC_LEN - \ 163 GENERATED_GBL_DATA_SIZE) 164 #define CONFIG_SYS_NAND_ECCPOS { \ 165 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 166 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 167 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 168 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } 169 #define CONFIG_SYS_NAND_PAGE_COUNT 64 170 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 171 #define CONFIG_SYS_NAND_ECCSIZE 512 172 #define CONFIG_SYS_NAND_ECCBYTES 10 173 #define CONFIG_SYS_NAND_OOBSIZE 64 174 #define CONFIG_SPL_NAND_BASE 175 #define CONFIG_SPL_NAND_DRIVERS 176 #define CONFIG_SPL_NAND_ECC 177 #define CONFIG_SPL_NAND_LOAD 178 #endif 179 180 #ifdef CONFIG_SYS_USE_NOR 181 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 182 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 183 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 184 #define CONFIG_ENV_SIZE (128 << 10) 185 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 186 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 187 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 188 + 3) 189 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 190 #endif 191 192 #ifdef CONFIG_USE_SPIFLASH 193 #define CONFIG_ENV_SIZE (64 << 10) 194 #define CONFIG_ENV_OFFSET (256 << 10) 195 #define CONFIG_ENV_SECT_SIZE (64 << 10) 196 #endif 197 198 /* 199 * Network & Ethernet Configuration 200 */ 201 #ifdef CONFIG_DRIVER_TI_EMAC 202 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII 203 #define CONFIG_BOOTP_DEFAULT 204 #define CONFIG_BOOTP_DNS2 205 #define CONFIG_BOOTP_SEND_HOSTNAME 206 #define CONFIG_NET_RETRY_COUNT 10 207 #endif 208 209 /* 210 * U-Boot general configuration 211 */ 212 #define CONFIG_BOOTFILE "zImage" /* Boot file name */ 213 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 214 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 215 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 216 #define CONFIG_MX_CYCLIC 217 218 /* 219 * Linux Information 220 */ 221 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 222 #define CONFIG_CMDLINE_TAG 223 #define CONFIG_REVISION_TAG 224 #define CONFIG_SETUP_MEMORY_TAGS 225 #define CONFIG_BOOTCOMMAND \ 226 "run envboot; " \ 227 "run mmcboot; " 228 229 #define DEFAULT_LINUX_BOOT_ENV \ 230 "loadaddr=0xc0700000\0" \ 231 "fdtaddr=0xc0600000\0" \ 232 "scriptaddr=0xc0600000\0" 233 234 #include <environment/ti/mmc.h> 235 236 #define CONFIG_EXTRA_ENV_SETTINGS \ 237 DEFAULT_LINUX_BOOT_ENV \ 238 DEFAULT_MMC_TI_ARGS \ 239 "bootpart=0:2\0" \ 240 "bootdir=/boot\0" \ 241 "bootfile=zImage\0" \ 242 "fdtfile=da850-lcdk.dtb\0" \ 243 "boot_fdt=yes\0" \ 244 "boot_fit=0\0" \ 245 "console=ttyS2,115200n8\0" 246 247 #ifdef CONFIG_CMD_BDI 248 #define CONFIG_CLOCKS 249 #endif 250 251 #if !defined(CONFIG_NAND) && \ 252 !defined(CONFIG_SYS_USE_NOR) && \ 253 !defined(CONFIG_USE_SPIFLASH) 254 #define CONFIG_ENV_SIZE (16 << 10) 255 #endif 256 257 /* SD/MMC */ 258 259 #ifdef CONFIG_ENV_IS_IN_MMC 260 #undef CONFIG_ENV_SIZE 261 #undef CONFIG_ENV_OFFSET 262 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 263 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ 264 #endif 265 266 #ifndef CONFIG_DIRECT_NOR_BOOT 267 /* defines for SPL */ 268 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 269 CONFIG_SYS_MALLOC_LEN) 270 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 271 #define CONFIG_SPL_STACK 0x8001ff00 272 #define CONFIG_SPL_TEXT_BASE 0x80000000 273 #define CONFIG_SPL_MAX_FOOTPRINT 32768 274 #define CONFIG_SPL_PAD_TO 32768 275 #endif 276 277 /* additions for new relocation code, must added to all boards */ 278 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 279 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 280 GENERATED_GBL_DATA_SIZE) 281 282 #include <asm/arch/hardware.h> 283 284 #endif /* __CONFIG_H */ 285