1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _DDR3_TRAINING_IP_PRV_IF_H 8 #define _DDR3_TRAINING_IP_PRV_IF_H 9 10 #include "ddr3_training_ip.h" 11 #include "ddr3_training_ip_flow.h" 12 #include "ddr3_training_ip_bist.h" 13 14 enum hws_static_config_type { 15 WRITE_LEVELING_STATIC, 16 READ_LEVELING_STATIC 17 }; 18 19 struct ddr3_device_info { 20 u32 device_id; 21 u32 ck_delay; 22 }; 23 24 typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable); 25 typedef int (*HWS_TIP_DUNIT_REG_READ_FUNC_PTR)( 26 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 27 u32 offset, u32 *data, u32 mask); 28 typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)( 29 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 30 u32 offset, u32 data, u32 mask); 31 typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)( 32 u8 dev_num, enum hws_ddr_freq freq, 33 struct hws_tip_freq_config_info *freq_config_info); 34 typedef int (*HWS_TIP_GET_DEVICE_INFO)( 35 u8 dev_num, struct ddr3_device_info *info_ptr); 36 typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)( 37 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info); 38 typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)( 39 u8 dev_num, u32 if_id, enum hws_ddr_freq freq); 40 typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq); 41 typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)( 42 u32 dev_num, enum hws_access_type access_type, u32 dunit_id, 43 u32 reg_addr, u32 data, u32 mask); 44 typedef int (*HWS_TRAINING_IP_IF_READ_FUNC_PTR)( 45 u32 dev_num, enum hws_access_type access_type, u32 dunit_id, 46 u32 reg_addr, u32 *data, u32 mask); 47 typedef int (*HWS_TRAINING_IP_BUS_WRITE_FUNC_PTR)( 48 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id, 49 enum hws_access_type phy_access_type, u32 phy_id, 50 enum hws_ddr_phy phy_type, u32 reg_addr, u32 data); 51 typedef int (*HWS_TRAINING_IP_BUS_READ_FUNC_PTR)( 52 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type, 53 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data); 54 typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)( 55 u32 dev_num, enum hws_algo_type algo_type); 56 typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)( 57 u32 dev_num, enum hws_access_type access_type, u32 if_id, 58 enum hws_ddr_freq frequency); 59 typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)( 60 u32 dev_num, struct init_cntr_param *init_cntr_prm); 61 typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num); 62 typedef int (*HWS_TRAINING_IP_PBS_TX_FUNC_PTR)(u32 dev_num); 63 typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)( 64 u32 dev_num, int enable); 65 typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)( 66 u32 dev_num, struct hws_topology_map *topology_map); 67 typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)( 68 u32 dev_num, enum hws_ddr_freq frequency, 69 enum hws_static_config_type static_config_type, u32 if_id); 70 typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)( 71 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); 72 typedef int (*HWS_TRAINING_IP_EXTERNAL_WRITE_PTR)( 73 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); 74 typedef int (*HWS_TRAINING_IP_BIST_ACTIVATE)( 75 u32 dev_num, enum hws_pattern pattern, enum hws_access_type access_type, 76 u32 if_num, enum hws_dir direction, 77 enum hws_stress_jump addr_stress_jump, 78 enum hws_pattern_duration duration, 79 enum hws_bist_operation oper_type, u32 offset, u32 cs_num, 80 u32 pattern_addr_length); 81 typedef int (*HWS_TRAINING_IP_BIST_READ_RESULT)( 82 u32 dev_num, u32 if_id, struct bist_result *pst_bist_result); 83 typedef int (*HWS_TRAINING_IP_LOAD_TOPOLOGY)(u32 dev_num, u32 config_num); 84 typedef int (*HWS_TRAINING_IP_READ_LEVELING)(u32 dev_num, u32 config_num); 85 typedef int (*HWS_TRAINING_IP_WRITE_LEVELING)(u32 dev_num, u32 config_num); 86 typedef u32 (*HWS_TRAINING_IP_GET_TEMP)(u8 dev_num); 87 88 struct hws_tip_config_func_db { 89 HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR tip_dunit_mux_select_func; 90 HWS_TIP_DUNIT_REG_READ_FUNC_PTR tip_dunit_read_func; 91 HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR tip_dunit_write_func; 92 HWS_TIP_GET_FREQ_CONFIG_INFO tip_get_freq_config_info_func; 93 HWS_TIP_GET_DEVICE_INFO tip_get_device_info_func; 94 HWS_SET_FREQ_DIVIDER_FUNC_PTR tip_set_freq_divider_func; 95 HWS_GET_CS_CONFIG_FUNC_PTR tip_get_cs_config_info; 96 HWS_TRAINING_IP_GET_TEMP tip_get_temperature; 97 }; 98 99 int ddr3_tip_init_config_func(u32 dev_num, 100 struct hws_tip_config_func_db *config_func); 101 int ddr3_tip_register_xsb_info(u32 dev_num, 102 struct hws_xsb_info *xsb_info_table); 103 enum hws_result *ddr3_tip_get_result_ptr(u32 stage); 104 int ddr3_set_freq_config_info(struct hws_tip_freq_config_info *table); 105 int print_device_info(u8 dev_num); 106 107 #endif /* _DDR3_TRAINING_IP_PRV_IF_H */ 108