1 /* 2 * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __IMX_REGS_LCDIF_H__ 14 #define __IMX_REGS_LCDIF_H__ 15 16 #ifndef __ASSEMBLY__ 17 #include <asm/mach-imx/regs-common.h> 18 19 struct mxs_lcdif_regs { 20 mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ 21 mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ 22 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ 23 defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) 24 mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ 25 #endif 26 mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ 27 mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */ 28 mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */ 29 30 #if defined(CONFIG_MX23) 31 uint32_t reserved1[4]; 32 #endif 33 34 mxs_reg_32(hw_lcdif_timing) /* 0x60 */ 35 mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ 36 mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ 37 mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */ 38 mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */ 39 mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */ 40 mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */ 41 mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */ 42 mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */ 43 mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */ 44 mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */ 45 mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */ 46 mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */ 47 mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ 48 mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ 49 mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ 50 mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ 51 mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */ 52 53 #if defined(CONFIG_MX23) 54 uint32_t reserved2[12]; 55 #endif 56 mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ 57 mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ 58 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ 59 defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) 60 mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ 61 #endif 62 mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ 63 mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */ 64 mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ 65 mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ 66 mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ 67 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \ 68 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) 69 mxs_reg_32(hw_lcdif_thres) 70 mxs_reg_32(hw_lcdif_as_ctrl) 71 mxs_reg_32(hw_lcdif_as_buf) 72 mxs_reg_32(hw_lcdif_as_next_buf) 73 mxs_reg_32(hw_lcdif_as_clrkeylow) 74 mxs_reg_32(hw_lcdif_as_clrkeyhigh) 75 mxs_reg_32(hw_lcdif_as_sync_delay) 76 mxs_reg_32(hw_lcdif_as_debug3) 77 mxs_reg_32(hw_lcdif_as_debug4) 78 mxs_reg_32(hw_lcdif_as_debug5) 79 #endif 80 }; 81 #endif 82 83 #define LCDIF_CTRL_SFTRST (1 << 31) 84 #define LCDIF_CTRL_CLKGATE (1 << 30) 85 #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) 86 #define LCDIF_CTRL_READ_WRITEB (1 << 28) 87 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) 88 #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) 89 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) 90 #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 91 #define LCDIF_CTRL_DVI_MODE (1 << 20) 92 #define LCDIF_CTRL_BYPASS_COUNT (1 << 19) 93 #define LCDIF_CTRL_VSYNC_MODE (1 << 18) 94 #define LCDIF_CTRL_DOTCLK_MODE (1 << 17) 95 #define LCDIF_CTRL_DATA_SELECT (1 << 16) 96 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) 97 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 98 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) 99 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 100 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) 101 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 102 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) 103 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) 104 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) 105 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) 106 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) 107 #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 108 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) 109 #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) 110 #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) 111 #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) 112 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) 113 #define LCDIF_CTRL_LCDIF_MASTER (1 << 5) 114 #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) 115 #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) 116 #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) 117 #define LCDIF_CTRL_RUN (1 << 0) 118 119 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) 120 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) 121 #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) 122 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) 123 #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) 124 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) 125 #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) 126 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) 127 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) 128 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 129 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) 130 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) 131 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) 132 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) 133 #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) 134 #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) 135 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) 136 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) 137 #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) 138 #define LCDIF_CTRL1_MODE86 (1 << 1) 139 #define LCDIF_CTRL1_RESET (1 << 0) 140 141 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) 142 #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 143 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) 144 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) 145 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) 146 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) 147 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) 148 #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) 149 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) 150 #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 151 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) 152 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) 153 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) 154 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) 155 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) 156 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) 157 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) 158 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 159 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) 160 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) 161 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) 162 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) 163 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) 164 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) 165 #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) 166 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) 167 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) 168 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) 169 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 170 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) 171 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 172 173 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) 174 #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 175 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) 176 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 177 178 #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff 179 #define LCDIF_CUR_BUF_ADDR_OFFSET 0 180 181 #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff 182 #define LCDIF_NEXT_BUF_ADDR_OFFSET 0 183 184 #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) 185 #define LCDIF_TIMING_CMD_HOLD_OFFSET 24 186 #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) 187 #define LCDIF_TIMING_CMD_SETUP_OFFSET 16 188 #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) 189 #define LCDIF_TIMING_DATA_HOLD_OFFSET 8 190 #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) 191 #define LCDIF_TIMING_DATA_SETUP_OFFSET 0 192 193 #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) 194 #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) 195 #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) 196 #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) 197 #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) 198 #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) 199 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) 200 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) 201 #define LCDIF_VDCTRL0_HALF_LINE (1 << 19) 202 #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) 203 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff 204 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 205 206 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff 207 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 208 209 #if defined(CONFIG_MX23) 210 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) 211 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 212 #else 213 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) 214 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 215 #endif 216 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff 217 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 218 219 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) 220 #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) 221 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) 222 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 223 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) 224 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 225 226 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) 227 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 228 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) 229 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff 230 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 231 232 #endif /* __IMX_REGS_LCDIF_H__ */ 233