1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration for Versatile Express. Parts were derived from other ARM 4 * configurations. 5 */ 6 7 #ifndef __VEXPRESS_AEMV8A_H 8 #define __VEXPRESS_AEMV8A_H 9 10 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 11 #ifndef CONFIG_SEMIHOSTING 12 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING 13 #endif 14 #define CONFIG_ARMV8_SWITCH_TO_EL1 15 #endif 16 17 #define CONFIG_REMAKE_ELF 18 19 /* Link Definitions */ 20 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 21 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 22 /* ATF loads u-boot here for BASE_FVP model */ 23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 24 #elif CONFIG_TARGET_VEXPRESS64_JUNO 25 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 26 #endif 27 28 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 29 30 /* CS register bases for the original memory map. */ 31 #define V2M_PA_CS0 0x00000000 32 #define V2M_PA_CS1 0x14000000 33 #define V2M_PA_CS2 0x18000000 34 #define V2M_PA_CS3 0x1c000000 35 #define V2M_PA_CS4 0x0c000000 36 #define V2M_PA_CS5 0x10000000 37 38 #define V2M_PERIPH_OFFSET(x) (x << 16) 39 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 40 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 41 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 42 43 #define V2M_BASE 0x80000000 44 45 /* Common peripherals relative to CS7. */ 46 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 47 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 48 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 49 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 50 51 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 52 #define V2M_UART0 0x7ff80000 53 #define V2M_UART1 0x7ff70000 54 #else /* Not Juno */ 55 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 56 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 57 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 58 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 59 #endif 60 61 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 62 63 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 64 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 65 66 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 67 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 68 69 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 70 71 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 72 73 /* System register offsets. */ 74 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 75 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 76 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 77 78 /* Generic Timer Definitions */ 79 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 80 81 /* Generic Interrupt Controller Definitions */ 82 #ifdef CONFIG_GICV3 83 #define GICD_BASE (0x2f000000) 84 #define GICR_BASE (0x2f100000) 85 #else 86 87 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 88 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 89 #define GICD_BASE (0x2f000000) 90 #define GICC_BASE (0x2c000000) 91 #elif CONFIG_TARGET_VEXPRESS64_JUNO 92 #define GICD_BASE (0x2C010000) 93 #define GICC_BASE (0x2C02f000) 94 #endif 95 #endif /* !CONFIG_GICV3 */ 96 97 /* Size of malloc() pool */ 98 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 99 100 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO 101 /* The Vexpress64 simulators use SMSC91C111 */ 102 #define CONFIG_SMC91111 1 103 #define CONFIG_SMC91111_BASE (0x01A000000) 104 #endif 105 106 /* PL011 Serial Configuration */ 107 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 108 #define CONFIG_PL011_CLOCK 7273800 109 #else 110 #define CONFIG_PL011_CLOCK 24000000 111 #endif 112 113 /*#define CONFIG_MENU_SHOW*/ 114 115 /* BOOTP options */ 116 #define CONFIG_BOOTP_BOOTFILESIZE 117 118 /* Miscellaneous configurable options */ 119 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 120 121 /* Physical Memory Map */ 122 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 123 /* Top 16MB reserved for secure world use */ 124 #define DRAM_SEC_SIZE 0x01000000 125 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE 126 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 127 128 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 129 #define PHYS_SDRAM_2 (0x880000000) 130 #define PHYS_SDRAM_2_SIZE 0x180000000 131 #endif 132 133 /* Enable memtest */ 134 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 135 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 136 137 /* Initial environment variables */ 138 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 139 /* 140 * Defines where the kernel and FDT exist in NOR flash and where it will 141 * be copied into DRAM 142 */ 143 #define CONFIG_EXTRA_ENV_SETTINGS \ 144 "kernel_name=norkern\0" \ 145 "kernel_alt_name=Image\0" \ 146 "kernel_addr=0x80080000\0" \ 147 "initrd_name=ramdisk.img\0" \ 148 "initrd_addr=0x84000000\0" \ 149 "fdtfile=board.dtb\0" \ 150 "fdt_alt_name=juno\0" \ 151 "fdt_addr=0x83000000\0" \ 152 "fdt_high=0xffffffffffffffff\0" \ 153 "initrd_high=0xffffffffffffffff\0" \ 154 155 /* Copy the kernel and FDT to DRAM memory and boot */ 156 #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ 157 "if test $? -eq 1; then "\ 158 " echo Loading ${kernel_alt_name} instead of "\ 159 "${kernel_name}; "\ 160 " afs load ${kernel_alt_name} ${kernel_addr};"\ 161 "fi ; "\ 162 "afs load ${fdtfile} ${fdt_addr} ; " \ 163 "if test $? -eq 1; then "\ 164 " echo Loading ${fdt_alt_name} instead of "\ 165 "${fdtfile}; "\ 166 " afs load ${fdt_alt_name} ${fdt_addr}; "\ 167 "fi ; "\ 168 "fdt addr ${fdt_addr}; fdt resize; " \ 169 "if afs load ${initrd_name} ${initrd_addr} ; "\ 170 "then "\ 171 " setenv initrd_param ${initrd_addr}; "\ 172 " else setenv initrd_param -; "\ 173 "fi ; " \ 174 "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" 175 176 177 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP 178 #define CONFIG_EXTRA_ENV_SETTINGS \ 179 "kernel_name=Image\0" \ 180 "kernel_addr=0x80080000\0" \ 181 "initrd_name=ramdisk.img\0" \ 182 "initrd_addr=0x88000000\0" \ 183 "fdtfile=devtree.dtb\0" \ 184 "fdt_addr=0x83000000\0" \ 185 "fdt_high=0xffffffffffffffff\0" \ 186 "initrd_high=0xffffffffffffffff\0" 187 188 #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ 189 "smhload ${fdtfile} ${fdt_addr}; " \ 190 "smhload ${initrd_name} ${initrd_addr} "\ 191 "initrd_end; " \ 192 "fdt addr ${fdt_addr}; fdt resize; " \ 193 "fdt chosen ${initrd_addr} ${initrd_end}; " \ 194 "booti $kernel_addr - $fdt_addr" 195 196 197 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM 198 #define CONFIG_EXTRA_ENV_SETTINGS \ 199 "kernel_addr=0x80080000\0" \ 200 "initrd_addr=0x84000000\0" \ 201 "fdt_addr=0x83000000\0" \ 202 "fdt_high=0xffffffffffffffff\0" \ 203 "initrd_high=0xffffffffffffffff\0" 204 205 #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" 206 207 208 #endif 209 210 /* Monitor Command Prompt */ 211 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 212 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 213 214 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 215 #define CONFIG_SYS_FLASH_BASE 0x08000000 216 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 259 218 /* Store environment at top of flash in the same location as blank.img */ 219 /* in the Juno firmware. */ 220 #define CONFIG_ENV_ADDR 0x0BFC0000 221 #define CONFIG_ENV_SECT_SIZE 0x00010000 222 #else 223 #define CONFIG_SYS_FLASH_BASE 0x0C000000 224 /* 256 x 256KiB sectors */ 225 #define CONFIG_SYS_MAX_FLASH_SECT 256 226 /* Store environment at top of flash */ 227 #define CONFIG_ENV_ADDR 0x0FFC0000 228 #define CONFIG_ENV_SECT_SIZE 0x00040000 229 #endif 230 231 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 232 #define CONFIG_SYS_MAX_FLASH_BANKS 1 233 234 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 235 #define FLASH_MAX_SECTOR_SIZE 0x00040000 236 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 237 238 #endif /* __VEXPRESS_AEMV8A_H */ 239