1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8540ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 25 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 26 27 /* 28 * default CCARBAR is at 0xff700000 29 * assume U-Boot is less than 0.5MB 30 */ 31 #define CONFIG_SYS_TEXT_BASE 0xfff80000 32 33 #ifndef CONFIG_HAS_FEC 34 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 35 #endif 36 37 #define CONFIG_PCI 38 #define CONFIG_PCI_INDIRECT_BRIDGE 39 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #define CONFIG_ENV_OVERWRITE 42 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 43 44 /* 45 * sysclk for MPC85xx 46 * 47 * Two valid values are: 48 * 33000000 49 * 66000000 50 * 51 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 52 * is likely the desired value here, so that is now the default. 53 * The board, however, can run at 66MHz. In any event, this value 54 * must match the settings of some switches. Details can be found 55 * in the README.mpc85xxads. 56 * 57 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 58 * 33MHz to accommodate, based on a PCI pin. 59 * Note that PCI-X won't work at 33MHz. 60 */ 61 62 #ifndef CONFIG_SYS_CLK_FREQ 63 #define CONFIG_SYS_CLK_FREQ 33000000 64 #endif 65 66 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_L2_CACHE /* toggle L2 cache */ 71 #define CONFIG_BTB /* toggle branch predition */ 72 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 74 #define CONFIG_SYS_MEMTEST_END 0x00400000 75 76 #define CONFIG_SYS_CCSRBAR 0xe0000000 77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 78 79 /* DDR Setup */ 80 #define CONFIG_SYS_FSL_DDR1 81 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 82 #define CONFIG_DDR_SPD 83 #undef CONFIG_FSL_DDR_INTERACTIVE 84 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 89 90 #define CONFIG_NUM_DDR_CONTROLLERS 1 91 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 92 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 93 94 /* I2C addresses of SPD EEPROMs */ 95 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 96 97 /* These are used when DDR doesn't use SPD. */ 98 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 99 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 100 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 101 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 102 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 103 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 104 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 105 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 106 107 /* 108 * SDRAM on the Local Bus 109 */ 110 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 111 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 112 113 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 114 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 115 116 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 119 #undef CONFIG_SYS_FLASH_CHECKSUM 120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 124 125 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 126 #define CONFIG_SYS_RAMBOOT 127 #else 128 #undef CONFIG_SYS_RAMBOOT 129 #endif 130 131 #define CONFIG_FLASH_CFI_DRIVER 132 #define CONFIG_SYS_FLASH_CFI 133 #define CONFIG_SYS_FLASH_EMPTY_INFO 134 135 #undef CONFIG_CLOCKS_IN_MHZ 136 137 138 /* 139 * Local Bus Definitions 140 */ 141 142 /* 143 * Base Register 2 and Option Register 2 configure SDRAM. 144 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 145 * 146 * For BR2, need: 147 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 148 * port-size = 32-bits = BR2[19:20] = 11 149 * no parity checking = BR2[21:22] = 00 150 * SDRAM for MSEL = BR2[24:26] = 011 151 * Valid = BR[31] = 1 152 * 153 * 0 4 8 12 16 20 24 28 154 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 155 * 156 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 157 * FIXME: the top 17 bits of BR2. 158 */ 159 160 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 161 162 /* 163 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 164 * 165 * For OR2, need: 166 * 64MB mask for AM, OR2[0:7] = 1111 1100 167 * XAM, OR2[17:18] = 11 168 * 9 columns OR2[19-21] = 010 169 * 13 rows OR2[23-25] = 100 170 * EAD set for extra time OR[31] = 1 171 * 172 * 0 4 8 12 16 20 24 28 173 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 174 */ 175 176 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 177 178 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 179 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 180 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 181 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 182 183 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 184 | LSDMR_RFCR5 \ 185 | LSDMR_PRETOACT3 \ 186 | LSDMR_ACTTORW3 \ 187 | LSDMR_BL8 \ 188 | LSDMR_WRC2 \ 189 | LSDMR_CL3 \ 190 | LSDMR_RFEN \ 191 ) 192 193 /* 194 * SDRAM Controller configuration sequence. 195 */ 196 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 197 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 198 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 199 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 200 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 201 202 203 /* 204 * 32KB, 8-bit wide for ADS config reg 205 */ 206 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 207 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 208 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 213 214 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 216 217 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 218 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 219 220 /* Serial Port */ 221 #define CONFIG_CONS_INDEX 1 222 #define CONFIG_SYS_NS16550 223 #define CONFIG_SYS_NS16550_SERIAL 224 #define CONFIG_SYS_NS16550_REG_SIZE 1 225 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 226 227 #define CONFIG_SYS_BAUDRATE_TABLE \ 228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 229 230 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 231 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 232 233 /* Use the HUSH parser */ 234 #define CONFIG_SYS_HUSH_PARSER 235 #ifdef CONFIG_SYS_HUSH_PARSER 236 #endif 237 238 /* pass open firmware flat tree */ 239 #define CONFIG_OF_LIBFDT 1 240 #define CONFIG_OF_BOARD_SETUP 1 241 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 242 243 /* 244 * I2C 245 */ 246 #define CONFIG_SYS_I2C 247 #define CONFIG_SYS_I2C_FSL 248 #define CONFIG_SYS_FSL_I2C_SPEED 400000 249 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 250 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 251 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 252 253 /* RapidIO MMU */ 254 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 255 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 256 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 257 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 258 259 /* 260 * General PCI 261 * Memory space is mapped 1-1, but I/O space must start from 0. 262 */ 263 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 264 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 265 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 266 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 267 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 268 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 269 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 270 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 271 272 #if defined(CONFIG_PCI) 273 274 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 275 276 #undef CONFIG_EEPRO100 277 #undef CONFIG_TULIP 278 279 #if !defined(CONFIG_PCI_PNP) 280 #define PCI_ENET0_IOADDR 0xe0000000 281 #define PCI_ENET0_MEMADDR 0xe0000000 282 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 283 #endif 284 285 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 286 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 287 288 #endif /* CONFIG_PCI */ 289 290 291 #if defined(CONFIG_TSEC_ENET) 292 293 #define CONFIG_MII 1 /* MII PHY management */ 294 #define CONFIG_TSEC1 1 295 #define CONFIG_TSEC1_NAME "TSEC0" 296 #define CONFIG_TSEC2 1 297 #define CONFIG_TSEC2_NAME "TSEC1" 298 #define TSEC1_PHY_ADDR 0 299 #define TSEC2_PHY_ADDR 1 300 #define TSEC1_PHYIDX 0 301 #define TSEC2_PHYIDX 0 302 #define TSEC1_FLAGS TSEC_GIGABIT 303 #define TSEC2_FLAGS TSEC_GIGABIT 304 305 306 #if CONFIG_HAS_FEC 307 #define CONFIG_MPC85XX_FEC 1 308 #define CONFIG_MPC85XX_FEC_NAME "FEC" 309 #define FEC_PHY_ADDR 3 310 #define FEC_PHYIDX 0 311 #define FEC_FLAGS 0 312 #endif 313 314 /* Options are: TSEC[0-1], FEC */ 315 #define CONFIG_ETHPRIME "TSEC0" 316 317 #endif /* CONFIG_TSEC_ENET */ 318 319 320 /* 321 * Environment 322 */ 323 #ifndef CONFIG_SYS_RAMBOOT 324 #define CONFIG_ENV_IS_IN_FLASH 1 325 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 326 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 327 #define CONFIG_ENV_SIZE 0x2000 328 #else 329 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 330 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 331 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 332 #define CONFIG_ENV_SIZE 0x2000 333 #endif 334 335 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 336 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 337 338 339 /* 340 * BOOTP options 341 */ 342 #define CONFIG_BOOTP_BOOTFILESIZE 343 #define CONFIG_BOOTP_BOOTPATH 344 #define CONFIG_BOOTP_GATEWAY 345 #define CONFIG_BOOTP_HOSTNAME 346 347 348 /* 349 * Command line configuration. 350 */ 351 #define CONFIG_CMD_PING 352 #define CONFIG_CMD_I2C 353 #define CONFIG_CMD_ELF 354 #define CONFIG_CMD_IRQ 355 356 #if defined(CONFIG_PCI) 357 #define CONFIG_CMD_PCI 358 #endif 359 360 #undef CONFIG_WATCHDOG /* watchdog disabled */ 361 362 /* 363 * Miscellaneous configurable options 364 */ 365 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 366 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 367 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 368 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 369 370 #if defined(CONFIG_CMD_KGDB) 371 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 372 #else 373 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 374 #endif 375 376 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 377 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 378 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 379 380 /* 381 * For booting Linux, the board info and command line data 382 * have to be in the first 64 MB of memory, since this is 383 * the maximum mapped by the Linux kernel during initialization. 384 */ 385 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 386 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 387 388 #if defined(CONFIG_CMD_KGDB) 389 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 390 #endif 391 392 393 /* 394 * Environment Configuration 395 */ 396 397 /* The mac addresses for all ethernet interface */ 398 #if defined(CONFIG_TSEC_ENET) 399 #define CONFIG_HAS_ETH0 400 #define CONFIG_HAS_ETH1 401 #define CONFIG_HAS_ETH2 402 #endif 403 404 #define CONFIG_IPADDR 192.168.1.253 405 406 #define CONFIG_HOSTNAME unknown 407 #define CONFIG_ROOTPATH "/nfsroot" 408 #define CONFIG_BOOTFILE "your.uImage" 409 410 #define CONFIG_SERVERIP 192.168.1.1 411 #define CONFIG_GATEWAYIP 192.168.1.1 412 #define CONFIG_NETMASK 255.255.255.0 413 414 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 415 416 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 417 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 418 419 #define CONFIG_BAUDRATE 115200 420 421 #define CONFIG_EXTRA_ENV_SETTINGS \ 422 "netdev=eth0\0" \ 423 "consoledev=ttyS0\0" \ 424 "ramdiskaddr=1000000\0" \ 425 "ramdiskfile=your.ramdisk.u-boot\0" \ 426 "fdtaddr=400000\0" \ 427 "fdtfile=your.fdt.dtb\0" 428 429 #define CONFIG_NFSBOOTCOMMAND \ 430 "setenv bootargs root=/dev/nfs rw " \ 431 "nfsroot=$serverip:$rootpath " \ 432 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 433 "console=$consoledev,$baudrate $othbootargs;" \ 434 "tftp $loadaddr $bootfile;" \ 435 "tftp $fdtaddr $fdtfile;" \ 436 "bootm $loadaddr - $fdtaddr" 437 438 #define CONFIG_RAMBOOTCOMMAND \ 439 "setenv bootargs root=/dev/ram rw " \ 440 "console=$consoledev,$baudrate $othbootargs;" \ 441 "tftp $ramdiskaddr $ramdiskfile;" \ 442 "tftp $loadaddr $bootfile;" \ 443 "tftp $fdtaddr $fdtfile;" \ 444 "bootm $loadaddr $ramdiskaddr $fdtaddr" 445 446 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 447 448 #endif /* __CONFIG_H */ 449