1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _AM33XX_CPU_H 12 #define _AM33XX_CPU_H 13 14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 15 #include <asm/types.h> 16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 17 18 #include <asm/arch/hardware.h> 19 20 #define CL_BIT(x) (0 << x) 21 22 /* Timer register bits */ 23 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 24 #define TCLR_AR BIT(1) /* Auto reload */ 25 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 26 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 27 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 28 #define TCLR_CE BIT(6) /* compare mode enable */ 29 #define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ 30 #define TCLR_TCM BIT(8) /* edge detection of input pin*/ 31 #define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ 32 #define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ 33 #define TCLR_CAPTMODE BIT(13) /* capture mode */ 34 #define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ 35 36 #define TCFG_RESET BIT(0) /* software reset */ 37 #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ 38 #define TCFG_IDLEMOD_SHIFT (2) /* power management */ 39 /* device type */ 40 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 41 #define TST_DEVICE 0x0 42 #define EMU_DEVICE 0x1 43 #define HS_DEVICE 0x2 44 #define GP_DEVICE 0x3 45 46 /* cpu-id for AM43XX AM33XX and TI81XX family */ 47 #define AM437X 0xB98C 48 #define AM335X 0xB944 49 #define TI81XX 0xB81E 50 #define DEVICE_ID (CTRL_BASE + 0x0600) 51 #define DEVICE_ID_MASK 0x1FFF 52 #define PACKAGE_TYPE_SHIFT 16 53 #define PACKAGE_TYPE_MASK (3 << 16) 54 55 /* Package Type */ 56 #define PACKAGE_TYPE_UNDEFINED 0x0 57 #define PACKAGE_TYPE_ZCZ 0x1 58 #define PACKAGE_TYPE_ZCE 0x2 59 #define PACKAGE_TYPE_RESERVED 0x3 60 61 /* MPU max frequencies */ 62 #define AM335X_ZCZ_300 0x1FEF 63 #define AM335X_ZCZ_600 0x1FAF 64 #define AM335X_ZCZ_720 0x1F2F 65 #define AM335X_ZCZ_800 0x1E2F 66 #define AM335X_ZCZ_1000 0x1C2F 67 #define AM335X_ZCE_300 0x1FDF 68 #define AM335X_ZCE_600 0x1F9F 69 70 /* This gives the status of the boot mode pins on the evm */ 71 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 72 | BIT(3) | BIT(4)) 73 74 #define PRM_RSTCTRL_RESET 0x01 75 #define PRM_RSTST_WARM_RESET_MASK 0x232 76 77 #ifndef __KERNEL_STRICT_NAMES 78 #ifndef __ASSEMBLY__ 79 #include <asm/ti-common/omap_wdt.h> 80 81 #ifndef CONFIG_AM43XX 82 /* Encapsulating core pll registers */ 83 struct cm_wkuppll { 84 unsigned int wkclkstctrl; /* offset 0x00 */ 85 unsigned int wkctrlclkctrl; /* offset 0x04 */ 86 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 87 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 88 unsigned int timer0clkctrl; /* offset 0x10 */ 89 unsigned int resv2[3]; 90 unsigned int idlestdpllmpu; /* offset 0x20 */ 91 unsigned int sscdeltamstepdllmpu; /* off 0x24 */ 92 unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */ 93 unsigned int clkseldpllmpu; /* offset 0x2c */ 94 unsigned int resv4[1]; 95 unsigned int idlestdpllddr; /* offset 0x34 */ 96 unsigned int resv5[2]; 97 unsigned int clkseldpllddr; /* offset 0x40 */ 98 unsigned int resv6[4]; 99 unsigned int clkseldplldisp; /* offset 0x54 */ 100 unsigned int resv7[1]; 101 unsigned int idlestdpllcore; /* offset 0x5c */ 102 unsigned int resv8[2]; 103 unsigned int clkseldpllcore; /* offset 0x68 */ 104 unsigned int resv9[1]; 105 unsigned int idlestdpllper; /* offset 0x70 */ 106 unsigned int resv10[2]; 107 unsigned int clkdcoldodpllper; /* offset 0x7c */ 108 unsigned int divm4dpllcore; /* offset 0x80 */ 109 unsigned int divm5dpllcore; /* offset 0x84 */ 110 unsigned int clkmoddpllmpu; /* offset 0x88 */ 111 unsigned int clkmoddpllper; /* offset 0x8c */ 112 unsigned int clkmoddpllcore; /* offset 0x90 */ 113 unsigned int clkmoddpllddr; /* offset 0x94 */ 114 unsigned int clkmoddplldisp; /* offset 0x98 */ 115 unsigned int clkseldpllper; /* offset 0x9c */ 116 unsigned int divm2dpllddr; /* offset 0xA0 */ 117 unsigned int divm2dplldisp; /* offset 0xA4 */ 118 unsigned int divm2dpllmpu; /* offset 0xA8 */ 119 unsigned int divm2dpllper; /* offset 0xAC */ 120 unsigned int resv11[1]; 121 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 122 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 123 unsigned int wkup_adctscctrl; /* offset 0xBC */ 124 unsigned int resv12; 125 unsigned int timer1clkctrl; /* offset 0xC4 */ 126 unsigned int resv13[4]; 127 unsigned int divm6dpllcore; /* offset 0xD8 */ 128 }; 129 130 /** 131 * Encapsulating peripheral functional clocks 132 * pll registers 133 */ 134 struct cm_perpll { 135 unsigned int l4lsclkstctrl; /* offset 0x00 */ 136 unsigned int l3sclkstctrl; /* offset 0x04 */ 137 unsigned int l4fwclkstctrl; /* offset 0x08 */ 138 unsigned int l3clkstctrl; /* offset 0x0c */ 139 unsigned int resv1; 140 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 141 unsigned int lcdclkctrl; /* offset 0x18 */ 142 unsigned int usb0clkctrl; /* offset 0x1C */ 143 unsigned int resv2; 144 unsigned int tptc0clkctrl; /* offset 0x24 */ 145 unsigned int emifclkctrl; /* offset 0x28 */ 146 unsigned int ocmcramclkctrl; /* offset 0x2c */ 147 unsigned int gpmcclkctrl; /* offset 0x30 */ 148 unsigned int mcasp0clkctrl; /* offset 0x34 */ 149 unsigned int uart5clkctrl; /* offset 0x38 */ 150 unsigned int mmc0clkctrl; /* offset 0x3C */ 151 unsigned int elmclkctrl; /* offset 0x40 */ 152 unsigned int i2c2clkctrl; /* offset 0x44 */ 153 unsigned int i2c1clkctrl; /* offset 0x48 */ 154 unsigned int spi0clkctrl; /* offset 0x4C */ 155 unsigned int spi1clkctrl; /* offset 0x50 */ 156 unsigned int resv3[3]; 157 unsigned int l4lsclkctrl; /* offset 0x60 */ 158 unsigned int l4fwclkctrl; /* offset 0x64 */ 159 unsigned int mcasp1clkctrl; /* offset 0x68 */ 160 unsigned int uart1clkctrl; /* offset 0x6C */ 161 unsigned int uart2clkctrl; /* offset 0x70 */ 162 unsigned int uart3clkctrl; /* offset 0x74 */ 163 unsigned int uart4clkctrl; /* offset 0x78 */ 164 unsigned int timer7clkctrl; /* offset 0x7C */ 165 unsigned int timer2clkctrl; /* offset 0x80 */ 166 unsigned int timer3clkctrl; /* offset 0x84 */ 167 unsigned int timer4clkctrl; /* offset 0x88 */ 168 unsigned int resv4[8]; 169 unsigned int gpio1clkctrl; /* offset 0xAC */ 170 unsigned int gpio2clkctrl; /* offset 0xB0 */ 171 unsigned int gpio3clkctrl; /* offset 0xB4 */ 172 unsigned int resv5; 173 unsigned int tpccclkctrl; /* offset 0xBC */ 174 unsigned int dcan0clkctrl; /* offset 0xC0 */ 175 unsigned int dcan1clkctrl; /* offset 0xC4 */ 176 unsigned int resv6; 177 unsigned int epwmss1clkctrl; /* offset 0xCC */ 178 unsigned int emiffwclkctrl; /* offset 0xD0 */ 179 unsigned int epwmss0clkctrl; /* offset 0xD4 */ 180 unsigned int epwmss2clkctrl; /* offset 0xD8 */ 181 unsigned int l3instrclkctrl; /* offset 0xDC */ 182 unsigned int l3clkctrl; /* Offset 0xE0 */ 183 unsigned int resv8[2]; 184 unsigned int timer5clkctrl; /* offset 0xEC */ 185 unsigned int timer6clkctrl; /* offset 0xF0 */ 186 unsigned int mmc1clkctrl; /* offset 0xF4 */ 187 unsigned int mmc2clkctrl; /* offset 0xF8 */ 188 unsigned int resv9[8]; 189 unsigned int l4hsclkstctrl; /* offset 0x11C */ 190 unsigned int l4hsclkctrl; /* offset 0x120 */ 191 unsigned int resv10[8]; 192 unsigned int cpswclkstctrl; /* offset 0x144 */ 193 unsigned int lcdcclkstctrl; /* offset 0x148 */ 194 }; 195 196 /* Encapsulating Display pll registers */ 197 struct cm_dpll { 198 unsigned int resv1; 199 unsigned int clktimer7clk; /* offset 0x04 */ 200 unsigned int clktimer2clk; /* offset 0x08 */ 201 unsigned int clktimer3clk; /* offset 0x0C */ 202 unsigned int clktimer4clk; /* offset 0x10 */ 203 unsigned int resv2; 204 unsigned int clktimer5clk; /* offset 0x18 */ 205 unsigned int clktimer6clk; /* offset 0x1C */ 206 unsigned int resv3[2]; 207 unsigned int clktimer1clk; /* offset 0x28 */ 208 unsigned int resv4[2]; 209 unsigned int clklcdcpixelclk; /* offset 0x34 */ 210 }; 211 212 struct prm_device_inst { 213 unsigned int prm_rstctrl; 214 unsigned int prm_rsttime; 215 unsigned int prm_rstst; 216 }; 217 #else 218 /* Encapsulating core pll registers */ 219 struct cm_wkuppll { 220 unsigned int resv0[136]; 221 unsigned int wkl4wkclkctrl; /* offset 0x220 */ 222 unsigned int resv1[7]; 223 unsigned int usbphy0clkctrl; /* offset 0x240 */ 224 unsigned int resv112; 225 unsigned int usbphy1clkctrl; /* offset 0x248 */ 226 unsigned int resv113[45]; 227 unsigned int wkclkstctrl; /* offset 0x300 */ 228 unsigned int resv2[15]; 229 unsigned int wkup_i2c0ctrl; /* offset 0x340 */ 230 unsigned int resv3; 231 unsigned int wkup_uart0ctrl; /* offset 0x348 */ 232 unsigned int resv4[5]; 233 unsigned int wkctrlclkctrl; /* offset 0x360 */ 234 unsigned int resv5; 235 unsigned int wkgpio0clkctrl; /* offset 0x368 */ 236 237 unsigned int resv6[109]; 238 unsigned int clkmoddpllcore; /* offset 0x520 */ 239 unsigned int idlestdpllcore; /* offset 0x524 */ 240 unsigned int resv61; 241 unsigned int clkseldpllcore; /* offset 0x52C */ 242 unsigned int resv7[2]; 243 unsigned int divm4dpllcore; /* offset 0x538 */ 244 unsigned int divm5dpllcore; /* offset 0x53C */ 245 unsigned int divm6dpllcore; /* offset 0x540 */ 246 247 unsigned int resv8[7]; 248 unsigned int clkmoddpllmpu; /* offset 0x560 */ 249 unsigned int idlestdpllmpu; /* offset 0x564 */ 250 unsigned int resv9; 251 unsigned int clkseldpllmpu; /* offset 0x56c */ 252 unsigned int divm2dpllmpu; /* offset 0x570 */ 253 254 unsigned int resv10[11]; 255 unsigned int clkmoddpllddr; /* offset 0x5A0 */ 256 unsigned int idlestdpllddr; /* offset 0x5A4 */ 257 unsigned int resv11; 258 unsigned int clkseldpllddr; /* offset 0x5AC */ 259 unsigned int divm2dpllddr; /* offset 0x5B0 */ 260 261 unsigned int resv12[11]; 262 unsigned int clkmoddpllper; /* offset 0x5E0 */ 263 unsigned int idlestdpllper; /* offset 0x5E4 */ 264 unsigned int resv13; 265 unsigned int clkseldpllper; /* offset 0x5EC */ 266 unsigned int divm2dpllper; /* offset 0x5F0 */ 267 unsigned int resv14[8]; 268 unsigned int clkdcoldodpllper; /* offset 0x614 */ 269 270 unsigned int resv15[2]; 271 unsigned int clkmoddplldisp; /* offset 0x620 */ 272 unsigned int resv16[2]; 273 unsigned int clkseldplldisp; /* offset 0x62C */ 274 unsigned int divm2dplldisp; /* offset 0x630 */ 275 }; 276 277 /* 278 * Encapsulating peripheral functional clocks 279 * pll registers 280 */ 281 struct cm_perpll { 282 unsigned int l3clkstctrl; /* offset 0x00 */ 283 unsigned int resv0[7]; 284 unsigned int l3clkctrl; /* Offset 0x20 */ 285 unsigned int resv112[7]; 286 unsigned int l3instrclkctrl; /* offset 0x40 */ 287 unsigned int resv2[3]; 288 unsigned int ocmcramclkctrl; /* offset 0x50 */ 289 unsigned int resv3[9]; 290 unsigned int tpccclkctrl; /* offset 0x78 */ 291 unsigned int resv4; 292 unsigned int tptc0clkctrl; /* offset 0x80 */ 293 294 unsigned int resv5[7]; 295 unsigned int l4hsclkctrl; /* offset 0x0A0 */ 296 unsigned int resv6; 297 unsigned int l4fwclkctrl; /* offset 0x0A8 */ 298 unsigned int resv7[85]; 299 unsigned int l3sclkstctrl; /* offset 0x200 */ 300 unsigned int resv8[7]; 301 unsigned int gpmcclkctrl; /* offset 0x220 */ 302 unsigned int resv9[5]; 303 unsigned int mcasp0clkctrl; /* offset 0x238 */ 304 unsigned int resv10; 305 unsigned int mcasp1clkctrl; /* offset 0x240 */ 306 unsigned int resv11; 307 unsigned int mmc2clkctrl; /* offset 0x248 */ 308 unsigned int resv12[3]; 309 unsigned int qspiclkctrl; /* offset 0x258 */ 310 unsigned int resv121; 311 unsigned int usb0clkctrl; /* offset 0x260 */ 312 unsigned int resv122; 313 unsigned int usb1clkctrl; /* offset 0x268 */ 314 unsigned int resv13[101]; 315 unsigned int l4lsclkstctrl; /* offset 0x400 */ 316 unsigned int resv14[7]; 317 unsigned int l4lsclkctrl; /* offset 0x420 */ 318 unsigned int resv15; 319 unsigned int dcan0clkctrl; /* offset 0x428 */ 320 unsigned int resv16; 321 unsigned int dcan1clkctrl; /* offset 0x430 */ 322 unsigned int resv17[13]; 323 unsigned int elmclkctrl; /* offset 0x468 */ 324 325 unsigned int resv18[3]; 326 unsigned int gpio1clkctrl; /* offset 0x478 */ 327 unsigned int resv19; 328 unsigned int gpio2clkctrl; /* offset 0x480 */ 329 unsigned int resv20; 330 unsigned int gpio3clkctrl; /* offset 0x488 */ 331 unsigned int resv41; 332 unsigned int gpio4clkctrl; /* offset 0x490 */ 333 unsigned int resv42; 334 unsigned int gpio5clkctrl; /* offset 0x498 */ 335 unsigned int resv21[3]; 336 337 unsigned int i2c1clkctrl; /* offset 0x4A8 */ 338 unsigned int resv22; 339 unsigned int i2c2clkctrl; /* offset 0x4B0 */ 340 unsigned int resv23[3]; 341 unsigned int mmc0clkctrl; /* offset 0x4C0 */ 342 unsigned int resv24; 343 unsigned int mmc1clkctrl; /* offset 0x4C8 */ 344 345 unsigned int resv25[13]; 346 unsigned int spi0clkctrl; /* offset 0x500 */ 347 unsigned int resv26; 348 unsigned int spi1clkctrl; /* offset 0x508 */ 349 unsigned int resv27[9]; 350 unsigned int timer2clkctrl; /* offset 0x530 */ 351 unsigned int resv28; 352 unsigned int timer3clkctrl; /* offset 0x538 */ 353 unsigned int resv29; 354 unsigned int timer4clkctrl; /* offset 0x540 */ 355 unsigned int resv30[5]; 356 unsigned int timer7clkctrl; /* offset 0x558 */ 357 358 unsigned int resv31[9]; 359 unsigned int uart1clkctrl; /* offset 0x580 */ 360 unsigned int resv32; 361 unsigned int uart2clkctrl; /* offset 0x588 */ 362 unsigned int resv33; 363 unsigned int uart3clkctrl; /* offset 0x590 */ 364 unsigned int resv34; 365 unsigned int uart4clkctrl; /* offset 0x598 */ 366 unsigned int resv35; 367 unsigned int uart5clkctrl; /* offset 0x5A0 */ 368 unsigned int resv36[5]; 369 unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */ 370 unsigned int resv361; 371 unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */ 372 unsigned int resv3611[79]; 373 374 unsigned int emifclkstctrl; /* offset 0x700 */ 375 unsigned int resv362[7]; 376 unsigned int emifclkctrl; /* offset 0x720 */ 377 unsigned int resv37[3]; 378 unsigned int emiffwclkctrl; /* offset 0x730 */ 379 unsigned int resv371; 380 unsigned int otfaemifclkctrl; /* offset 0x738 */ 381 unsigned int resv38[57]; 382 unsigned int lcdclkctrl; /* offset 0x820 */ 383 unsigned int resv39[183]; 384 unsigned int cpswclkstctrl; /* offset 0xB00 */ 385 unsigned int resv40[7]; 386 unsigned int cpgmac0clkctrl; /* offset 0xB20 */ 387 }; 388 389 struct cm_device_inst { 390 unsigned int cm_clkout1_ctrl; 391 unsigned int cm_dll_ctrl; 392 }; 393 394 struct prm_device_inst { 395 unsigned int prm_rstctrl; 396 unsigned int prm_rstst; 397 }; 398 399 struct cm_dpll { 400 unsigned int resv1; 401 unsigned int clktimer2clk; /* offset 0x04 */ 402 unsigned int resv2[11]; 403 unsigned int clkselmacclk; /* offset 0x34 */ 404 }; 405 #endif /* CONFIG_AM43XX */ 406 407 /* Control Module RTC registers */ 408 struct cm_rtc { 409 unsigned int rtcclkctrl; /* offset 0x0 */ 410 unsigned int clkstctrl; /* offset 0x4 */ 411 }; 412 413 /* Timer 32 bit registers */ 414 struct gptimer { 415 unsigned int tidr; /* offset 0x00 */ 416 unsigned char res1[12]; 417 unsigned int tiocp_cfg; /* offset 0x10 */ 418 unsigned char res2[12]; 419 unsigned int tier; /* offset 0x20 */ 420 unsigned int tistatr; /* offset 0x24 */ 421 unsigned int tistat; /* offset 0x28 */ 422 unsigned int tisr; /* offset 0x2c */ 423 unsigned int tcicr; /* offset 0x30 */ 424 unsigned int twer; /* offset 0x34 */ 425 unsigned int tclr; /* offset 0x38 */ 426 unsigned int tcrr; /* offset 0x3c */ 427 unsigned int tldr; /* offset 0x40 */ 428 unsigned int ttgr; /* offset 0x44 */ 429 unsigned int twpc; /* offset 0x48 */ 430 unsigned int tmar; /* offset 0x4c */ 431 unsigned int tcar1; /* offset 0x50 */ 432 unsigned int tscir; /* offset 0x54 */ 433 unsigned int tcar2; /* offset 0x58 */ 434 }; 435 436 /* UART Registers */ 437 struct uart_sys { 438 unsigned int resv1[21]; 439 unsigned int uartsyscfg; /* offset 0x54 */ 440 unsigned int uartsyssts; /* offset 0x58 */ 441 }; 442 443 /* VTP Registers */ 444 struct vtp_reg { 445 unsigned int vtp0ctrlreg; 446 }; 447 448 /* Control Status Register */ 449 struct ctrl_stat { 450 unsigned int resv1[16]; 451 unsigned int statusreg; /* ofset 0x40 */ 452 unsigned int resv2[51]; 453 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 454 unsigned int resv3[319]; 455 unsigned int dev_attr; 456 }; 457 458 /* AM33XX GPIO registers */ 459 #define OMAP_GPIO_REVISION 0x0000 460 #define OMAP_GPIO_SYSCONFIG 0x0010 461 #define OMAP_GPIO_SYSSTATUS 0x0114 462 #define OMAP_GPIO_IRQSTATUS1 0x002c 463 #define OMAP_GPIO_IRQSTATUS2 0x0030 464 #define OMAP_GPIO_IRQSTATUS_SET_0 0x0034 465 #define OMAP_GPIO_IRQSTATUS_SET_1 0x0038 466 #define OMAP_GPIO_CTRL 0x0130 467 #define OMAP_GPIO_OE 0x0134 468 #define OMAP_GPIO_DATAIN 0x0138 469 #define OMAP_GPIO_DATAOUT 0x013c 470 #define OMAP_GPIO_LEVELDETECT0 0x0140 471 #define OMAP_GPIO_LEVELDETECT1 0x0144 472 #define OMAP_GPIO_RISINGDETECT 0x0148 473 #define OMAP_GPIO_FALLINGDETECT 0x014c 474 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 475 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 476 #define OMAP_GPIO_CLEARDATAOUT 0x0190 477 #define OMAP_GPIO_SETDATAOUT 0x0194 478 479 /* Control Device Register */ 480 481 /* Control Device Register */ 482 #define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F 483 #define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8 484 #define MREQPRIO_1_DSS_MASK 0xFFFFFF8F 485 486 struct ctrl_dev { 487 unsigned int deviceid; /* offset 0x00 */ 488 unsigned int resv1[7]; 489 unsigned int usb_ctrl0; /* offset 0x20 */ 490 unsigned int resv2; 491 unsigned int usb_ctrl1; /* offset 0x28 */ 492 unsigned int resv3; 493 unsigned int macid0l; /* offset 0x30 */ 494 unsigned int macid0h; /* offset 0x34 */ 495 unsigned int macid1l; /* offset 0x38 */ 496 unsigned int macid1h; /* offset 0x3c */ 497 unsigned int resv4[4]; 498 unsigned int miisel; /* offset 0x50 */ 499 unsigned int resv5[7]; 500 unsigned int mreqprio_0; /* offset 0x70 */ 501 unsigned int mreqprio_1; /* offset 0x74 */ 502 unsigned int resv6[97]; 503 unsigned int efuse_sma; /* offset 0x1FC */ 504 }; 505 506 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */ 507 #define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0 508 #define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0 509 #define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800 510 511 struct l3f_cfg_bwlimiter { 512 u32 padding0[2]; 513 u32 modena_init0_bw_fractional; 514 u32 modena_init0_bw_integer; 515 u32 modena_init0_watermark_0; 516 }; 517 518 /* gmii_sel register defines */ 519 #define GMII1_SEL_MII 0x0 520 #define GMII1_SEL_RMII 0x1 521 #define GMII1_SEL_RGMII 0x2 522 #define GMII2_SEL_MII 0x0 523 #define GMII2_SEL_RMII 0x4 524 #define GMII2_SEL_RGMII 0x8 525 #define RGMII1_IDMODE BIT(4) 526 #define RGMII2_IDMODE BIT(5) 527 #define RMII1_IO_CLK_EN BIT(6) 528 #define RMII2_IO_CLK_EN BIT(7) 529 530 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) 531 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) 532 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) 533 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) 534 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) 535 536 /* PWMSS */ 537 struct pwmss_regs { 538 unsigned int idver; 539 unsigned int sysconfig; 540 unsigned int clkconfig; 541 unsigned int clkstatus; 542 }; 543 #define ECAP_CLK_EN BIT(0) 544 #define ECAP_CLK_STOP_REQ BIT(1) 545 #define EPWM_CLK_EN BIT(8) 546 #define EPWM_CLK_STOP_REQ BIT(9) 547 548 struct pwmss_ecap_regs { 549 unsigned int tsctr; 550 unsigned int ctrphs; 551 unsigned int cap1; 552 unsigned int cap2; 553 unsigned int cap3; 554 unsigned int cap4; 555 unsigned int resv1[4]; 556 unsigned short ecctl1; 557 unsigned short ecctl2; 558 }; 559 560 struct pwmss_epwm_regs { 561 unsigned short tbctl; 562 unsigned short tbsts; 563 unsigned short tbphshr; 564 unsigned short tbphs; 565 unsigned short tbcnt; 566 unsigned short tbprd; 567 unsigned short res1; 568 unsigned short cmpctl; 569 unsigned short cmpahr; 570 unsigned short cmpa; 571 unsigned short cmpb; 572 unsigned short aqctla; 573 unsigned short aqctlb; 574 unsigned short aqsfrc; 575 unsigned short aqcsfrc; 576 unsigned short dbctl; 577 unsigned short dbred; 578 unsigned short dbfed; 579 unsigned short tzsel; 580 unsigned short tzctl; 581 unsigned short tzflg; 582 unsigned short tzclr; 583 unsigned short tzfrc; 584 unsigned short etsel; 585 unsigned short etps; 586 unsigned short etflg; 587 unsigned short etclr; 588 unsigned short etfrc; 589 unsigned short pcctl; 590 unsigned int res2[66]; 591 unsigned short hrcnfg; 592 }; 593 594 /* Capture Control register 2 */ 595 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6) 596 #define ECTRL2_MDSL_ECAP BIT(9) 597 #define ECTRL2_CTRSTP_FREERUN BIT(4) 598 #define ECTRL2_PLSL_LOW BIT(10) 599 #define ECTRL2_SYNC_EN BIT(5) 600 601 #endif /* __ASSEMBLY__ */ 602 #endif /* __KERNEL_STRICT_NAMES */ 603 604 #endif /* _AM33XX_CPU_H */ 605