1Intel Bay Trail FSP UPD Binding
2===============================
3
4The device tree node which describes the overriding of the Intel Bay Trail FSP
5UPD data for configuring the SoC.
6
7All properties can be found within the `upd-region` struct in
8arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
9Intel's FSP Binary Configuration Tool for Bay Trail.  This list of properties is
10matched up to Intel's E3800 FSPv4 release.
11
12# Boolean properties:
13
14- fsp,enable-sdio
15- fsp,enable-sdcard
16- fsp,enable-hsuart0
17- fsp,enable-hsuart1
18- fsp,enable-spi
19- fsp,enable-sata
20- fsp,enable-azalia
21- fsp,enable-xhci
22- fsp,enable-lpe
23- fsp,lpss-sio-enable-pci-mode
24- fsp,enable-dma0
25- fsp,enable-dma1
26- fsp,enable-i2-c0
27- fsp,enable-i2-c1
28- fsp,enable-i2-c2
29- fsp,enable-i2-c3
30- fsp,enable-i2-c4
31- fsp,enable-i2-c5
32- fsp,enable-i2-c6
33- fsp,enable-pwm0
34- fsp,enable-pwm1
35- fsp,enable-hsi
36- fsp,mrc-debug-msg
37- fsp,isp-enable
38- fsp,scc-enable-pci-mode
39- fsp,igd-render-standby
40- fsp,txe-uma-enable
41- fsp,emmc45-ddr50-enabled
42- fsp,emmc45-hs200-enabled
43- fsp,enable-igd
44- fsp,enable-memory-down
45
46If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
47"fsp,memory-down-params{};" to specify how your memory is configured.  If you do
48not set "fsp,enable-memory-down", then the DIMM SPD information will be
49discovered by the FSP and used to setup main memory.
50
51
52# Integer properties:
53
54- fsp,mrc-init-tseg-size
55- fsp,mrc-init-mmio-size
56- fsp,mrc-init-spd-addr1
57- fsp,mrc-init-spd-addr2
58- fsp,emmc-boot-mode
59- fsp,sata-mode
60- fsp,igd-dvmt50-pre-alloc
61- fsp,aperture-size
62- fsp,gtt-size
63- fsp,os-selection
64- fsp,emmc45-retune-timer-value
65
66- fsp,memory-down-params {
67
68	# Boolean properties:
69
70	- fsp,dimm-0-enable
71	- fsp,dimm-1-enable
72
73	# Integer properties:
74
75	- fsp,dram-speed:
76	  0x0: "800 MHz"
77	  0x1: "1066 MHz"
78	  0x2: "1333 MHz"
79	  0x3: "1600 MHz"
80
81	- fsp,dram-type
82	  0x0: "DDR3"
83	  0x1: "DDR3L"
84	  0x2: "DDR3U"
85	  0x4: "LPDDR2"
86	  0x5: "LPDDR3"
87	  0x6: "DDR4"
88
89	- fsp,dimm-width
90	  0x0: "x8"
91	  0x1: "x16"
92	  0x2: "x32"
93
94	- fsp,dimm-density
95	  0x0: "1 Gbit"
96	  0x1: "2 Gbit"
97	  0x2: "4 Gbit"
98	  0x3: "8 Gbit"
99
100	- fsp,dimm-bus-width
101	  0x0: "8 bits"
102	  0x1: "16 bits"
103	  0x2: "32 bits"
104	  0x3: "64 bits"
105
106	- fsp,dimm-sides
107	  0x0: "1 rank"
108	  0x1: "2 ranks"
109
110	- fsp,dimm-tcl
111	- fsp,dimm-trpt-rcd
112	- fsp,dimm-twr
113	- fsp,dimm-twtr
114	- fsp,dimm-trrd
115	- fsp,dimm-trtp
116	- fsp,dimm-tfaw
117};
118
119
120Example (from MinnowMax Dual Core):
121-----------------------------------
122
123/ {
124	...
125
126	fsp {
127		compatible = "intel,baytrail-fsp";
128		fsp,mrc-init-tseg-size = <0>;
129		fsp,mrc-init-mmio-size = <0x800>;
130		fsp,mrc-init-spd-addr1 = <0xa0>;
131		fsp,mrc-init-spd-addr2 = <0xa2>;
132		fsp,emmc-boot-mode = <2>;
133		fsp,enable-sdio;
134		fsp,enable-sdcard;
135		fsp,enable-hsuart1;
136		fsp,enable-spi;
137		fsp,enable-sata;
138		fsp,sata-mode = <1>;
139		fsp,enable-xhci;
140		fsp,enable-lpe;
141		fsp,lpss-sio-enable-pci-mode;
142		fsp,enable-dma0;
143		fsp,enable-dma1;
144		fsp,enable-i2c0;
145		fsp,enable-i2c1;
146		fsp,enable-i2c2;
147		fsp,enable-i2c3;
148		fsp,enable-i2c4;
149		fsp,enable-i2c5;
150		fsp,enable-i2c6;
151		fsp,enable-pwm0;
152		fsp,enable-pwm1;
153		fsp,igd-dvmt50-pre-alloc = <2>;
154		fsp,aperture-size = <2>;
155		fsp,gtt-size = <2>;
156		fsp,serial-debug-port-address = <0x3f8>;
157		fsp,serial-debug-port-type = <1>;
158		fsp,mrc-debug-msg;
159		fsp,scc-enable-pci-mode;
160		fsp,os-selection = <4>;
161		fsp,emmc45-ddr50-enabled;
162		fsp,emmc45-retune-timer-value = <8>;
163		fsp,enable-igd;
164		fsp,enable-memory-down;
165		fsp,memory-down-params {
166			compatible = "intel,baytrail-fsp-mdp";
167			fsp,dram-speed = <1>;
168			fsp,dram-type = <1>;
169			fsp,dimm-0-enable;
170			fsp,dimm-width = <1>;
171			fsp,dimm-density = <2>;
172			fsp,dimm-bus-width = <3>;
173			fsp,dimm-sides = <0>;
174			fsp,dimm-tcl = <0xb>;
175			fsp,dimm-trpt-rcd = <0xb>;
176			fsp,dimm-twr = <0xc>;
177			fsp,dimm-twtr = <6>;
178			fsp,dimm-trrd = <6>;
179			fsp,dimm-trtp = <6>;
180			fsp,dimm-tfaw = <0x14>;
181		};
182	};
183
184	...
185};
186