1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/irq.h> 9 #include <asm/pci.h> 10 #include <asm/post.h> 11 #include <asm/processor.h> 12 #include <asm/arch/device.h> 13 #include <asm/arch/qemu.h> 14 #include <asm/fw_cfg.h> 15 16 static bool i440fx; 17 18 static void enable_pm_piix(void) 19 { 20 u8 en; 21 u16 cmd; 22 23 /* Set the PM I/O base */ 24 x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); 25 26 /* Enable access to the PM I/O space */ 27 cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND); 28 cmd |= PCI_COMMAND_IO; 29 x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); 30 31 /* PM I/O Space Enable (PMIOSE) */ 32 en = x86_pci_read_config8(PIIX_PM, PMREGMISC); 33 en |= PMIOSE; 34 x86_pci_write_config8(PIIX_PM, PMREGMISC, en); 35 } 36 37 static void enable_pm_ich9(void) 38 { 39 /* Set the PM I/O base */ 40 x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); 41 } 42 43 static void qemu_chipset_init(void) 44 { 45 u16 device, xbcs; 46 int pam, i; 47 48 /* 49 * i440FX and Q35 chipset have different PAM register offset, but with 50 * the same bitfield layout. Here we determine the offset based on its 51 * PCI device ID. 52 */ 53 device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); 54 i440fx = (device == PCI_DEVICE_ID_INTEL_82441); 55 pam = i440fx ? I440FX_PAM : Q35_PAM; 56 57 /* 58 * Initialize Programmable Attribute Map (PAM) Registers 59 * 60 * Configure legacy segments C/D/E/F to system RAM 61 */ 62 for (i = 0; i < PAM_NUM; i++) 63 x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); 64 65 if (i440fx) { 66 /* 67 * Enable legacy IDE I/O ports decode 68 * 69 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. 70 * However Linux ata_piix driver does sanity check on these two 71 * registers to see whether legacy ports decode is turned on. 72 * This is to make Linux ata_piix driver happy. 73 */ 74 x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); 75 x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); 76 77 /* Enable I/O APIC */ 78 xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); 79 xbcs |= APIC_EN; 80 x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); 81 82 enable_pm_piix(); 83 } else { 84 /* Configure PCIe ECAM base address */ 85 x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, 86 CONFIG_PCIE_ECAM_BASE | BAR_EN); 87 88 enable_pm_ich9(); 89 } 90 91 qemu_fwcfg_init(); 92 } 93 94 int arch_cpu_init(void) 95 { 96 int ret; 97 98 post_code(POST_CPU_INIT); 99 100 ret = x86_cpu_init_f(); 101 if (ret) 102 return ret; 103 104 return 0; 105 } 106 107 #ifndef CONFIG_EFI_STUB 108 int print_cpuinfo(void) 109 { 110 post_code(POST_CPU_INFO); 111 return default_print_cpuinfo(); 112 } 113 #endif 114 115 void reset_cpu(ulong addr) 116 { 117 /* cold reset */ 118 x86_full_reset(); 119 } 120 121 int arch_early_init_r(void) 122 { 123 qemu_chipset_init(); 124 125 return 0; 126 } 127 128 #ifdef CONFIG_GENERATE_MP_TABLE 129 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) 130 { 131 u8 irq; 132 133 if (i440fx) { 134 /* 135 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not 136 * connected to I/O APIC INTPIN#16-19. Instead they are routed 137 * to an irq number controled by the PIRQ routing register. 138 */ 139 irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), 140 PCI_INTERRUPT_LINE); 141 } else { 142 /* 143 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. 144 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. 145 */ 146 irq = pirq < 8 ? pirq + 16 : pirq + 12; 147 } 148 149 return irq; 150 } 151 #endif 152