1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 /* 7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 8 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 9 * consisting of a standard header and a device-specific set of registers. PCI 10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 11 * other things). Within the PCI configuration space, the GPIOBASE register 12 * tells us where in the device's I/O region we can find more registers to 13 * actually access the GPIOs. 14 * 15 * PCI bus/device/function 0:1f:0 => PCI config registers 16 * PCI config register "GPIOBASE" 17 * PCI I/O space + [GPIOBASE] => start of GPIO registers 18 * GPIO registers => gpio pin function, direction, value 19 * 20 * 21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 22 * ICH versions have more, but the decoding the matrix that describes them is 23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 24 * but they will ONLY work for certain unspecified chipsets because the offset 25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 26 * reserved or subject to arcane restrictions. 27 */ 28 29 #include <common.h> 30 #include <dm.h> 31 #include <errno.h> 32 #include <fdtdec.h> 33 #include <pci.h> 34 #include <asm/gpio.h> 35 #include <asm/io.h> 36 #include <asm/pci.h> 37 38 #define GPIO_PER_BANK 32 39 40 struct ich6_bank_priv { 41 /* These are I/O addresses */ 42 uint16_t use_sel; 43 uint16_t io_sel; 44 uint16_t lvl; 45 }; 46 47 #define GPIO_USESEL_OFFSET(x) (x) 48 #define GPIO_IOSEL_OFFSET(x) (x + 4) 49 #define GPIO_LVL_OFFSET(x) (x + 8) 50 51 #define IOPAD_MODE_MASK 0x7 52 #define IOPAD_PULL_ASSIGN_SHIFT 7 53 #define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT) 54 #define IOPAD_PULL_STRENGTH_SHIFT 9 55 #define IOPAD_PULL_STRENGTH_MASK (0x3 << IOPAD_PULL_STRENGTH_SHIFT) 56 57 /* TODO: Move this to device tree, or platform data */ 58 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) 59 { 60 gd->arch.gpio_map = map; 61 } 62 63 static int gpio_ich6_get_base(unsigned long base) 64 { 65 pci_dev_t pci_dev; /* handle for 0:1f:0 */ 66 u8 tmpbyte; 67 u16 tmpword; 68 u32 tmplong; 69 70 /* Where should it be? */ 71 pci_dev = PCI_BDF(0, 0x1f, 0); 72 73 /* Is the device present? */ 74 tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID); 75 if (tmpword != PCI_VENDOR_ID_INTEL) { 76 debug("%s: wrong VendorID\n", __func__); 77 return -ENODEV; 78 } 79 80 tmpword = x86_pci_read_config16(pci_dev, PCI_DEVICE_ID); 81 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); 82 /* 83 * We'd like to validate the Device ID too, but pretty much any 84 * value is either a) correct with slight differences, or b) 85 * correct but undocumented. We'll have to check a bunch of other 86 * things instead... 87 */ 88 89 /* I/O should already be enabled (it's a RO bit). */ 90 tmpword = x86_pci_read_config16(pci_dev, PCI_COMMAND); 91 if (!(tmpword & PCI_COMMAND_IO)) { 92 debug("%s: device IO not enabled\n", __func__); 93 return -ENODEV; 94 } 95 96 /* Header Type must be normal (bits 6-0 only; see spec.) */ 97 tmpbyte = x86_pci_read_config8(pci_dev, PCI_HEADER_TYPE); 98 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 99 debug("%s: invalid Header type\n", __func__); 100 return -ENODEV; 101 } 102 103 /* Base Class must be a bridge device */ 104 tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_CODE); 105 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 106 debug("%s: invalid class\n", __func__); 107 return -ENODEV; 108 } 109 /* Sub Class must be ISA */ 110 tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); 111 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 112 debug("%s: invalid subclass\n", __func__); 113 return -ENODEV; 114 } 115 116 /* Programming Interface must be 0x00 (no others exist) */ 117 tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_PROG); 118 if (tmpbyte != 0x00) { 119 debug("%s: invalid interface type\n", __func__); 120 return -ENODEV; 121 } 122 123 /* 124 * GPIOBASE moved to its current offset with ICH6, but prior to 125 * that it was unused (or undocumented). Check that it looks 126 * okay: not all ones or zeros. 127 * 128 * Note we don't need check bit0 here, because the Tunnel Creek 129 * GPIO base address register bit0 is reserved (read returns 0), 130 * while on the Ivybridge the bit0 is used to indicate it is an 131 * I/O space. 132 */ 133 tmplong = x86_pci_read_config32(pci_dev, base); 134 if (tmplong == 0x00000000 || tmplong == 0xffffffff) { 135 debug("%s: unexpected BASE value\n", __func__); 136 return -ENODEV; 137 } 138 139 /* 140 * Okay, I guess we're looking at the right device. The actual 141 * GPIO registers are in the PCI device's I/O space, starting 142 * at the offset that we just read. Bit 0 indicates that it's 143 * an I/O address, not a memory address, so mask that off. 144 */ 145 return tmplong & 0xfffc; 146 } 147 148 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value) 149 { 150 u32 val; 151 152 val = inl(base); 153 if (value) 154 val |= (1UL << offset); 155 else 156 val &= ~(1UL << offset); 157 outl(val, base); 158 159 return 0; 160 } 161 162 static int _ich6_gpio_set_function(uint16_t base, unsigned offset, int func) 163 { 164 u32 val; 165 166 if (func) { 167 val = inl(base); 168 val |= (1UL << offset); 169 outl(val, base); 170 } else { 171 val = inl(base); 172 val &= ~(1UL << offset); 173 outl(val, base); 174 } 175 176 return 0; 177 } 178 179 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir) 180 { 181 u32 val; 182 183 if (!dir) { 184 val = inl(base); 185 val |= (1UL << offset); 186 outl(val, base); 187 } else { 188 val = inl(base); 189 val &= ~(1UL << offset); 190 outl(val, base); 191 } 192 193 return 0; 194 } 195 196 static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) 197 { 198 u32 gpio_offset[2]; 199 int pad_offset; 200 int val; 201 int ret; 202 const void *prop; 203 204 /* 205 * GPIO node is not mandatory, so we only do the 206 * pinmuxing if the node exist. 207 */ 208 ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset", 209 gpio_offset, 2); 210 if (!ret) { 211 /* Do we want to force the GPIO mode? */ 212 prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio", 213 NULL); 214 if (prop) 215 _ich6_gpio_set_function(GPIO_USESEL_OFFSET 216 (gpiobase) + 217 gpio_offset[0], 218 gpio_offset[1], 1); 219 220 val = 221 fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1); 222 if (val != -1) 223 _ich6_gpio_set_direction(GPIO_IOSEL_OFFSET 224 (gpiobase) + 225 gpio_offset[0], 226 gpio_offset[1], val); 227 228 val = 229 fdtdec_get_int(gd->fdt_blob, pin_node, "output-value", -1); 230 if (val != -1) 231 _ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase) 232 + gpio_offset[0], 233 gpio_offset[1], val); 234 } 235 236 /* if iobase is present, let's configure the pad */ 237 if (iobase != -1) { 238 int iobase_addr; 239 240 /* 241 * The offset for the same pin for the IOBASE and GPIOBASE are 242 * different, so instead of maintaining a lookup table, 243 * the device tree should provide directly the correct 244 * value for both mapping. 245 */ 246 pad_offset = 247 fdtdec_get_int(gd->fdt_blob, pin_node, "pad-offset", -1); 248 if (pad_offset == -1) { 249 debug("%s: Invalid register io offset %d\n", 250 __func__, pad_offset); 251 return -EINVAL; 252 } 253 254 /* compute the absolute pad address */ 255 iobase_addr = iobase + pad_offset; 256 257 /* 258 * Do we need to set a specific function mode? 259 * If someone put also 'mode-gpio', this option will 260 * be just ignored by the controller 261 */ 262 val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1); 263 if (val != -1) 264 clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val); 265 266 /* Configure the pull-up/down if needed */ 267 val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1); 268 if (val != -1) 269 clrsetbits_le32(iobase_addr, 270 IOPAD_PULL_ASSIGN_MASK, 271 val << IOPAD_PULL_ASSIGN_SHIFT); 272 273 val = 274 fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength", -1); 275 if (val != -1) 276 clrsetbits_le32(iobase_addr, 277 IOPAD_PULL_STRENGTH_MASK, 278 val << IOPAD_PULL_STRENGTH_SHIFT); 279 280 debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset, 281 readl(iobase_addr)); 282 } 283 284 return 0; 285 } 286 287 int gpio_ich6_pinctrl_init(void) 288 { 289 int pin_node; 290 int node; 291 int ret; 292 int gpiobase; 293 int iobase_offset; 294 int iobase = -1; 295 296 /* 297 * Get the memory/io base address to configure every pins. 298 * IOBASE is used to configure the mode/pads 299 * GPIOBASE is used to configure the direction and default value 300 */ 301 gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE); 302 if (gpiobase < 0) { 303 debug("%s: invalid GPIOBASE address (%08x)\n", __func__, 304 gpiobase); 305 return -EINVAL; 306 } 307 308 /* This is not an error to not have a pinctrl node */ 309 node = 310 fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_X86_PINCTRL); 311 if (node <= 0) { 312 debug("%s: no pinctrl node\n", __func__); 313 return 0; 314 } 315 316 /* 317 * Get the IOBASE, this is not mandatory as this is not 318 * supported by all the CPU 319 */ 320 iobase_offset = fdtdec_get_int(gd->fdt_blob, node, "io-base", -1); 321 if (iobase_offset == -1) { 322 debug("%s: io-base offset not present\n", __func__); 323 } else { 324 iobase = gpio_ich6_get_base(iobase_offset); 325 if (iobase < 0) { 326 debug("%s: invalid IOBASE address (%08x)\n", __func__, 327 iobase); 328 return -EINVAL; 329 } 330 } 331 332 for (pin_node = fdt_first_subnode(gd->fdt_blob, node); 333 pin_node > 0; 334 pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) { 335 /* Configure the pin */ 336 ret = _gpio_ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node); 337 if (ret != 0) { 338 debug("%s: invalid configuration for the pin %d\n", 339 __func__, pin_node); 340 return ret; 341 } 342 } 343 344 return 0; 345 } 346 347 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) 348 { 349 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 350 u16 gpiobase; 351 int offset; 352 353 gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE); 354 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); 355 if (offset == -1) { 356 debug("%s: Invalid register offset %d\n", __func__, offset); 357 return -EINVAL; 358 } 359 plat->base_addr = gpiobase + offset; 360 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, 361 "bank-name", NULL); 362 363 return 0; 364 } 365 366 static int ich6_gpio_probe(struct udevice *dev) 367 { 368 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 369 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 370 struct ich6_bank_priv *bank = dev_get_priv(dev); 371 372 if (gd->arch.gpio_map) { 373 setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); 374 gd->arch.gpio_map = NULL; 375 } 376 377 uc_priv->gpio_count = GPIO_PER_BANK; 378 uc_priv->bank_name = plat->bank_name; 379 bank->use_sel = plat->base_addr; 380 bank->io_sel = plat->base_addr + 4; 381 bank->lvl = plat->base_addr + 8; 382 383 return 0; 384 } 385 386 static int ich6_gpio_request(struct udevice *dev, unsigned offset, 387 const char *label) 388 { 389 struct ich6_bank_priv *bank = dev_get_priv(dev); 390 u32 tmplong; 391 392 /* 393 * Make sure that the GPIO pin we want isn't already in use for some 394 * built-in hardware function. We have to check this for every 395 * requested pin. 396 */ 397 tmplong = inl(bank->use_sel); 398 if (!(tmplong & (1UL << offset))) { 399 debug("%s: gpio %d is reserved for internal use\n", __func__, 400 offset); 401 return -EPERM; 402 } 403 404 return 0; 405 } 406 407 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) 408 { 409 struct ich6_bank_priv *bank = dev_get_priv(dev); 410 411 return _ich6_gpio_set_direction(inl(bank->io_sel), offset, 0); 412 } 413 414 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, 415 int value) 416 { 417 int ret; 418 struct ich6_bank_priv *bank = dev_get_priv(dev); 419 420 ret = _ich6_gpio_set_direction(inl(bank->io_sel), offset, 1); 421 if (ret) 422 return ret; 423 424 return _ich6_gpio_set_value(bank->lvl, offset, value); 425 } 426 427 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) 428 { 429 struct ich6_bank_priv *bank = dev_get_priv(dev); 430 u32 tmplong; 431 int r; 432 433 tmplong = inl(bank->lvl); 434 r = (tmplong & (1UL << offset)) ? 1 : 0; 435 return r; 436 } 437 438 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, 439 int value) 440 { 441 struct ich6_bank_priv *bank = dev_get_priv(dev); 442 return _ich6_gpio_set_value(bank->lvl, offset, value); 443 } 444 445 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) 446 { 447 struct ich6_bank_priv *bank = dev_get_priv(dev); 448 u32 mask = 1UL << offset; 449 450 if (!(inl(bank->use_sel) & mask)) 451 return GPIOF_FUNC; 452 if (inl(bank->io_sel) & mask) 453 return GPIOF_INPUT; 454 else 455 return GPIOF_OUTPUT; 456 } 457 458 static const struct dm_gpio_ops gpio_ich6_ops = { 459 .request = ich6_gpio_request, 460 .direction_input = ich6_gpio_direction_input, 461 .direction_output = ich6_gpio_direction_output, 462 .get_value = ich6_gpio_get_value, 463 .set_value = ich6_gpio_set_value, 464 .get_function = ich6_gpio_get_function, 465 }; 466 467 static const struct udevice_id intel_ich6_gpio_ids[] = { 468 { .compatible = "intel,ich6-gpio" }, 469 { } 470 }; 471 472 U_BOOT_DRIVER(gpio_ich6) = { 473 .name = "gpio_ich6", 474 .id = UCLASS_GPIO, 475 .of_match = intel_ich6_gpio_ids, 476 .ops = &gpio_ich6_ops, 477 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, 478 .probe = ich6_gpio_probe, 479 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), 480 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), 481 }; 482