| 4bb54c2c | 14-Feb-2023 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234
Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map,
so bump the CBB ranges property to cover all of the 1 TiB add
arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234
Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map,
so bump the CBB ranges property to cover all of the 1 TiB address space.
This fixes an issue where some of the PCIe regions could not be remapped
because of they were outside the memory specified by the CBB's ranges
property.
Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 682e1c49 | 17-Oct-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Drop I2C iommus and dma-coherent properties
Drop the iommus and dma-coherent properties for the I2C controller
device tree nodes. These are only needed for the device tree nodes
that r
arm64: tegra: Drop I2C iommus and dma-coherent properties
Drop the iommus and dma-coherent properties for the I2C controller
device tree nodes. These are only needed for the device tree nodes
that represent the GPC DMA controller, since that is the device
performing the direct memory accesses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 320e0a70 | 19-Jan-2023 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Populate the XUDC node for Tegra234
Populate the Tegra XUSB device controller (XUDC) node for Tegra234.
This is based upon a patch from Wayne Chang <waynec@nvidia.com>.
Signed-off-by
arm64: tegra: Populate the XUDC node for Tegra234
Populate the Tegra XUSB device controller (XUDC) node for Tegra234.
This is based upon a patch from Wayne Chang <waynec@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| f19bb95d | 19-Jan-2023 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Add dma-coherent property for Tegra194 XUDC
DMA operations for XUSB device controller (XUDC) are coherent for
Tegra194 and so add the 'dma-coherent' property for this device.
Signed-o
arm64: tegra: Add dma-coherent property for Tegra194 XUDC
DMA operations for XUSB device controller (XUDC) are coherent for
Tegra194 and so add the 'dma-coherent' property for this device.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 260e8d42 | 16-Jan-2023 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Populate address/size cells for Tegra234 I2C
Populate the address and size cells properties for the I2C devices on
Tegra234.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-of
arm64: tegra: Populate address/size cells for Tegra234 I2C
Populate the address and size cells properties for the I2C devices on
Tegra234.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 79ed18d9 | 22-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 2838cfdd | 17-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
th
arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
the IP blocks on that bus. However, most of these devices can do DMA to
a larger address space, so translation of DMA addresses needs to happen
in a 64-bit address space.
Partially this was already done by the memory controller increasing that
address space by setting #address-cells and #size-cells to 2, but a full
DMA address translation would still cause truncation when traversing to
the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the
top-level bus and adjusting all "reg" and "ranges" properties of its
children.
While at it, also move the PCI and GPU nodes back under the top-level
bus where they belong. The were put outside of it to work around this
same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 29bcc1ea | 18-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fix duplicate regulator on Jetson TX1
When the top-level regulators were renamed, the 1.2V camera regulator
accidentally ended up with the same DT node name as the 1.8V camera
regulato
arm64: tegra: Fix duplicate regulator on Jetson TX1
When the top-level regulators were renamed, the 1.2V camera regulator
accidentally ended up with the same DT node name as the 1.8V camera
regulator.
Fixes: 097e01c61015 ("arm64: tegra: Rename top-level regulators")
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 1002a361 | 17-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
There's only a single clock for this IP block, so it doesn't need a
clock-names property.
Signed-off-by: Thierry Reding <treding@nvidia.co
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
There's only a single clock for this IP block, so it doesn't need a
clock-names property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 132b552c | 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
The compatible string list for SDHCI on Tegra234 should be
"nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci"
fallback. Us
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
The compatible string list for SDHCI on Tegra234 should be
"nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci"
fallback. Use that consistently for all SDHCI controllers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| d8e19478 | 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove unused reset-names for QSPI
The Tegra QSPI controller uses a single reset line, so there's no need
for a reset-names property. Remove such properties.
Signed-off-by: Thierry Re
arm64: tegra: Remove unused reset-names for QSPI
The Tegra QSPI controller uses a single reset line, so there's no need
for a reset-names property. Remove such properties.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| e9ddebc3 | 05-Sep-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove reset-names for QSPI
The Tegra QSPI controllers use a single reset control, so reset-names is
not necessary and therefore not specified in the DT bindings. Drop the
property fro
arm64: tegra: Remove reset-names for QSPI
The Tegra QSPI controllers use a single reset control, so reset-names is
not necessary and therefore not specified in the DT bindings. Drop the
property from device tree files to avoid validation warnings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| b2fbcbe1 | 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Use correct compatible string for Tegra234 HDA
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-
arm64: tegra: Use correct compatible string for Tegra234 HDA
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 7f0ea5ac | 04-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Use correct compatible string for Tegra194 HDA
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-
arm64: tegra: Use correct compatible string for Tegra194 HDA
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 85ab13c1 | 07-Dec-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
The PMC pinmux configuration nodes need to be part of a top-level pinmux
node. Add that new "pinmux" node and move the configuration nodes into
it
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
The PMC pinmux configuration nodes need to be part of a top-level pinmux
node. Add that new "pinmux" node and move the configuration nodes into
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 27f1568b | 07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: tegra: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache
arm64: tegra: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| 14910d68 | 19-Sep-2022 |
Fabio Estevam <festevam@denx.de> |
arm64: tegra: Remove 'enable-active-low'
The 'enable-active-low' property is not a valid one.
Only 'enable-active-high' is valid, and when this property is absent
the gpio regulator will act as act
arm64: tegra: Remove 'enable-active-low'
The 'enable-active-low' property is not a valid one.
Only 'enable-active-high' is valid, and when this property is absent
the gpio regulator will act as active low by default.
Remove the invalid 'enable-active-low' property.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|