xref: /openbmc/linux/arch/powerpc/boot/dts/turris1x.dts (revision 71de0a05) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Turris 1.x Device Tree Source
4 *
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
6 *
7 * Pinout, Schematics and Altium hardware design files are open source
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/leds/common.h>
14/include/ "fsl/p2020si-pre.dtsi"
15
16/ {
17	model = "Turris 1.x";
18	compatible = "cznic,turris1x", "fsl,P2020RDB-PC"; /* fsl,P2020RDB-PC is required for booting Linux */
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		ethernet2 = &enet2;
24		serial0 = &serial0;
25		serial1 = &serial1;
26		pci0 = &pci0;
27		pci1 = &pci1;
28		pci2 = &pci2;
29		spi0 = &spi0;
30	};
31
32	memory {
33		device_type = "memory";
34	};
35
36	soc: soc@ffe00000 {
37		ranges = <0x0 0x0 0xffe00000 0x00100000>;
38
39		i2c@3000 {
40			/* PCA9557PW GPIO controller for boot config */
41			gpio-controller@18 {
42				compatible = "nxp,pca9557";
43				label = "bootcfg";
44				reg = <0x18>;
45				#gpio-cells = <2>;
46				gpio-controller;
47				polarity = <0x00>;
48			};
49
50			/* STM32F030R8T6 MCU for power control */
51			power-control@2a {
52				/*
53				 * Turris Power Control firmware runs on STM32F0 MCU.
54				 * This firmware is open source and available at:
55				 * https://gitlab.nic.cz/turris/hw/turris_power_control
56				 */
57				reg = <0x2a>;
58			};
59
60			/* DDR3 SPD/EEPROM PSWP instruction */
61			eeprom@32 {
62				reg = <0x32>;
63			};
64
65			/* SA56004ED temperature control */
66			temperature-sensor@4c {
67				compatible = "nxp,sa56004";
68				reg = <0x4c>;
69				interrupt-parent = <&gpio>;
70				interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */
71					     <13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */
72				#address-cells = <1>;
73				#size-cells = <0>;
74
75				/* Local temperature sensor (SA56004ED internal) */
76				channel@0 {
77					reg = <0>;
78					label = "board";
79				};
80
81				/* Remote temperature sensor (D+/D- connected to P2020 CPU Temperature Diode) */
82				channel@1 {
83					reg = <1>;
84					label = "cpu";
85				};
86			};
87
88			/* DDR3 SPD/EEPROM */
89			eeprom@52 {
90				compatible = "atmel,spd";
91				reg = <0x52>;
92			};
93
94			/* MCP79402-I/ST Protected EEPROM */
95			eeprom@57 {
96				reg = <0x57>;
97			};
98
99			/* ATSHA204-TH-DA-T crypto module */
100			crypto@64 {
101				compatible = "atmel,atsha204";
102				reg = <0x64>;
103			};
104
105			/* IDT6V49205BNLGI clock generator */
106			clock-generator@69 {
107				compatible = "idt,6v49205b";
108				reg = <0x69>;
109			};
110
111			/* MCP79402-I/ST RTC */
112			rtc@6f {
113				compatible = "microchip,mcp7940x";
114				reg = <0x6f>;
115				interrupt-parent = <&gpio>;
116				interrupts = <14 0>; /* GPIO14 - MFP pin */
117			};
118		};
119
120		/* SPI on connector P1 */
121		spi0: spi@7000 {
122		};
123
124		gpio: gpio-controller@fc00 {
125			#interrupt-cells = <2>;
126			interrupt-controller;
127		};
128
129		/* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */
130		usb@22000 {
131			phy_type = "ulpi";
132			dr_mode = "host";
133		};
134
135		enet0: ethernet@24000 {
136			/* Connected to port 6 of QCA8337N-AL3C switch */
137			phy-connection-type = "rgmii-id";
138
139			fixed-link {
140				speed = <1000>;
141				full-duplex;
142			};
143		};
144
145		mdio@24520 {
146			/* KSZ9031RNXCA ethernet phy for WAN port */
147			phy: ethernet-phy@7 {
148				interrupts = <3 1 0 0>;
149				reg = <0x7>;
150			};
151
152			/* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */
153			switch@10 {
154				compatible = "qca,qca8337";
155				interrupts = <2 1 0 0>;
156				reg = <0x10>;
157
158				ports {
159					#address-cells = <1>;
160					#size-cells = <0>;
161
162					port@0 {
163						reg = <0>;
164						label = "cpu";
165						ethernet = <&enet1>;
166						phy-mode = "rgmii-id";
167
168						fixed-link {
169							speed = <1000>;
170							full-duplex;
171						};
172					};
173
174					port@1 {
175						reg = <1>;
176						label = "lan5";
177					};
178
179					port@2 {
180						reg = <2>;
181						label = "lan4";
182					};
183
184					port@3 {
185						reg = <3>;
186						label = "lan3";
187					};
188
189					port@4 {
190						reg = <4>;
191						label = "lan2";
192					};
193
194					port@5 {
195						reg = <5>;
196						label = "lan1";
197					};
198
199					port@6 {
200						reg = <6>;
201						label = "cpu";
202						ethernet = <&enet0>;
203						phy-mode = "rgmii-id";
204
205						fixed-link {
206							speed = <1000>;
207							full-duplex;
208						};
209					};
210				};
211			};
212		};
213
214		ptp_clock@24e00 {
215			fsl,tclk-period = <5>;
216			fsl,tmr-prsc = <200>;
217			fsl,tmr-add = <0xcccccccd>;
218			fsl,tmr-fiper1 = <0x3b9ac9fb>;
219			fsl,tmr-fiper2 = <0x0001869b>;
220			fsl,max-adj = <249999999>;
221		};
222
223		enet1: ethernet@25000 {
224			/* Connected to port 0 of QCA8337N-AL3C switch */
225			phy-connection-type = "rgmii-id";
226
227			fixed-link {
228				speed = <1000>;
229				full-duplex;
230			};
231		};
232
233		mdio@25520 {
234			status = "disabled";
235		};
236
237		enet2: ethernet@26000 {
238			/* Connected to KSZ9031RNXCA ethernet phy (WAN port) */
239			label = "wan";
240			phy-handle = <&phy>;
241			phy-connection-type = "rgmii-id";
242		};
243
244		mdio@26520 {
245			status = "disabled";
246		};
247
248		sdhc@2e000 {
249			bus-width = <4>;
250			cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
251		};
252	};
253
254	lbc: localbus@ffe05000 {
255		reg = <0 0xffe05000 0 0x1000>;
256
257		ranges = <0x0 0x0 0x0 0xef000000 0x01000000>, /* NOR */
258			 <0x1 0x0 0x0 0xff800000 0x00040000>, /* NAND */
259			 <0x3 0x0 0x0 0xffa00000 0x00020000>; /* CPLD */
260
261		/* S29GL128P90TFIR10 NOR */
262		nor@0,0 {
263			compatible = "cfi-flash";
264			reg = <0x0 0x0 0x01000000>;
265			bank-width = <2>;
266			device-width = <1>;
267
268			partitions {
269				compatible = "fixed-partitions";
270				#address-cells = <1>;
271				#size-cells = <1>;
272
273				partition@0 {
274					/* 128 kB for Device Tree Blob */
275					reg = <0x00000000 0x00020000>;
276					label = "dtb";
277				};
278
279				partition@20000 {
280					/* 1.7 MB for Linux Kernel Image */
281					reg = <0x00020000 0x001a0000>;
282					label = "kernel";
283				};
284
285				partition@1c0000 {
286					/* 1.5 MB for Rescue JFFS2 Root File System */
287					reg = <0x001c0000 0x00180000>;
288					label = "rescue";
289				};
290
291				partition@340000 {
292					/* 11 MB for TAR.XZ Archive with Factory content of NAND Root File System */
293					reg = <0x00340000 0x00b00000>;
294					label = "factory";
295				};
296
297				partition@e40000 {
298					/* 768 kB for Certificates JFFS2 File System */
299					reg = <0x00e40000 0x000c0000>;
300					label = "certificates";
301				};
302
303				/* free unused space 0x00f00000-0x00f20000 */
304
305				partition@f20000 {
306					/* 128 kB for U-Boot Environment Variables */
307					reg = <0x00f20000 0x00020000>;
308					label = "u-boot-env";
309				};
310
311				partition@f40000 {
312					/* 768 kB for U-Boot Bootloader Image */
313					reg = <0x00f40000 0x000c0000>;
314					label = "u-boot";
315				};
316			};
317		};
318
319		/* MT29F2G08ABAEAWP:E NAND */
320		nand@1,0 {
321			compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
322			reg = <0x1 0x0 0x00040000>;
323			nand-ecc-mode = "soft";
324			nand-ecc-algo = "bch";
325
326			partitions {
327				compatible = "fixed-partitions";
328				#address-cells = <1>;
329				#size-cells = <1>;
330
331				partition@0 {
332					/* 256 MB for UBI with one volume: UBIFS Root File System */
333					reg = <0x00000000 0x10000000>;
334					label = "rootfs";
335				};
336			};
337		};
338
339		/* LCMXO1200C-3FTN256C FPGA */
340		cpld@3,0 {
341			/*
342			 * Turris CPLD firmware which runs on this Lattice FPGA,
343			 * is extended version of P1021RDB-PC CPLD v4.1 firmware.
344			 * It is backward compatible with its original version
345			 * and the only extension is support for Turris LEDs.
346			 * Turris CPLD firmware is open source and available at:
347			 * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v
348			 */
349			compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
350			reg = <0x3 0x0 0x30>;
351			#address-cells = <1>;
352			#size-cells = <1>;
353			ranges = <0x0 0x3 0x0 0x00020000>;
354
355			/* MAX6370KA+T watchdog */
356			watchdog@2 {
357				/*
358				 * CPLD firmware maps SET0, SET1 and SET2
359				 * input logic of MAX6370KA+T chip to CPLD
360				 * memory space at byte offset 0x2. WDI
361				 * input logic is outside of the CPLD and
362				 * connected via external GPIO.
363				 */
364				compatible = "maxim,max6370";
365				reg = <0x02 0x01>;
366				gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
367			};
368
369			reboot@d {
370				/*
371				 * CPLD firmware which manages system reset and
372				 * watchdog registers has bugs. It does not
373				 * autoclear system reset register after change
374				 * and watchdog ignores reset line on immediate
375				 * succeeding reset cycle triggered by watchdog.
376				 * These bugs have to be workarounded in U-Boot
377				 * bootloader. So use system reset via syscon as
378				 * a last resort because older U-Boot versions
379				 * do not have workaround for watchdog.
380				 *
381				 * Reset method via rstcr's global-utilities
382				 * (the preferred one) has priority level 128,
383				 * watchdog has priority level 0 and default
384				 * syscon-reboot priority level is 192.
385				 *
386				 * So define syscon-reboot with custom priority
387				 * level 64 (between rstcr and watchdog) because
388				 * rstcr should stay as default preferred reset
389				 * method and reset via watchdog is more broken
390				 * than system reset via syscon.
391				 */
392				compatible = "syscon-reboot";
393				reg = <0x0d 0x01>;
394				offset = <0x0d>;
395				mask = <0x01>;
396				value = <0x01>;
397				priority = <64>;
398			};
399
400			led-controller@13 {
401				/*
402				 * LEDs are controlled by CPLD firmware.
403				 * All five LAN LEDs share common RGB settings
404				 * and so it is not possible to set different
405				 * colors on different LAN ports.
406				 */
407				compatible = "cznic,turris1x-leds";
408				reg = <0x13 0x1d>;
409				#address-cells = <1>;
410				#size-cells = <0>;
411
412				multi-led@0 {
413					reg = <0x0>;
414					color = <LED_COLOR_ID_RGB>;
415					function = LED_FUNCTION_WAN;
416				};
417
418				multi-led@1 {
419					reg = <0x1>;
420					color = <LED_COLOR_ID_RGB>;
421					function = LED_FUNCTION_LAN;
422					function-enumerator = <5>;
423				};
424
425				multi-led@2 {
426					reg = <0x2>;
427					color = <LED_COLOR_ID_RGB>;
428					function = LED_FUNCTION_LAN;
429					function-enumerator = <4>;
430				};
431
432				multi-led@3 {
433					reg = <0x3>;
434					color = <LED_COLOR_ID_RGB>;
435					function = LED_FUNCTION_LAN;
436					function-enumerator = <3>;
437				};
438
439				multi-led@4 {
440					reg = <0x4>;
441					color = <LED_COLOR_ID_RGB>;
442					function = LED_FUNCTION_LAN;
443					function-enumerator = <2>;
444				};
445
446				multi-led@5 {
447					reg = <0x5>;
448					color = <LED_COLOR_ID_RGB>;
449					function = LED_FUNCTION_LAN;
450					function-enumerator = <1>;
451				};
452
453				multi-led@6 {
454					reg = <0x6>;
455					color = <LED_COLOR_ID_RGB>;
456					function = LED_FUNCTION_WLAN;
457				};
458
459				multi-led@7 {
460					reg = <0x7>;
461					color = <LED_COLOR_ID_RGB>;
462					function = LED_FUNCTION_POWER;
463				};
464			};
465		};
466	};
467
468	pci2: pcie@ffe08000 {
469		/*
470		 * PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller.
471		 * This xHCI controller is available only on Turris 1.1 boards.
472		 * Turris 1.0 boards have nothing connected to this PCIe bus,
473		 * so system would see only PCIe Root Port of this PCIe Root
474		 * Complex. TUSB7340RKM xHCI controller has four SuperSpeed
475		 * channels. Channel 0 is connected to the front USB 3.0 port,
476		 * channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
477		 * slot 1 (CN5), channels 2 and 3 to connector P600.
478		 *
479		 * P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller
480		 * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
481		 * So allocate 2MB of PCIe MEM for this PCIe bus.
482		 */
483		reg = <0 0xffe08000 0 0x1000>;
484		ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */
485			 <0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
486
487		pcie@0 {
488			ranges;
489		};
490	};
491
492	pci1: pcie@ffe09000 {
493		/* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
494		reg = <0 0xffe09000 0 0x1000>;
495		ranges = <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000>, /* MEM */
496			 <0x01000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; /* IO */
497
498		pcie@0 {
499			ranges;
500		};
501	};
502
503	pci0: pcie@ffe0a000 {
504		/*
505		 * PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card.
506		 * Turris 1.1 boards have in this mPCIe slot additional USB 2.0
507		 * pins via channel 1 of TUSB7340RKM xHCI controller and also
508		 * additional SIM card slot, both for USB-based WWAN cards.
509		 */
510		reg = <0 0xffe0a000 0 0x1000>;
511		ranges = <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000>, /* MEM */
512			 <0x01000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; /* IO */
513
514		pcie@0 {
515			ranges;
516		};
517	};
518};
519
520/include/ "fsl/p2020si-post.dtsi"
521