1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Shunli Wang <shunli.wang@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12 
13 #include <dt-bindings/clock/mt2701-clk.h>
14 
15 static const struct mtk_gate_regs hif_cg_regs = {
16 	.sta_ofs = 0x0030,
17 };
18 
19 #define GATE_HIF(_id, _name, _parent, _shift) {		\
20 		.id = _id,				\
21 		.name = _name,				\
22 		.parent_name = _parent,			\
23 		.regs = &hif_cg_regs,			\
24 		.shift = _shift,			\
25 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
26 	}
27 
28 static const struct mtk_gate hif_clks[] = {
29 	GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
30 	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
31 	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
32 	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
33 	GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
34 	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
35 };
36 
37 static u16 rst_ofs[] = { 0x34, };
38 
39 static const struct mtk_clk_rst_desc clk_rst_desc = {
40 	.version = MTK_RST_SIMPLE,
41 	.rst_bank_ofs = rst_ofs,
42 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
43 };
44 
45 static const struct mtk_clk_desc hif_desc = {
46 	.clks = hif_clks,
47 	.num_clks = ARRAY_SIZE(hif_clks),
48 	.rst_desc = &clk_rst_desc,
49 };
50 
51 static const struct of_device_id of_match_clk_mt2701_hif[] = {
52 	{ .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
53 	{ /* sentinel */ }
54 };
55 
56 static struct platform_driver clk_mt2701_hif_drv = {
57 	.probe = mtk_clk_simple_probe,
58 	.remove = mtk_clk_simple_remove,
59 	.driver = {
60 		.name = "clk-mt2701-hif",
61 		.of_match_table = of_match_clk_mt2701_hif,
62 	},
63 };
64 
65 builtin_platform_driver(clk_mt2701_hif_drv);
66