1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra234-misc"; 27 reg = <0x0 0x00100000 0x0 0xf000>, 28 <0x0 0x0010f000 0x0 0x1000>; 29 status = "okay"; 30 }; 31 32 timer@2080000 { 33 compatible = "nvidia,tegra234-timer"; 34 reg = <0x0 0x02080000 0x0 0x00121000>; 35 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51 status = "okay"; 52 }; 53 54 gpio: gpio@2200000 { 55 compatible = "nvidia,tegra234-gpio"; 56 reg-names = "security", "gpio"; 57 reg = <0x0 0x02200000 0x0 0x10000>, 58 <0x0 0x02210000 0x0 0x10000>; 59 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 #gpio-cells = <2>; 110 gpio-controller; 111 }; 112 113 gpcdma: dma-controller@2600000 { 114 compatible = "nvidia,tegra234-gpcdma", 115 "nvidia,tegra186-gpcdma"; 116 reg = <0x0 0x2600000 0x0 0x210000>; 117 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 118 reset-names = "gpcdma"; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153 dma-channel-mask = <0xfffffffe>; 154 dma-coherent; 155 }; 156 157 aconnect@2900000 { 158 compatible = "nvidia,tegra234-aconnect", 159 "nvidia,tegra210-aconnect"; 160 clocks = <&bpmp TEGRA234_CLK_APE>, 161 <&bpmp TEGRA234_CLK_APB2APE>; 162 clock-names = "ape", "apb2ape"; 163 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164 status = "disabled"; 165 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 169 170 tegra_ahub: ahub@2900800 { 171 compatible = "nvidia,tegra234-ahub"; 172 reg = <0x0 0x02900800 0x0 0x800>; 173 clocks = <&bpmp TEGRA234_CLK_AHUB>; 174 clock-names = "ahub"; 175 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177 status = "disabled"; 178 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 182 183 tegra_i2s1: i2s@2901000 { 184 compatible = "nvidia,tegra234-i2s", 185 "nvidia,tegra210-i2s"; 186 reg = <0x0 0x2901000 0x0 0x100>; 187 clocks = <&bpmp TEGRA234_CLK_I2S1>, 188 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189 clock-names = "i2s", "sync_input"; 190 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192 assigned-clock-rates = <1536000>; 193 sound-name-prefix = "I2S1"; 194 status = "disabled"; 195 }; 196 197 tegra_i2s2: i2s@2901100 { 198 compatible = "nvidia,tegra234-i2s", 199 "nvidia,tegra210-i2s"; 200 reg = <0x0 0x2901100 0x0 0x100>; 201 clocks = <&bpmp TEGRA234_CLK_I2S2>, 202 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203 clock-names = "i2s", "sync_input"; 204 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206 assigned-clock-rates = <1536000>; 207 sound-name-prefix = "I2S2"; 208 status = "disabled"; 209 }; 210 211 tegra_i2s3: i2s@2901200 { 212 compatible = "nvidia,tegra234-i2s", 213 "nvidia,tegra210-i2s"; 214 reg = <0x0 0x2901200 0x0 0x100>; 215 clocks = <&bpmp TEGRA234_CLK_I2S3>, 216 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217 clock-names = "i2s", "sync_input"; 218 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220 assigned-clock-rates = <1536000>; 221 sound-name-prefix = "I2S3"; 222 status = "disabled"; 223 }; 224 225 tegra_i2s4: i2s@2901300 { 226 compatible = "nvidia,tegra234-i2s", 227 "nvidia,tegra210-i2s"; 228 reg = <0x0 0x2901300 0x0 0x100>; 229 clocks = <&bpmp TEGRA234_CLK_I2S4>, 230 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231 clock-names = "i2s", "sync_input"; 232 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234 assigned-clock-rates = <1536000>; 235 sound-name-prefix = "I2S4"; 236 status = "disabled"; 237 }; 238 239 tegra_i2s5: i2s@2901400 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901400 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S5>, 244 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S5"; 250 status = "disabled"; 251 }; 252 253 tegra_i2s6: i2s@2901500 { 254 compatible = "nvidia,tegra234-i2s", 255 "nvidia,tegra210-i2s"; 256 reg = <0x0 0x2901500 0x0 0x100>; 257 clocks = <&bpmp TEGRA234_CLK_I2S6>, 258 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S6"; 264 status = "disabled"; 265 }; 266 267 tegra_sfc1: sfc@2902000 { 268 compatible = "nvidia,tegra234-sfc", 269 "nvidia,tegra210-sfc"; 270 reg = <0x0 0x2902000 0x0 0x200>; 271 sound-name-prefix = "SFC1"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc2: sfc@2902200 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902200 0x0 0x200>; 279 sound-name-prefix = "SFC2"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc3: sfc@2902400 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902400 0x0 0x200>; 287 sound-name-prefix = "SFC3"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc4: sfc@2902600 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902600 0x0 0x200>; 295 sound-name-prefix = "SFC4"; 296 status = "disabled"; 297 }; 298 299 tegra_amx1: amx@2903000 { 300 compatible = "nvidia,tegra234-amx", 301 "nvidia,tegra194-amx"; 302 reg = <0x0 0x2903000 0x0 0x100>; 303 sound-name-prefix = "AMX1"; 304 status = "disabled"; 305 }; 306 307 tegra_amx2: amx@2903100 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903100 0x0 0x100>; 311 sound-name-prefix = "AMX2"; 312 status = "disabled"; 313 }; 314 315 tegra_amx3: amx@2903200 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903200 0x0 0x100>; 319 sound-name-prefix = "AMX3"; 320 status = "disabled"; 321 }; 322 323 tegra_amx4: amx@2903300 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903300 0x0 0x100>; 327 sound-name-prefix = "AMX4"; 328 status = "disabled"; 329 }; 330 331 tegra_adx1: adx@2903800 { 332 compatible = "nvidia,tegra234-adx", 333 "nvidia,tegra210-adx"; 334 reg = <0x0 0x2903800 0x0 0x100>; 335 sound-name-prefix = "ADX1"; 336 status = "disabled"; 337 }; 338 339 tegra_adx2: adx@2903900 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903900 0x0 0x100>; 343 sound-name-prefix = "ADX2"; 344 status = "disabled"; 345 }; 346 347 tegra_adx3: adx@2903a00 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903a00 0x0 0x100>; 351 sound-name-prefix = "ADX3"; 352 status = "disabled"; 353 }; 354 355 tegra_adx4: adx@2903b00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903b00 0x0 0x100>; 359 sound-name-prefix = "ADX4"; 360 status = "disabled"; 361 }; 362 363 364 tegra_dmic1: dmic@2904000 { 365 compatible = "nvidia,tegra234-dmic", 366 "nvidia,tegra210-dmic"; 367 reg = <0x0 0x2904000 0x0 0x100>; 368 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369 clock-names = "dmic"; 370 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372 assigned-clock-rates = <3072000>; 373 sound-name-prefix = "DMIC1"; 374 status = "disabled"; 375 }; 376 377 tegra_dmic2: dmic@2904100 { 378 compatible = "nvidia,tegra234-dmic", 379 "nvidia,tegra210-dmic"; 380 reg = <0x0 0x2904100 0x0 0x100>; 381 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382 clock-names = "dmic"; 383 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385 assigned-clock-rates = <3072000>; 386 sound-name-prefix = "DMIC2"; 387 status = "disabled"; 388 }; 389 390 tegra_dmic3: dmic@2904200 { 391 compatible = "nvidia,tegra234-dmic", 392 "nvidia,tegra210-dmic"; 393 reg = <0x0 0x2904200 0x0 0x100>; 394 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395 clock-names = "dmic"; 396 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <3072000>; 399 sound-name-prefix = "DMIC3"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic4: dmic@2904300 { 404 compatible = "nvidia,tegra234-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x0 0x2904300 0x0 0x100>; 407 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC4"; 413 status = "disabled"; 414 }; 415 416 tegra_dspk1: dspk@2905000 { 417 compatible = "nvidia,tegra234-dspk", 418 "nvidia,tegra186-dspk"; 419 reg = <0x0 0x2905000 0x0 0x100>; 420 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421 clock-names = "dspk"; 422 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <12288000>; 425 sound-name-prefix = "DSPK1"; 426 status = "disabled"; 427 }; 428 429 tegra_dspk2: dspk@2905100 { 430 compatible = "nvidia,tegra234-dspk", 431 "nvidia,tegra186-dspk"; 432 reg = <0x0 0x2905100 0x0 0x100>; 433 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434 clock-names = "dspk"; 435 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <12288000>; 438 sound-name-prefix = "DSPK2"; 439 status = "disabled"; 440 }; 441 442 tegra_ope1: processing-engine@2908000 { 443 compatible = "nvidia,tegra234-ope", 444 "nvidia,tegra210-ope"; 445 reg = <0x0 0x2908000 0x0 0x100>; 446 sound-name-prefix = "OPE1"; 447 status = "disabled"; 448 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 equalizer@2908100 { 454 compatible = "nvidia,tegra234-peq", 455 "nvidia,tegra210-peq"; 456 reg = <0x0 0x2908100 0x0 0x100>; 457 }; 458 459 dynamic-range-compressor@2908200 { 460 compatible = "nvidia,tegra234-mbdrc", 461 "nvidia,tegra210-mbdrc"; 462 reg = <0x0 0x2908200 0x0 0x200>; 463 }; 464 }; 465 466 tegra_mvc1: mvc@290a000 { 467 compatible = "nvidia,tegra234-mvc", 468 "nvidia,tegra210-mvc"; 469 reg = <0x0 0x290a000 0x0 0x200>; 470 sound-name-prefix = "MVC1"; 471 status = "disabled"; 472 }; 473 474 tegra_mvc2: mvc@290a200 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a200 0x0 0x200>; 478 sound-name-prefix = "MVC2"; 479 status = "disabled"; 480 }; 481 482 tegra_amixer: amixer@290bb00 { 483 compatible = "nvidia,tegra234-amixer", 484 "nvidia,tegra210-amixer"; 485 reg = <0x0 0x290bb00 0x0 0x800>; 486 sound-name-prefix = "MIXER1"; 487 status = "disabled"; 488 }; 489 490 tegra_admaif: admaif@290f000 { 491 compatible = "nvidia,tegra234-admaif", 492 "nvidia,tegra186-admaif"; 493 reg = <0x0 0x0290f000 0x0 0x1000>; 494 dmas = <&adma 1>, <&adma 1>, 495 <&adma 2>, <&adma 2>, 496 <&adma 3>, <&adma 3>, 497 <&adma 4>, <&adma 4>, 498 <&adma 5>, <&adma 5>, 499 <&adma 6>, <&adma 6>, 500 <&adma 7>, <&adma 7>, 501 <&adma 8>, <&adma 8>, 502 <&adma 9>, <&adma 9>, 503 <&adma 10>, <&adma 10>, 504 <&adma 11>, <&adma 11>, 505 <&adma 12>, <&adma 12>, 506 <&adma 13>, <&adma 13>, 507 <&adma 14>, <&adma 14>, 508 <&adma 15>, <&adma 15>, 509 <&adma 16>, <&adma 16>, 510 <&adma 17>, <&adma 17>, 511 <&adma 18>, <&adma 18>, 512 <&adma 19>, <&adma 19>, 513 <&adma 20>, <&adma 20>; 514 dma-names = "rx1", "tx1", 515 "rx2", "tx2", 516 "rx3", "tx3", 517 "rx4", "tx4", 518 "rx5", "tx5", 519 "rx6", "tx6", 520 "rx7", "tx7", 521 "rx8", "tx8", 522 "rx9", "tx9", 523 "rx10", "tx10", 524 "rx11", "tx11", 525 "rx12", "tx12", 526 "rx13", "tx13", 527 "rx14", "tx14", 528 "rx15", "tx15", 529 "rx16", "tx16", 530 "rx17", "tx17", 531 "rx18", "tx18", 532 "rx19", "tx19", 533 "rx20", "tx20"; 534 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536 interconnect-names = "dma-mem", "write"; 537 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538 status = "disabled"; 539 }; 540 541 tegra_asrc: asrc@2910000 { 542 compatible = "nvidia,tegra234-asrc", 543 "nvidia,tegra186-asrc"; 544 reg = <0x0 0x2910000 0x0 0x2000>; 545 sound-name-prefix = "ASRC1"; 546 status = "disabled"; 547 }; 548 }; 549 550 adma: dma-controller@2930000 { 551 compatible = "nvidia,tegra234-adma", 552 "nvidia,tegra186-adma"; 553 reg = <0x0 0x02930000 0x0 0x20000>; 554 interrupt-parent = <&agic>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587 #dma-cells = <1>; 588 clocks = <&bpmp TEGRA234_CLK_AHUB>; 589 clock-names = "d_audio"; 590 status = "disabled"; 591 }; 592 593 agic: interrupt-controller@2a40000 { 594 compatible = "nvidia,tegra234-agic", 595 "nvidia,tegra210-agic"; 596 #interrupt-cells = <3>; 597 interrupt-controller; 598 reg = <0x0 0x02a41000 0x0 0x1000>, 599 <0x0 0x02a42000 0x0 0x2000>; 600 interrupts = <GIC_SPI 145 601 (GIC_CPU_MASK_SIMPLE(4) | 602 IRQ_TYPE_LEVEL_HIGH)>; 603 clocks = <&bpmp TEGRA234_CLK_APE>; 604 clock-names = "clk"; 605 status = "disabled"; 606 }; 607 }; 608 609 mc: memory-controller@2c00000 { 610 compatible = "nvidia,tegra234-mc"; 611 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 612 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 613 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 614 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 615 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 616 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 617 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 618 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 619 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 620 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 621 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 622 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 623 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 624 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 625 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 626 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 627 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 628 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631 "ch11", "ch12", "ch13", "ch14", "ch15"; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 #interconnect-cells = <1>; 634 status = "okay"; 635 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 639 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 640 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641 642 /* 643 * Bit 39 of addresses passing through the memory 644 * controller selects the XBAR format used when memory 645 * is accessed. This is used to transparently access 646 * memory in the XBAR format used by the discrete GPU 647 * (bit 39 set) or Tegra (bit 39 clear). 648 * 649 * As a consequence, the operating system must ensure 650 * that bit 39 is never used implicitly, for example 651 * via an I/O virtual address mapping of an IOMMU. If 652 * devices require access to the XBAR switch, their 653 * drivers must set this bit explicitly. 654 * 655 * Limit the DMA range for memory clients to [38:0]. 656 */ 657 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658 659 emc: external-memory-controller@2c60000 { 660 compatible = "nvidia,tegra234-emc"; 661 reg = <0x0 0x02c60000 0x0 0x90000>, 662 <0x0 0x01780000 0x0 0x80000>; 663 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA234_CLK_EMC>; 665 clock-names = "emc"; 666 status = "okay"; 667 668 #interconnect-cells = <0>; 669 670 nvidia,bpmp = <&bpmp>; 671 }; 672 }; 673 674 uarta: serial@3100000 { 675 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 676 reg = <0x0 0x03100000 0x0 0x10000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&bpmp TEGRA234_CLK_UARTA>; 679 clock-names = "serial"; 680 resets = <&bpmp TEGRA234_RESET_UARTA>; 681 reset-names = "serial"; 682 status = "disabled"; 683 }; 684 685 gen1_i2c: i2c@3160000 { 686 compatible = "nvidia,tegra194-i2c"; 687 reg = <0x0 0x3160000 0x0 0x100>; 688 status = "disabled"; 689 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 clock-frequency = <400000>; 693 clocks = <&bpmp TEGRA234_CLK_I2C1 694 &bpmp TEGRA234_CLK_PLLP_OUT0>; 695 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 696 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 697 clock-names = "div-clk", "parent"; 698 resets = <&bpmp TEGRA234_RESET_I2C1>; 699 reset-names = "i2c"; 700 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 701 dma-coherent; 702 dmas = <&gpcdma 21>, <&gpcdma 21>; 703 dma-names = "rx", "tx"; 704 }; 705 706 cam_i2c: i2c@3180000 { 707 compatible = "nvidia,tegra194-i2c"; 708 reg = <0x0 0x3180000 0x0 0x100>; 709 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 clock-frequency = <400000>; 714 clocks = <&bpmp TEGRA234_CLK_I2C3 715 &bpmp TEGRA234_CLK_PLLP_OUT0>; 716 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 717 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 718 clock-names = "div-clk", "parent"; 719 resets = <&bpmp TEGRA234_RESET_I2C3>; 720 reset-names = "i2c"; 721 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 722 dma-coherent; 723 dmas = <&gpcdma 23>, <&gpcdma 23>; 724 dma-names = "rx", "tx"; 725 }; 726 727 dp_aux_ch1_i2c: i2c@3190000 { 728 compatible = "nvidia,tegra194-i2c"; 729 reg = <0x0 0x3190000 0x0 0x100>; 730 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 clock-frequency = <100000>; 735 clocks = <&bpmp TEGRA234_CLK_I2C4 736 &bpmp TEGRA234_CLK_PLLP_OUT0>; 737 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 738 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 739 clock-names = "div-clk", "parent"; 740 resets = <&bpmp TEGRA234_RESET_I2C4>; 741 reset-names = "i2c"; 742 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 743 dma-coherent; 744 dmas = <&gpcdma 26>, <&gpcdma 26>; 745 dma-names = "rx", "tx"; 746 }; 747 748 dp_aux_ch0_i2c: i2c@31b0000 { 749 compatible = "nvidia,tegra194-i2c"; 750 reg = <0x0 0x31b0000 0x0 0x100>; 751 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 clock-frequency = <100000>; 756 clocks = <&bpmp TEGRA234_CLK_I2C6 757 &bpmp TEGRA234_CLK_PLLP_OUT0>; 758 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 759 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 760 clock-names = "div-clk", "parent"; 761 resets = <&bpmp TEGRA234_RESET_I2C6>; 762 reset-names = "i2c"; 763 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 764 dma-coherent; 765 dmas = <&gpcdma 30>, <&gpcdma 30>; 766 dma-names = "rx", "tx"; 767 }; 768 769 dp_aux_ch2_i2c: i2c@31c0000 { 770 compatible = "nvidia,tegra194-i2c"; 771 reg = <0x0 0x31c0000 0x0 0x100>; 772 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 clock-frequency = <100000>; 777 clocks = <&bpmp TEGRA234_CLK_I2C7 778 &bpmp TEGRA234_CLK_PLLP_OUT0>; 779 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 780 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 781 clock-names = "div-clk", "parent"; 782 resets = <&bpmp TEGRA234_RESET_I2C7>; 783 reset-names = "i2c"; 784 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 785 dma-coherent; 786 dmas = <&gpcdma 27>, <&gpcdma 27>; 787 dma-names = "rx", "tx"; 788 }; 789 790 uarti: serial@31d0000 { 791 compatible = "arm,sbsa-uart"; 792 reg = <0x0 0x31d0000 0x0 0x10000>; 793 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 794 status = "disabled"; 795 }; 796 797 dp_aux_ch3_i2c: i2c@31e0000 { 798 compatible = "nvidia,tegra194-i2c"; 799 reg = <0x0 0x31e0000 0x0 0x100>; 800 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 clock-frequency = <100000>; 805 clocks = <&bpmp TEGRA234_CLK_I2C9 806 &bpmp TEGRA234_CLK_PLLP_OUT0>; 807 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 808 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 809 clock-names = "div-clk", "parent"; 810 resets = <&bpmp TEGRA234_RESET_I2C9>; 811 reset-names = "i2c"; 812 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 813 dma-coherent; 814 dmas = <&gpcdma 31>, <&gpcdma 31>; 815 dma-names = "rx", "tx"; 816 }; 817 818 spi@3270000 { 819 compatible = "nvidia,tegra234-qspi"; 820 reg = <0x0 0x3270000 0x0 0x1000>; 821 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 825 <&bpmp TEGRA234_CLK_QSPI0_PM>; 826 clock-names = "qspi", "qspi_out"; 827 resets = <&bpmp TEGRA234_RESET_QSPI0>; 828 status = "disabled"; 829 }; 830 831 pwm1: pwm@3280000 { 832 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 833 reg = <0x0 0x3280000 0x0 0x10000>; 834 clocks = <&bpmp TEGRA234_CLK_PWM1>; 835 resets = <&bpmp TEGRA234_RESET_PWM1>; 836 reset-names = "pwm"; 837 status = "disabled"; 838 #pwm-cells = <2>; 839 }; 840 841 pwm2: pwm@3290000 { 842 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 843 reg = <0x0 0x3290000 0x0 0x10000>; 844 clocks = <&bpmp TEGRA234_CLK_PWM2>; 845 resets = <&bpmp TEGRA234_RESET_PWM2>; 846 reset-names = "pwm"; 847 status = "disabled"; 848 #pwm-cells = <2>; 849 }; 850 851 pwm3: pwm@32a0000 { 852 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 853 reg = <0x0 0x32a0000 0x0 0x10000>; 854 clocks = <&bpmp TEGRA234_CLK_PWM3>; 855 resets = <&bpmp TEGRA234_RESET_PWM3>; 856 reset-names = "pwm"; 857 status = "disabled"; 858 #pwm-cells = <2>; 859 }; 860 861 pwm5: pwm@32c0000 { 862 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 863 reg = <0x0 0x32c0000 0x0 0x10000>; 864 clocks = <&bpmp TEGRA234_CLK_PWM5>; 865 resets = <&bpmp TEGRA234_RESET_PWM5>; 866 reset-names = "pwm"; 867 status = "disabled"; 868 #pwm-cells = <2>; 869 }; 870 871 pwm6: pwm@32d0000 { 872 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 873 reg = <0x0 0x32d0000 0x0 0x10000>; 874 clocks = <&bpmp TEGRA234_CLK_PWM6>; 875 resets = <&bpmp TEGRA234_RESET_PWM6>; 876 reset-names = "pwm"; 877 status = "disabled"; 878 #pwm-cells = <2>; 879 }; 880 881 pwm7: pwm@32e0000 { 882 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 883 reg = <0x0 0x32e0000 0x0 0x10000>; 884 clocks = <&bpmp TEGRA234_CLK_PWM7>; 885 resets = <&bpmp TEGRA234_RESET_PWM7>; 886 reset-names = "pwm"; 887 status = "disabled"; 888 #pwm-cells = <2>; 889 }; 890 891 pwm8: pwm@32f0000 { 892 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 893 reg = <0x0 0x32f0000 0x0 0x10000>; 894 clocks = <&bpmp TEGRA234_CLK_PWM8>; 895 resets = <&bpmp TEGRA234_RESET_PWM8>; 896 reset-names = "pwm"; 897 status = "disabled"; 898 #pwm-cells = <2>; 899 }; 900 901 spi@3300000 { 902 compatible = "nvidia,tegra234-qspi"; 903 reg = <0x0 0x3300000 0x0 0x1000>; 904 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 908 <&bpmp TEGRA234_CLK_QSPI1_PM>; 909 clock-names = "qspi", "qspi_out"; 910 resets = <&bpmp TEGRA234_RESET_QSPI1>; 911 status = "disabled"; 912 }; 913 914 mmc@3400000 { 915 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 916 reg = <0x0 0x03400000 0x0 0x20000>; 917 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 919 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 920 clock-names = "sdhci", "tmclk"; 921 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 922 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 923 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 924 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 925 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 926 reset-names = "sdhci"; 927 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 928 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 929 interconnect-names = "dma-mem", "write"; 930 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 931 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 932 pinctrl-0 = <&sdmmc1_3v3>; 933 pinctrl-1 = <&sdmmc1_1v8>; 934 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 935 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 936 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 937 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 938 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 939 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 940 nvidia,default-tap = <14>; 941 nvidia,default-trim = <0x8>; 942 sd-uhs-sdr25; 943 sd-uhs-sdr50; 944 sd-uhs-ddr50; 945 sd-uhs-sdr104; 946 status = "disabled"; 947 }; 948 949 mmc@3460000 { 950 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 951 reg = <0x0 0x03460000 0x0 0x20000>; 952 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 954 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 955 clock-names = "sdhci", "tmclk"; 956 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 957 <&bpmp TEGRA234_CLK_PLLC4>; 958 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 959 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 960 reset-names = "sdhci"; 961 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 962 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 963 interconnect-names = "dma-mem", "write"; 964 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 965 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 966 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 967 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 968 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 969 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 970 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 971 nvidia,default-tap = <0x8>; 972 nvidia,default-trim = <0x14>; 973 nvidia,dqs-trim = <40>; 974 supports-cqe; 975 status = "disabled"; 976 }; 977 978 hda@3510000 { 979 compatible = "nvidia,tegra234-hda"; 980 reg = <0x0 0x3510000 0x0 0x10000>; 981 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 983 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 984 clock-names = "hda", "hda2codec_2x"; 985 resets = <&bpmp TEGRA234_RESET_HDA>, 986 <&bpmp TEGRA234_RESET_HDACODEC>; 987 reset-names = "hda", "hda2codec_2x"; 988 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 989 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 990 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 991 interconnect-names = "dma-mem", "write"; 992 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 993 status = "disabled"; 994 }; 995 996 xusb_padctl: padctl@3520000 { 997 compatible = "nvidia,tegra234-xusb-padctl"; 998 reg = <0x0 0x03520000 0x0 0x20000>, 999 <0x0 0x03540000 0x0 0x10000>; 1000 reg-names = "padctl", "ao"; 1001 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1002 1003 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 1004 reset-names = "padctl"; 1005 1006 status = "disabled"; 1007 1008 pads { 1009 usb2 { 1010 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 1011 clock-names = "trk"; 1012 1013 lanes { 1014 usb2-0 { 1015 nvidia,function = "xusb"; 1016 status = "disabled"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 usb2-1 { 1021 nvidia,function = "xusb"; 1022 status = "disabled"; 1023 #phy-cells = <0>; 1024 }; 1025 1026 usb2-2 { 1027 nvidia,function = "xusb"; 1028 status = "disabled"; 1029 #phy-cells = <0>; 1030 }; 1031 1032 usb2-3 { 1033 nvidia,function = "xusb"; 1034 status = "disabled"; 1035 #phy-cells = <0>; 1036 }; 1037 }; 1038 }; 1039 1040 usb3 { 1041 lanes { 1042 usb3-0 { 1043 nvidia,function = "xusb"; 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 1048 usb3-1 { 1049 nvidia,function = "xusb"; 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 1054 usb3-2 { 1055 nvidia,function = "xusb"; 1056 status = "disabled"; 1057 #phy-cells = <0>; 1058 }; 1059 1060 usb3-3 { 1061 nvidia,function = "xusb"; 1062 status = "disabled"; 1063 #phy-cells = <0>; 1064 }; 1065 }; 1066 }; 1067 }; 1068 1069 ports { 1070 usb2-0 { 1071 status = "disabled"; 1072 }; 1073 1074 usb2-1 { 1075 status = "disabled"; 1076 }; 1077 1078 usb2-2 { 1079 status = "disabled"; 1080 }; 1081 1082 usb2-3 { 1083 status = "disabled"; 1084 }; 1085 1086 usb3-0 { 1087 status = "disabled"; 1088 }; 1089 1090 usb3-1 { 1091 status = "disabled"; 1092 }; 1093 1094 usb3-2 { 1095 status = "disabled"; 1096 }; 1097 1098 usb3-3 { 1099 status = "disabled"; 1100 }; 1101 }; 1102 }; 1103 1104 usb@3550000 { 1105 compatible = "nvidia,tegra234-xudc"; 1106 reg = <0x0 0x03550000 0x0 0x8000>, 1107 <0x0 0x03558000 0x0 0x8000>; 1108 reg-names = "base", "fpci"; 1109 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1111 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1112 <&bpmp TEGRA234_CLK_XUSB_SS>, 1113 <&bpmp TEGRA234_CLK_XUSB_FS>; 1114 clock-names = "dev", "ss", "ss_src", "fs_src"; 1115 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1116 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1117 interconnect-names = "dma-mem", "write"; 1118 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1119 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1120 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1121 power-domain-names = "dev", "ss"; 1122 nvidia,xusb-padctl = <&xusb_padctl>; 1123 dma-coherent; 1124 status = "disabled"; 1125 }; 1126 1127 usb@3610000 { 1128 compatible = "nvidia,tegra234-xusb"; 1129 reg = <0x0 0x03610000 0x0 0x40000>, 1130 <0x0 0x03600000 0x0 0x10000>, 1131 <0x0 0x03650000 0x0 0x10000>; 1132 reg-names = "hcd", "fpci", "bar2"; 1133 1134 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1136 1137 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1138 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1139 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1140 <&bpmp TEGRA234_CLK_XUSB_SS>, 1141 <&bpmp TEGRA234_CLK_CLK_M>, 1142 <&bpmp TEGRA234_CLK_XUSB_FS>, 1143 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1144 <&bpmp TEGRA234_CLK_CLK_M>, 1145 <&bpmp TEGRA234_CLK_PLLE>; 1146 clock-names = "xusb_host", "xusb_falcon_src", 1147 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1148 "xusb_fs_src", "pll_u_480m", "clk_m", 1149 "pll_e"; 1150 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1151 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1152 interconnect-names = "dma-mem", "write"; 1153 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1154 1155 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1156 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1157 power-domain-names = "xusb_host", "xusb_ss"; 1158 1159 nvidia,xusb-padctl = <&xusb_padctl>; 1160 dma-coherent; 1161 status = "disabled"; 1162 }; 1163 1164 fuse@3810000 { 1165 compatible = "nvidia,tegra234-efuse"; 1166 reg = <0x0 0x03810000 0x0 0x10000>; 1167 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1168 clock-names = "fuse"; 1169 }; 1170 1171 hsp_top0: hsp@3c00000 { 1172 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1173 reg = <0x0 0x03c00000 0x0 0xa0000>; 1174 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1183 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1184 "shared3", "shared4", "shared5", "shared6", 1185 "shared7"; 1186 #mbox-cells = <2>; 1187 }; 1188 1189 p2u_hsio_0: phy@3e00000 { 1190 compatible = "nvidia,tegra234-p2u"; 1191 reg = <0x0 0x03e00000 0x0 0x10000>; 1192 reg-names = "ctl"; 1193 1194 #phy-cells = <0>; 1195 }; 1196 1197 p2u_hsio_1: phy@3e10000 { 1198 compatible = "nvidia,tegra234-p2u"; 1199 reg = <0x0 0x03e10000 0x0 0x10000>; 1200 reg-names = "ctl"; 1201 1202 #phy-cells = <0>; 1203 }; 1204 1205 p2u_hsio_2: phy@3e20000 { 1206 compatible = "nvidia,tegra234-p2u"; 1207 reg = <0x0 0x03e20000 0x0 0x10000>; 1208 reg-names = "ctl"; 1209 1210 #phy-cells = <0>; 1211 }; 1212 1213 p2u_hsio_3: phy@3e30000 { 1214 compatible = "nvidia,tegra234-p2u"; 1215 reg = <0x0 0x03e30000 0x0 0x10000>; 1216 reg-names = "ctl"; 1217 1218 #phy-cells = <0>; 1219 }; 1220 1221 p2u_hsio_4: phy@3e40000 { 1222 compatible = "nvidia,tegra234-p2u"; 1223 reg = <0x0 0x03e40000 0x0 0x10000>; 1224 reg-names = "ctl"; 1225 1226 #phy-cells = <0>; 1227 }; 1228 1229 p2u_hsio_5: phy@3e50000 { 1230 compatible = "nvidia,tegra234-p2u"; 1231 reg = <0x0 0x03e50000 0x0 0x10000>; 1232 reg-names = "ctl"; 1233 1234 #phy-cells = <0>; 1235 }; 1236 1237 p2u_hsio_6: phy@3e60000 { 1238 compatible = "nvidia,tegra234-p2u"; 1239 reg = <0x0 0x03e60000 0x0 0x10000>; 1240 reg-names = "ctl"; 1241 1242 #phy-cells = <0>; 1243 }; 1244 1245 p2u_hsio_7: phy@3e70000 { 1246 compatible = "nvidia,tegra234-p2u"; 1247 reg = <0x0 0x03e70000 0x0 0x10000>; 1248 reg-names = "ctl"; 1249 1250 #phy-cells = <0>; 1251 }; 1252 1253 p2u_nvhs_0: phy@3e90000 { 1254 compatible = "nvidia,tegra234-p2u"; 1255 reg = <0x0 0x03e90000 0x0 0x10000>; 1256 reg-names = "ctl"; 1257 1258 #phy-cells = <0>; 1259 }; 1260 1261 p2u_nvhs_1: phy@3ea0000 { 1262 compatible = "nvidia,tegra234-p2u"; 1263 reg = <0x0 0x03ea0000 0x0 0x10000>; 1264 reg-names = "ctl"; 1265 1266 #phy-cells = <0>; 1267 }; 1268 1269 p2u_nvhs_2: phy@3eb0000 { 1270 compatible = "nvidia,tegra234-p2u"; 1271 reg = <0x0 0x03eb0000 0x0 0x10000>; 1272 reg-names = "ctl"; 1273 1274 #phy-cells = <0>; 1275 }; 1276 1277 p2u_nvhs_3: phy@3ec0000 { 1278 compatible = "nvidia,tegra234-p2u"; 1279 reg = <0x0 0x03ec0000 0x0 0x10000>; 1280 reg-names = "ctl"; 1281 1282 #phy-cells = <0>; 1283 }; 1284 1285 p2u_nvhs_4: phy@3ed0000 { 1286 compatible = "nvidia,tegra234-p2u"; 1287 reg = <0x0 0x03ed0000 0x0 0x10000>; 1288 reg-names = "ctl"; 1289 1290 #phy-cells = <0>; 1291 }; 1292 1293 p2u_nvhs_5: phy@3ee0000 { 1294 compatible = "nvidia,tegra234-p2u"; 1295 reg = <0x0 0x03ee0000 0x0 0x10000>; 1296 reg-names = "ctl"; 1297 1298 #phy-cells = <0>; 1299 }; 1300 1301 p2u_nvhs_6: phy@3ef0000 { 1302 compatible = "nvidia,tegra234-p2u"; 1303 reg = <0x0 0x03ef0000 0x0 0x10000>; 1304 reg-names = "ctl"; 1305 1306 #phy-cells = <0>; 1307 }; 1308 1309 p2u_nvhs_7: phy@3f00000 { 1310 compatible = "nvidia,tegra234-p2u"; 1311 reg = <0x0 0x03f00000 0x0 0x10000>; 1312 reg-names = "ctl"; 1313 1314 #phy-cells = <0>; 1315 }; 1316 1317 p2u_gbe_0: phy@3f20000 { 1318 compatible = "nvidia,tegra234-p2u"; 1319 reg = <0x0 0x03f20000 0x0 0x10000>; 1320 reg-names = "ctl"; 1321 1322 #phy-cells = <0>; 1323 }; 1324 1325 p2u_gbe_1: phy@3f30000 { 1326 compatible = "nvidia,tegra234-p2u"; 1327 reg = <0x0 0x03f30000 0x0 0x10000>; 1328 reg-names = "ctl"; 1329 1330 #phy-cells = <0>; 1331 }; 1332 1333 p2u_gbe_2: phy@3f40000 { 1334 compatible = "nvidia,tegra234-p2u"; 1335 reg = <0x0 0x03f40000 0x0 0x10000>; 1336 reg-names = "ctl"; 1337 1338 #phy-cells = <0>; 1339 }; 1340 1341 p2u_gbe_3: phy@3f50000 { 1342 compatible = "nvidia,tegra234-p2u"; 1343 reg = <0x0 0x03f50000 0x0 0x10000>; 1344 reg-names = "ctl"; 1345 1346 #phy-cells = <0>; 1347 }; 1348 1349 p2u_gbe_4: phy@3f60000 { 1350 compatible = "nvidia,tegra234-p2u"; 1351 reg = <0x0 0x03f60000 0x0 0x10000>; 1352 reg-names = "ctl"; 1353 1354 #phy-cells = <0>; 1355 }; 1356 1357 p2u_gbe_5: phy@3f70000 { 1358 compatible = "nvidia,tegra234-p2u"; 1359 reg = <0x0 0x03f70000 0x0 0x10000>; 1360 reg-names = "ctl"; 1361 1362 #phy-cells = <0>; 1363 }; 1364 1365 p2u_gbe_6: phy@3f80000 { 1366 compatible = "nvidia,tegra234-p2u"; 1367 reg = <0x0 0x03f80000 0x0 0x10000>; 1368 reg-names = "ctl"; 1369 1370 #phy-cells = <0>; 1371 }; 1372 1373 p2u_gbe_7: phy@3f90000 { 1374 compatible = "nvidia,tegra234-p2u"; 1375 reg = <0x0 0x03f90000 0x0 0x10000>; 1376 reg-names = "ctl"; 1377 1378 #phy-cells = <0>; 1379 }; 1380 1381 ethernet@6800000 { 1382 compatible = "nvidia,tegra234-mgbe"; 1383 reg = <0x0 0x06800000 0x0 0x10000>, 1384 <0x0 0x06810000 0x0 0x10000>, 1385 <0x0 0x068a0000 0x0 0x10000>; 1386 reg-names = "hypervisor", "mac", "xpcs"; 1387 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1388 interrupt-names = "common"; 1389 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1390 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1391 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1392 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1393 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1394 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1395 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1396 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1397 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1398 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1399 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1400 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1401 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1402 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1403 "rx-pcs", "tx-pcs"; 1404 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1405 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1406 reset-names = "mac", "pcs"; 1407 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1408 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1409 interconnect-names = "dma-mem", "write"; 1410 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1411 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1412 status = "disabled"; 1413 }; 1414 1415 ethernet@6900000 { 1416 compatible = "nvidia,tegra234-mgbe"; 1417 reg = <0x0 0x06900000 0x0 0x10000>, 1418 <0x0 0x06910000 0x0 0x10000>, 1419 <0x0 0x069a0000 0x0 0x10000>; 1420 reg-names = "hypervisor", "mac", "xpcs"; 1421 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1422 interrupt-names = "common"; 1423 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1424 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1425 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1426 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1427 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1428 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1429 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1430 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1431 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1432 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1433 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1434 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1435 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1436 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1437 "rx-pcs", "tx-pcs"; 1438 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1439 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1440 reset-names = "mac", "pcs"; 1441 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1442 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1443 interconnect-names = "dma-mem", "write"; 1444 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1445 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1446 status = "disabled"; 1447 }; 1448 1449 ethernet@6a00000 { 1450 compatible = "nvidia,tegra234-mgbe"; 1451 reg = <0x0 0x06a00000 0x0 0x10000>, 1452 <0x0 0x06a10000 0x0 0x10000>, 1453 <0x0 0x06aa0000 0x0 0x10000>; 1454 reg-names = "hypervisor", "mac", "xpcs"; 1455 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1456 interrupt-names = "common"; 1457 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1458 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1459 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1460 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1461 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1462 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1463 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1464 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1465 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1466 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1467 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1468 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1469 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1470 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1471 "rx-pcs", "tx-pcs"; 1472 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1473 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1474 reset-names = "mac", "pcs"; 1475 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1476 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1477 interconnect-names = "dma-mem", "write"; 1478 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1479 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1480 status = "disabled"; 1481 }; 1482 1483 ethernet@6b00000 { 1484 compatible = "nvidia,tegra234-mgbe"; 1485 reg = <0x0 0x06b00000 0x0 0x10000>, 1486 <0x0 0x06b10000 0x0 0x10000>, 1487 <0x0 0x06ba0000 0x0 0x10000>; 1488 reg-names = "hypervisor", "mac", "xpcs"; 1489 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1490 interrupt-names = "common"; 1491 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1492 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1493 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1494 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1495 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1496 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1497 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1498 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1499 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1500 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1501 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1502 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1503 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1504 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1505 "rx-pcs", "tx-pcs"; 1506 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1507 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1508 reset-names = "mac", "pcs"; 1509 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1510 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1511 interconnect-names = "dma-mem", "write"; 1512 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1513 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1514 status = "disabled"; 1515 }; 1516 1517 smmu_niso1: iommu@8000000 { 1518 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1519 reg = <0x0 0x8000000 0x0 0x1000000>, 1520 <0x0 0x7000000 0x0 0x1000000>; 1521 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1651 stream-match-mask = <0x7f80>; 1652 #global-interrupts = <2>; 1653 #iommu-cells = <1>; 1654 1655 nvidia,memory-controller = <&mc>; 1656 status = "okay"; 1657 }; 1658 1659 sce-fabric@b600000 { 1660 compatible = "nvidia,tegra234-sce-fabric"; 1661 reg = <0x0 0xb600000 0x0 0x40000>; 1662 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1663 status = "okay"; 1664 }; 1665 1666 rce-fabric@be00000 { 1667 compatible = "nvidia,tegra234-rce-fabric"; 1668 reg = <0x0 0xbe00000 0x0 0x40000>; 1669 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1670 status = "okay"; 1671 }; 1672 1673 hsp_aon: hsp@c150000 { 1674 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1675 reg = <0x0 0x0c150000 0x0 0x90000>; 1676 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1680 /* 1681 * Shared interrupt 0 is routed only to AON/SPE, so 1682 * we only have 4 shared interrupts for the CCPLEX. 1683 */ 1684 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1685 #mbox-cells = <2>; 1686 }; 1687 1688 gen2_i2c: i2c@c240000 { 1689 compatible = "nvidia,tegra194-i2c"; 1690 reg = <0x0 0xc240000 0x0 0x100>; 1691 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 status = "disabled"; 1695 clock-frequency = <100000>; 1696 clocks = <&bpmp TEGRA234_CLK_I2C2 1697 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1698 clock-names = "div-clk", "parent"; 1699 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1700 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1701 resets = <&bpmp TEGRA234_RESET_I2C2>; 1702 reset-names = "i2c"; 1703 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1704 dma-coherent; 1705 dmas = <&gpcdma 22>, <&gpcdma 22>; 1706 dma-names = "rx", "tx"; 1707 }; 1708 1709 gen8_i2c: i2c@c250000 { 1710 compatible = "nvidia,tegra194-i2c"; 1711 reg = <0x0 0xc250000 0x0 0x100>; 1712 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 status = "disabled"; 1716 clock-frequency = <400000>; 1717 clocks = <&bpmp TEGRA234_CLK_I2C8 1718 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1719 clock-names = "div-clk", "parent"; 1720 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1721 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1722 resets = <&bpmp TEGRA234_RESET_I2C8>; 1723 reset-names = "i2c"; 1724 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1725 dma-coherent; 1726 dmas = <&gpcdma 0>, <&gpcdma 0>; 1727 dma-names = "rx", "tx"; 1728 }; 1729 1730 rtc@c2a0000 { 1731 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1732 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1733 interrupt-parent = <&pmc>; 1734 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1736 clock-names = "rtc"; 1737 status = "disabled"; 1738 }; 1739 1740 gpio_aon: gpio@c2f0000 { 1741 compatible = "nvidia,tegra234-gpio-aon"; 1742 reg-names = "security", "gpio"; 1743 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1744 <0x0 0x0c2f1000 0x0 0x1000>; 1745 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1749 #interrupt-cells = <2>; 1750 interrupt-controller; 1751 #gpio-cells = <2>; 1752 gpio-controller; 1753 }; 1754 1755 pwm4: pwm@c340000 { 1756 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1757 reg = <0x0 0xc340000 0x0 0x10000>; 1758 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1759 resets = <&bpmp TEGRA234_RESET_PWM4>; 1760 reset-names = "pwm"; 1761 status = "disabled"; 1762 #pwm-cells = <2>; 1763 }; 1764 1765 pmc: pmc@c360000 { 1766 compatible = "nvidia,tegra234-pmc"; 1767 reg = <0x0 0x0c360000 0x0 0x10000>, 1768 <0x0 0x0c370000 0x0 0x10000>, 1769 <0x0 0x0c380000 0x0 0x10000>, 1770 <0x0 0x0c390000 0x0 0x10000>, 1771 <0x0 0x0c3a0000 0x0 0x10000>; 1772 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1773 1774 #interrupt-cells = <2>; 1775 interrupt-controller; 1776 1777 sdmmc1_1v8: sdmmc1-1v8 { 1778 pins = "sdmmc1-hv"; 1779 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1780 }; 1781 1782 sdmmc1_3v3: sdmmc1-3v3 { 1783 pins = "sdmmc1-hv"; 1784 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1785 }; 1786 1787 sdmmc3_1v8: sdmmc3-1v8 { 1788 pins = "sdmmc3-hv"; 1789 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1790 }; 1791 1792 sdmmc3_3v3: sdmmc3-3v3 { 1793 pins = "sdmmc3-hv"; 1794 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1795 }; 1796 }; 1797 1798 aon-fabric@c600000 { 1799 compatible = "nvidia,tegra234-aon-fabric"; 1800 reg = <0x0 0xc600000 0x0 0x40000>; 1801 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1802 status = "okay"; 1803 }; 1804 1805 bpmp-fabric@d600000 { 1806 compatible = "nvidia,tegra234-bpmp-fabric"; 1807 reg = <0x0 0xd600000 0x0 0x40000>; 1808 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1809 status = "okay"; 1810 }; 1811 1812 dce-fabric@de00000 { 1813 compatible = "nvidia,tegra234-sce-fabric"; 1814 reg = <0x0 0xde00000 0x0 0x40000>; 1815 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1816 status = "okay"; 1817 }; 1818 1819 ccplex@e000000 { 1820 compatible = "nvidia,tegra234-ccplex-cluster"; 1821 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1822 nvidia,bpmp = <&bpmp>; 1823 status = "okay"; 1824 }; 1825 1826 gic: interrupt-controller@f400000 { 1827 compatible = "arm,gic-v3"; 1828 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1829 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1830 interrupt-parent = <&gic>; 1831 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1832 1833 #redistributor-regions = <1>; 1834 #interrupt-cells = <3>; 1835 interrupt-controller; 1836 }; 1837 1838 smmu_iso: iommu@10000000 { 1839 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1840 reg = <0x0 0x10000000 0x0 0x1000000>; 1841 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1970 stream-match-mask = <0x7f80>; 1971 #global-interrupts = <1>; 1972 #iommu-cells = <1>; 1973 1974 nvidia,memory-controller = <&mc>; 1975 status = "okay"; 1976 }; 1977 1978 smmu_niso0: iommu@12000000 { 1979 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1980 reg = <0x0 0x12000000 0x0 0x1000000>, 1981 <0x0 0x11000000 0x0 0x1000000>; 1982 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 170 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IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2112 stream-match-mask = <0x7f80>; 2113 #global-interrupts = <2>; 2114 #iommu-cells = <1>; 2115 2116 nvidia,memory-controller = <&mc>; 2117 status = "okay"; 2118 }; 2119 2120 cbb-fabric@13a00000 { 2121 compatible = "nvidia,tegra234-cbb-fabric"; 2122 reg = <0x0 0x13a00000 0x0 0x400000>; 2123 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2124 status = "okay"; 2125 }; 2126 2127 host1x@13e00000 { 2128 compatible = "nvidia,tegra234-host1x"; 2129 reg = <0x0 0x13e00000 0x0 0x10000>, 2130 <0x0 0x13e10000 0x0 0x10000>, 2131 <0x0 0x13e40000 0x0 0x10000>; 2132 reg-names = "common", "hypervisor", "vm"; 2133 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2142 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2143 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2144 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2145 clock-names = "host1x"; 2146 2147 #address-cells = <2>; 2148 #size-cells = <2>; 2149 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2150 2151 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2152 interconnect-names = "dma-mem"; 2153 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2154 dma-coherent; 2155 2156 /* Context isolation domains */ 2157 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2158 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2159 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2160 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2161 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2162 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2163 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2164 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2165 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2166 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2167 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2168 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2169 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2170 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2171 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2172 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2173 2174 vic@15340000 { 2175 compatible = "nvidia,tegra234-vic"; 2176 reg = <0x0 0x15340000 0x0 0x00040000>; 2177 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2178 clocks = <&bpmp TEGRA234_CLK_VIC>; 2179 clock-names = "vic"; 2180 resets = <&bpmp TEGRA234_RESET_VIC>; 2181 reset-names = "vic"; 2182 2183 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2184 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2185 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2186 interconnect-names = "dma-mem", "write"; 2187 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2188 dma-coherent; 2189 }; 2190 2191 nvdec@15480000 { 2192 compatible = "nvidia,tegra234-nvdec"; 2193 reg = <0x0 0x15480000 0x0 0x00040000>; 2194 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2195 <&bpmp TEGRA234_CLK_FUSE>, 2196 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2197 clock-names = "nvdec", "fuse", "tsec_pka"; 2198 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2199 reset-names = "nvdec"; 2200 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2201 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2202 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2203 interconnect-names = "dma-mem", "write"; 2204 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2205 dma-coherent; 2206 2207 nvidia,memory-controller = <&mc>; 2208 2209 /* 2210 * Placeholder values that firmware needs to update with the real 2211 * offsets parsed from the microcode headers. 2212 */ 2213 nvidia,bl-manifest-offset = <0>; 2214 nvidia,bl-data-offset = <0>; 2215 nvidia,bl-code-offset = <0>; 2216 nvidia,os-manifest-offset = <0>; 2217 nvidia,os-data-offset = <0>; 2218 nvidia,os-code-offset = <0>; 2219 2220 /* 2221 * Firmware needs to set this to "okay" once the above values have 2222 * been updated. 2223 */ 2224 status = "disabled"; 2225 }; 2226 }; 2227 2228 pcie@140a0000 { 2229 compatible = "nvidia,tegra234-pcie"; 2230 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2231 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2232 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2233 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2234 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2235 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2236 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2237 2238 #address-cells = <3>; 2239 #size-cells = <2>; 2240 device_type = "pci"; 2241 num-lanes = <4>; 2242 num-viewport = <8>; 2243 linux,pci-domain = <8>; 2244 2245 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2246 clock-names = "core"; 2247 2248 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2249 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2250 reset-names = "apb", "core"; 2251 2252 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2253 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2254 interrupt-names = "intr", "msi"; 2255 2256 #interrupt-cells = <1>; 2257 interrupt-map-mask = <0 0 0 0>; 2258 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2259 2260 nvidia,bpmp = <&bpmp 8>; 2261 2262 nvidia,aspm-cmrt-us = <60>; 2263 nvidia,aspm-pwr-on-t-us = <20>; 2264 nvidia,aspm-l0s-entrance-latency-us = <3>; 2265 2266 bus-range = <0x0 0xff>; 2267 2268 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2269 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2270 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2271 2272 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2273 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2274 interconnect-names = "dma-mem", "write"; 2275 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2276 iommu-map-mask = <0x0>; 2277 dma-coherent; 2278 2279 status = "disabled"; 2280 }; 2281 2282 pcie@140c0000 { 2283 compatible = "nvidia,tegra234-pcie"; 2284 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2285 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2286 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2287 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2288 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2289 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2290 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2291 2292 #address-cells = <3>; 2293 #size-cells = <2>; 2294 device_type = "pci"; 2295 num-lanes = <4>; 2296 num-viewport = <8>; 2297 linux,pci-domain = <9>; 2298 2299 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2300 clock-names = "core"; 2301 2302 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2303 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2304 reset-names = "apb", "core"; 2305 2306 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2307 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2308 interrupt-names = "intr", "msi"; 2309 2310 #interrupt-cells = <1>; 2311 interrupt-map-mask = <0 0 0 0>; 2312 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2313 2314 nvidia,bpmp = <&bpmp 9>; 2315 2316 nvidia,aspm-cmrt-us = <60>; 2317 nvidia,aspm-pwr-on-t-us = <20>; 2318 nvidia,aspm-l0s-entrance-latency-us = <3>; 2319 2320 bus-range = <0x0 0xff>; 2321 2322 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2323 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2324 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2325 2326 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2327 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2328 interconnect-names = "dma-mem", "write"; 2329 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2330 iommu-map-mask = <0x0>; 2331 dma-coherent; 2332 2333 status = "disabled"; 2334 }; 2335 2336 pcie@140e0000 { 2337 compatible = "nvidia,tegra234-pcie"; 2338 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2339 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2340 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2341 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2342 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2343 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2344 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2345 2346 #address-cells = <3>; 2347 #size-cells = <2>; 2348 device_type = "pci"; 2349 num-lanes = <4>; 2350 num-viewport = <8>; 2351 linux,pci-domain = <10>; 2352 2353 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2354 clock-names = "core"; 2355 2356 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2357 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2358 reset-names = "apb", "core"; 2359 2360 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2361 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2362 interrupt-names = "intr", "msi"; 2363 2364 #interrupt-cells = <1>; 2365 interrupt-map-mask = <0 0 0 0>; 2366 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2367 2368 nvidia,bpmp = <&bpmp 10>; 2369 2370 nvidia,aspm-cmrt-us = <60>; 2371 nvidia,aspm-pwr-on-t-us = <20>; 2372 nvidia,aspm-l0s-entrance-latency-us = <3>; 2373 2374 bus-range = <0x0 0xff>; 2375 2376 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2377 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2378 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2379 2380 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2381 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2382 interconnect-names = "dma-mem", "write"; 2383 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2384 iommu-map-mask = <0x0>; 2385 dma-coherent; 2386 2387 status = "disabled"; 2388 }; 2389 2390 pcie-ep@140e0000 { 2391 compatible = "nvidia,tegra234-pcie-ep"; 2392 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2393 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2394 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2395 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2396 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2397 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2398 2399 num-lanes = <4>; 2400 2401 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2402 clock-names = "core"; 2403 2404 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2405 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2406 reset-names = "apb", "core"; 2407 2408 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2409 interrupt-names = "intr"; 2410 2411 nvidia,bpmp = <&bpmp 10>; 2412 2413 nvidia,enable-ext-refclk; 2414 nvidia,aspm-cmrt-us = <60>; 2415 nvidia,aspm-pwr-on-t-us = <20>; 2416 nvidia,aspm-l0s-entrance-latency-us = <3>; 2417 2418 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2419 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2420 interconnect-names = "dma-mem", "write"; 2421 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2422 iommu-map-mask = <0x0>; 2423 dma-coherent; 2424 2425 status = "disabled"; 2426 }; 2427 2428 pcie@14100000 { 2429 compatible = "nvidia,tegra234-pcie"; 2430 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2431 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2432 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2433 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2434 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2435 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2436 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2437 2438 #address-cells = <3>; 2439 #size-cells = <2>; 2440 device_type = "pci"; 2441 num-lanes = <1>; 2442 num-viewport = <8>; 2443 linux,pci-domain = <1>; 2444 2445 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2446 clock-names = "core"; 2447 2448 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2449 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2450 reset-names = "apb", "core"; 2451 2452 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2453 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2454 interrupt-names = "intr", "msi"; 2455 2456 #interrupt-cells = <1>; 2457 interrupt-map-mask = <0 0 0 0>; 2458 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2459 2460 nvidia,bpmp = <&bpmp 1>; 2461 2462 nvidia,aspm-cmrt-us = <60>; 2463 nvidia,aspm-pwr-on-t-us = <20>; 2464 nvidia,aspm-l0s-entrance-latency-us = <3>; 2465 2466 bus-range = <0x0 0xff>; 2467 2468 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2469 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2470 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2471 2472 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2473 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2474 interconnect-names = "dma-mem", "write"; 2475 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2476 iommu-map-mask = <0x0>; 2477 dma-coherent; 2478 2479 status = "disabled"; 2480 }; 2481 2482 pcie@14120000 { 2483 compatible = "nvidia,tegra234-pcie"; 2484 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2485 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2486 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2487 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2488 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2489 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2490 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2491 2492 #address-cells = <3>; 2493 #size-cells = <2>; 2494 device_type = "pci"; 2495 num-lanes = <1>; 2496 num-viewport = <8>; 2497 linux,pci-domain = <2>; 2498 2499 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2500 clock-names = "core"; 2501 2502 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2503 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2504 reset-names = "apb", "core"; 2505 2506 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2507 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2508 interrupt-names = "intr", "msi"; 2509 2510 #interrupt-cells = <1>; 2511 interrupt-map-mask = <0 0 0 0>; 2512 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2513 2514 nvidia,bpmp = <&bpmp 2>; 2515 2516 nvidia,aspm-cmrt-us = <60>; 2517 nvidia,aspm-pwr-on-t-us = <20>; 2518 nvidia,aspm-l0s-entrance-latency-us = <3>; 2519 2520 bus-range = <0x0 0xff>; 2521 2522 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2523 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2524 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2525 2526 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2527 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2528 interconnect-names = "dma-mem", "write"; 2529 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2530 iommu-map-mask = <0x0>; 2531 dma-coherent; 2532 2533 status = "disabled"; 2534 }; 2535 2536 pcie@14140000 { 2537 compatible = "nvidia,tegra234-pcie"; 2538 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2539 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2540 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2541 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2542 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2543 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2544 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2545 2546 #address-cells = <3>; 2547 #size-cells = <2>; 2548 device_type = "pci"; 2549 num-lanes = <1>; 2550 num-viewport = <8>; 2551 linux,pci-domain = <3>; 2552 2553 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2554 clock-names = "core"; 2555 2556 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2557 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2558 reset-names = "apb", "core"; 2559 2560 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2561 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2562 interrupt-names = "intr", "msi"; 2563 2564 #interrupt-cells = <1>; 2565 interrupt-map-mask = <0 0 0 0>; 2566 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2567 2568 nvidia,bpmp = <&bpmp 3>; 2569 2570 nvidia,aspm-cmrt-us = <60>; 2571 nvidia,aspm-pwr-on-t-us = <20>; 2572 nvidia,aspm-l0s-entrance-latency-us = <3>; 2573 2574 bus-range = <0x0 0xff>; 2575 2576 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2577 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2578 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2579 2580 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2581 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2582 interconnect-names = "dma-mem", "write"; 2583 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2584 iommu-map-mask = <0x0>; 2585 dma-coherent; 2586 2587 status = "disabled"; 2588 }; 2589 2590 pcie@14160000 { 2591 compatible = "nvidia,tegra234-pcie"; 2592 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2593 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2594 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2595 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2596 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2597 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2598 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2599 2600 #address-cells = <3>; 2601 #size-cells = <2>; 2602 device_type = "pci"; 2603 num-lanes = <4>; 2604 num-viewport = <8>; 2605 linux,pci-domain = <4>; 2606 2607 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2608 clock-names = "core"; 2609 2610 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2611 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2612 reset-names = "apb", "core"; 2613 2614 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2615 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2616 interrupt-names = "intr", "msi"; 2617 2618 #interrupt-cells = <1>; 2619 interrupt-map-mask = <0 0 0 0>; 2620 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2621 2622 nvidia,bpmp = <&bpmp 4>; 2623 2624 nvidia,aspm-cmrt-us = <60>; 2625 nvidia,aspm-pwr-on-t-us = <20>; 2626 nvidia,aspm-l0s-entrance-latency-us = <3>; 2627 2628 bus-range = <0x0 0xff>; 2629 2630 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2631 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2632 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2633 2634 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2635 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2636 interconnect-names = "dma-mem", "write"; 2637 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2638 iommu-map-mask = <0x0>; 2639 dma-coherent; 2640 2641 status = "disabled"; 2642 }; 2643 2644 pcie@14180000 { 2645 compatible = "nvidia,tegra234-pcie"; 2646 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2647 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2648 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2649 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2650 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2651 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2652 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2653 2654 #address-cells = <3>; 2655 #size-cells = <2>; 2656 device_type = "pci"; 2657 num-lanes = <4>; 2658 num-viewport = <8>; 2659 linux,pci-domain = <0>; 2660 2661 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2662 clock-names = "core"; 2663 2664 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2665 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2666 reset-names = "apb", "core"; 2667 2668 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2669 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2670 interrupt-names = "intr", "msi"; 2671 2672 #interrupt-cells = <1>; 2673 interrupt-map-mask = <0 0 0 0>; 2674 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2675 2676 nvidia,bpmp = <&bpmp 0>; 2677 2678 nvidia,aspm-cmrt-us = <60>; 2679 nvidia,aspm-pwr-on-t-us = <20>; 2680 nvidia,aspm-l0s-entrance-latency-us = <3>; 2681 2682 bus-range = <0x0 0xff>; 2683 2684 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2685 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2686 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2687 2688 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2689 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2690 interconnect-names = "dma-mem", "write"; 2691 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2692 iommu-map-mask = <0x0>; 2693 dma-coherent; 2694 2695 status = "disabled"; 2696 }; 2697 2698 pcie@141a0000 { 2699 compatible = "nvidia,tegra234-pcie"; 2700 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2701 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2702 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2703 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2704 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2705 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2706 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2707 2708 #address-cells = <3>; 2709 #size-cells = <2>; 2710 device_type = "pci"; 2711 num-lanes = <8>; 2712 num-viewport = <8>; 2713 linux,pci-domain = <5>; 2714 2715 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2716 clock-names = "core"; 2717 2718 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2719 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2720 reset-names = "apb", "core"; 2721 2722 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2723 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2724 interrupt-names = "intr", "msi"; 2725 2726 #interrupt-cells = <1>; 2727 interrupt-map-mask = <0 0 0 0>; 2728 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2729 2730 nvidia,bpmp = <&bpmp 5>; 2731 2732 nvidia,aspm-cmrt-us = <60>; 2733 nvidia,aspm-pwr-on-t-us = <20>; 2734 nvidia,aspm-l0s-entrance-latency-us = <3>; 2735 2736 bus-range = <0x0 0xff>; 2737 2738 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2739 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2740 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2741 2742 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2743 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2744 interconnect-names = "dma-mem", "write"; 2745 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2746 iommu-map-mask = <0x0>; 2747 dma-coherent; 2748 2749 status = "disabled"; 2750 }; 2751 2752 pcie-ep@141a0000 { 2753 compatible = "nvidia,tegra234-pcie-ep"; 2754 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2755 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2756 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2757 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2758 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2759 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2760 2761 num-lanes = <8>; 2762 2763 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2764 clock-names = "core"; 2765 2766 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2767 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2768 reset-names = "apb", "core"; 2769 2770 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2771 interrupt-names = "intr"; 2772 2773 nvidia,bpmp = <&bpmp 5>; 2774 2775 nvidia,enable-ext-refclk; 2776 nvidia,aspm-cmrt-us = <60>; 2777 nvidia,aspm-pwr-on-t-us = <20>; 2778 nvidia,aspm-l0s-entrance-latency-us = <3>; 2779 2780 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2781 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2782 interconnect-names = "dma-mem", "write"; 2783 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2784 iommu-map-mask = <0x0>; 2785 dma-coherent; 2786 2787 status = "disabled"; 2788 }; 2789 2790 pcie@141c0000 { 2791 compatible = "nvidia,tegra234-pcie"; 2792 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2793 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2794 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2795 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2796 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2797 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2798 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2799 2800 #address-cells = <3>; 2801 #size-cells = <2>; 2802 device_type = "pci"; 2803 num-lanes = <4>; 2804 num-viewport = <8>; 2805 linux,pci-domain = <6>; 2806 2807 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2808 clock-names = "core"; 2809 2810 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2811 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2812 reset-names = "apb", "core"; 2813 2814 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2815 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2816 interrupt-names = "intr", "msi"; 2817 2818 #interrupt-cells = <1>; 2819 interrupt-map-mask = <0 0 0 0>; 2820 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2821 2822 nvidia,bpmp = <&bpmp 6>; 2823 2824 nvidia,aspm-cmrt-us = <60>; 2825 nvidia,aspm-pwr-on-t-us = <20>; 2826 nvidia,aspm-l0s-entrance-latency-us = <3>; 2827 2828 bus-range = <0x0 0xff>; 2829 2830 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2831 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2832 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2833 2834 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2835 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2836 interconnect-names = "dma-mem", "write"; 2837 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2838 iommu-map-mask = <0x0>; 2839 dma-coherent; 2840 2841 status = "disabled"; 2842 }; 2843 2844 pcie-ep@141c0000 { 2845 compatible = "nvidia,tegra234-pcie-ep"; 2846 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2847 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2848 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2849 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2850 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2851 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2852 2853 num-lanes = <4>; 2854 2855 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2856 clock-names = "core"; 2857 2858 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2859 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2860 reset-names = "apb", "core"; 2861 2862 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2863 interrupt-names = "intr"; 2864 2865 nvidia,bpmp = <&bpmp 6>; 2866 2867 nvidia,enable-ext-refclk; 2868 nvidia,aspm-cmrt-us = <60>; 2869 nvidia,aspm-pwr-on-t-us = <20>; 2870 nvidia,aspm-l0s-entrance-latency-us = <3>; 2871 2872 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2873 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2874 interconnect-names = "dma-mem", "write"; 2875 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2876 iommu-map-mask = <0x0>; 2877 dma-coherent; 2878 2879 status = "disabled"; 2880 }; 2881 2882 pcie@141e0000 { 2883 compatible = "nvidia,tegra234-pcie"; 2884 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2885 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2886 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2887 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2888 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2889 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2890 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2891 2892 #address-cells = <3>; 2893 #size-cells = <2>; 2894 device_type = "pci"; 2895 num-lanes = <8>; 2896 num-viewport = <8>; 2897 linux,pci-domain = <7>; 2898 2899 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2900 clock-names = "core"; 2901 2902 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2903 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2904 reset-names = "apb", "core"; 2905 2906 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2907 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2908 interrupt-names = "intr", "msi"; 2909 2910 #interrupt-cells = <1>; 2911 interrupt-map-mask = <0 0 0 0>; 2912 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2913 2914 nvidia,bpmp = <&bpmp 7>; 2915 2916 nvidia,aspm-cmrt-us = <60>; 2917 nvidia,aspm-pwr-on-t-us = <20>; 2918 nvidia,aspm-l0s-entrance-latency-us = <3>; 2919 2920 bus-range = <0x0 0xff>; 2921 2922 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2923 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2924 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2925 2926 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2927 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2928 interconnect-names = "dma-mem", "write"; 2929 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2930 iommu-map-mask = <0x0>; 2931 dma-coherent; 2932 2933 status = "disabled"; 2934 }; 2935 2936 pcie-ep@141e0000 { 2937 compatible = "nvidia,tegra234-pcie-ep"; 2938 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2939 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2940 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2941 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2942 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2943 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2944 2945 num-lanes = <8>; 2946 2947 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2948 clock-names = "core"; 2949 2950 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2951 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2952 reset-names = "apb", "core"; 2953 2954 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2955 interrupt-names = "intr"; 2956 2957 nvidia,bpmp = <&bpmp 7>; 2958 2959 nvidia,enable-ext-refclk; 2960 nvidia,aspm-cmrt-us = <60>; 2961 nvidia,aspm-pwr-on-t-us = <20>; 2962 nvidia,aspm-l0s-entrance-latency-us = <3>; 2963 2964 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2965 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2966 interconnect-names = "dma-mem", "write"; 2967 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2968 iommu-map-mask = <0x0>; 2969 dma-coherent; 2970 2971 status = "disabled"; 2972 }; 2973 }; 2974 2975 sram@40000000 { 2976 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2977 reg = <0x0 0x40000000 0x0 0x80000>; 2978 2979 #address-cells = <1>; 2980 #size-cells = <1>; 2981 ranges = <0x0 0x0 0x40000000 0x80000>; 2982 2983 no-memory-wc; 2984 2985 cpu_bpmp_tx: sram@70000 { 2986 reg = <0x70000 0x1000>; 2987 label = "cpu-bpmp-tx"; 2988 pool; 2989 }; 2990 2991 cpu_bpmp_rx: sram@71000 { 2992 reg = <0x71000 0x1000>; 2993 label = "cpu-bpmp-rx"; 2994 pool; 2995 }; 2996 }; 2997 2998 bpmp: bpmp { 2999 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 3000 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 3001 TEGRA_HSP_DB_MASTER_BPMP>; 3002 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 3003 #clock-cells = <1>; 3004 #reset-cells = <1>; 3005 #power-domain-cells = <1>; 3006 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 3007 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 3008 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 3009 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 3010 interconnect-names = "read", "write", "dma-mem", "dma-write"; 3011 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 3012 3013 bpmp_i2c: i2c { 3014 compatible = "nvidia,tegra186-bpmp-i2c"; 3015 nvidia,bpmp-bus-id = <5>; 3016 #address-cells = <1>; 3017 #size-cells = <0>; 3018 }; 3019 }; 3020 3021 cpus { 3022 #address-cells = <1>; 3023 #size-cells = <0>; 3024 3025 cpu0_0: cpu@0 { 3026 compatible = "arm,cortex-a78"; 3027 device_type = "cpu"; 3028 reg = <0x00000>; 3029 3030 enable-method = "psci"; 3031 3032 i-cache-size = <65536>; 3033 i-cache-line-size = <64>; 3034 i-cache-sets = <256>; 3035 d-cache-size = <65536>; 3036 d-cache-line-size = <64>; 3037 d-cache-sets = <256>; 3038 next-level-cache = <&l2c0_0>; 3039 }; 3040 3041 cpu0_1: cpu@100 { 3042 compatible = "arm,cortex-a78"; 3043 device_type = "cpu"; 3044 reg = <0x00100>; 3045 3046 enable-method = "psci"; 3047 3048 i-cache-size = <65536>; 3049 i-cache-line-size = <64>; 3050 i-cache-sets = <256>; 3051 d-cache-size = <65536>; 3052 d-cache-line-size = <64>; 3053 d-cache-sets = <256>; 3054 next-level-cache = <&l2c0_1>; 3055 }; 3056 3057 cpu0_2: cpu@200 { 3058 compatible = "arm,cortex-a78"; 3059 device_type = "cpu"; 3060 reg = <0x00200>; 3061 3062 enable-method = "psci"; 3063 3064 i-cache-size = <65536>; 3065 i-cache-line-size = <64>; 3066 i-cache-sets = <256>; 3067 d-cache-size = <65536>; 3068 d-cache-line-size = <64>; 3069 d-cache-sets = <256>; 3070 next-level-cache = <&l2c0_2>; 3071 }; 3072 3073 cpu0_3: cpu@300 { 3074 compatible = "arm,cortex-a78"; 3075 device_type = "cpu"; 3076 reg = <0x00300>; 3077 3078 enable-method = "psci"; 3079 3080 i-cache-size = <65536>; 3081 i-cache-line-size = <64>; 3082 i-cache-sets = <256>; 3083 d-cache-size = <65536>; 3084 d-cache-line-size = <64>; 3085 d-cache-sets = <256>; 3086 next-level-cache = <&l2c0_3>; 3087 }; 3088 3089 cpu1_0: cpu@10000 { 3090 compatible = "arm,cortex-a78"; 3091 device_type = "cpu"; 3092 reg = <0x10000>; 3093 3094 enable-method = "psci"; 3095 3096 i-cache-size = <65536>; 3097 i-cache-line-size = <64>; 3098 i-cache-sets = <256>; 3099 d-cache-size = <65536>; 3100 d-cache-line-size = <64>; 3101 d-cache-sets = <256>; 3102 next-level-cache = <&l2c1_0>; 3103 }; 3104 3105 cpu1_1: cpu@10100 { 3106 compatible = "arm,cortex-a78"; 3107 device_type = "cpu"; 3108 reg = <0x10100>; 3109 3110 enable-method = "psci"; 3111 3112 i-cache-size = <65536>; 3113 i-cache-line-size = <64>; 3114 i-cache-sets = <256>; 3115 d-cache-size = <65536>; 3116 d-cache-line-size = <64>; 3117 d-cache-sets = <256>; 3118 next-level-cache = <&l2c1_1>; 3119 }; 3120 3121 cpu1_2: cpu@10200 { 3122 compatible = "arm,cortex-a78"; 3123 device_type = "cpu"; 3124 reg = <0x10200>; 3125 3126 enable-method = "psci"; 3127 3128 i-cache-size = <65536>; 3129 i-cache-line-size = <64>; 3130 i-cache-sets = <256>; 3131 d-cache-size = <65536>; 3132 d-cache-line-size = <64>; 3133 d-cache-sets = <256>; 3134 next-level-cache = <&l2c1_2>; 3135 }; 3136 3137 cpu1_3: cpu@10300 { 3138 compatible = "arm,cortex-a78"; 3139 device_type = "cpu"; 3140 reg = <0x10300>; 3141 3142 enable-method = "psci"; 3143 3144 i-cache-size = <65536>; 3145 i-cache-line-size = <64>; 3146 i-cache-sets = <256>; 3147 d-cache-size = <65536>; 3148 d-cache-line-size = <64>; 3149 d-cache-sets = <256>; 3150 next-level-cache = <&l2c1_3>; 3151 }; 3152 3153 cpu2_0: cpu@20000 { 3154 compatible = "arm,cortex-a78"; 3155 device_type = "cpu"; 3156 reg = <0x20000>; 3157 3158 enable-method = "psci"; 3159 3160 i-cache-size = <65536>; 3161 i-cache-line-size = <64>; 3162 i-cache-sets = <256>; 3163 d-cache-size = <65536>; 3164 d-cache-line-size = <64>; 3165 d-cache-sets = <256>; 3166 next-level-cache = <&l2c2_0>; 3167 }; 3168 3169 cpu2_1: cpu@20100 { 3170 compatible = "arm,cortex-a78"; 3171 device_type = "cpu"; 3172 reg = <0x20100>; 3173 3174 enable-method = "psci"; 3175 3176 i-cache-size = <65536>; 3177 i-cache-line-size = <64>; 3178 i-cache-sets = <256>; 3179 d-cache-size = <65536>; 3180 d-cache-line-size = <64>; 3181 d-cache-sets = <256>; 3182 next-level-cache = <&l2c2_1>; 3183 }; 3184 3185 cpu2_2: cpu@20200 { 3186 compatible = "arm,cortex-a78"; 3187 device_type = "cpu"; 3188 reg = <0x20200>; 3189 3190 enable-method = "psci"; 3191 3192 i-cache-size = <65536>; 3193 i-cache-line-size = <64>; 3194 i-cache-sets = <256>; 3195 d-cache-size = <65536>; 3196 d-cache-line-size = <64>; 3197 d-cache-sets = <256>; 3198 next-level-cache = <&l2c2_2>; 3199 }; 3200 3201 cpu2_3: cpu@20300 { 3202 compatible = "arm,cortex-a78"; 3203 device_type = "cpu"; 3204 reg = <0x20300>; 3205 3206 enable-method = "psci"; 3207 3208 i-cache-size = <65536>; 3209 i-cache-line-size = <64>; 3210 i-cache-sets = <256>; 3211 d-cache-size = <65536>; 3212 d-cache-line-size = <64>; 3213 d-cache-sets = <256>; 3214 next-level-cache = <&l2c2_3>; 3215 }; 3216 3217 cpu-map { 3218 cluster0 { 3219 core0 { 3220 cpu = <&cpu0_0>; 3221 }; 3222 3223 core1 { 3224 cpu = <&cpu0_1>; 3225 }; 3226 3227 core2 { 3228 cpu = <&cpu0_2>; 3229 }; 3230 3231 core3 { 3232 cpu = <&cpu0_3>; 3233 }; 3234 }; 3235 3236 cluster1 { 3237 core0 { 3238 cpu = <&cpu1_0>; 3239 }; 3240 3241 core1 { 3242 cpu = <&cpu1_1>; 3243 }; 3244 3245 core2 { 3246 cpu = <&cpu1_2>; 3247 }; 3248 3249 core3 { 3250 cpu = <&cpu1_3>; 3251 }; 3252 }; 3253 3254 cluster2 { 3255 core0 { 3256 cpu = <&cpu2_0>; 3257 }; 3258 3259 core1 { 3260 cpu = <&cpu2_1>; 3261 }; 3262 3263 core2 { 3264 cpu = <&cpu2_2>; 3265 }; 3266 3267 core3 { 3268 cpu = <&cpu2_3>; 3269 }; 3270 }; 3271 }; 3272 3273 l2c0_0: l2-cache00 { 3274 compatible = "cache"; 3275 cache-size = <262144>; 3276 cache-line-size = <64>; 3277 cache-sets = <512>; 3278 cache-unified; 3279 cache-level = <2>; 3280 next-level-cache = <&l3c0>; 3281 }; 3282 3283 l2c0_1: l2-cache01 { 3284 compatible = "cache"; 3285 cache-size = <262144>; 3286 cache-line-size = <64>; 3287 cache-sets = <512>; 3288 cache-unified; 3289 cache-level = <2>; 3290 next-level-cache = <&l3c0>; 3291 }; 3292 3293 l2c0_2: l2-cache02 { 3294 compatible = "cache"; 3295 cache-size = <262144>; 3296 cache-line-size = <64>; 3297 cache-sets = <512>; 3298 cache-unified; 3299 cache-level = <2>; 3300 next-level-cache = <&l3c0>; 3301 }; 3302 3303 l2c0_3: l2-cache03 { 3304 compatible = "cache"; 3305 cache-size = <262144>; 3306 cache-line-size = <64>; 3307 cache-sets = <512>; 3308 cache-unified; 3309 cache-level = <2>; 3310 next-level-cache = <&l3c0>; 3311 }; 3312 3313 l2c1_0: l2-cache10 { 3314 compatible = "cache"; 3315 cache-size = <262144>; 3316 cache-line-size = <64>; 3317 cache-sets = <512>; 3318 cache-unified; 3319 cache-level = <2>; 3320 next-level-cache = <&l3c1>; 3321 }; 3322 3323 l2c1_1: l2-cache11 { 3324 compatible = "cache"; 3325 cache-size = <262144>; 3326 cache-line-size = <64>; 3327 cache-sets = <512>; 3328 cache-unified; 3329 cache-level = <2>; 3330 next-level-cache = <&l3c1>; 3331 }; 3332 3333 l2c1_2: l2-cache12 { 3334 compatible = "cache"; 3335 cache-size = <262144>; 3336 cache-line-size = <64>; 3337 cache-sets = <512>; 3338 cache-unified; 3339 cache-level = <2>; 3340 next-level-cache = <&l3c1>; 3341 }; 3342 3343 l2c1_3: l2-cache13 { 3344 compatible = "cache"; 3345 cache-size = <262144>; 3346 cache-line-size = <64>; 3347 cache-sets = <512>; 3348 cache-unified; 3349 cache-level = <2>; 3350 next-level-cache = <&l3c1>; 3351 }; 3352 3353 l2c2_0: l2-cache20 { 3354 compatible = "cache"; 3355 cache-size = <262144>; 3356 cache-line-size = <64>; 3357 cache-sets = <512>; 3358 cache-unified; 3359 cache-level = <2>; 3360 next-level-cache = <&l3c2>; 3361 }; 3362 3363 l2c2_1: l2-cache21 { 3364 compatible = "cache"; 3365 cache-size = <262144>; 3366 cache-line-size = <64>; 3367 cache-sets = <512>; 3368 cache-unified; 3369 cache-level = <2>; 3370 next-level-cache = <&l3c2>; 3371 }; 3372 3373 l2c2_2: l2-cache22 { 3374 compatible = "cache"; 3375 cache-size = <262144>; 3376 cache-line-size = <64>; 3377 cache-sets = <512>; 3378 cache-unified; 3379 cache-level = <2>; 3380 next-level-cache = <&l3c2>; 3381 }; 3382 3383 l2c2_3: l2-cache23 { 3384 compatible = "cache"; 3385 cache-size = <262144>; 3386 cache-line-size = <64>; 3387 cache-sets = <512>; 3388 cache-unified; 3389 cache-level = <2>; 3390 next-level-cache = <&l3c2>; 3391 }; 3392 3393 l3c0: l3-cache0 { 3394 compatible = "cache"; 3395 cache-unified; 3396 cache-size = <2097152>; 3397 cache-line-size = <64>; 3398 cache-sets = <2048>; 3399 cache-level = <3>; 3400 }; 3401 3402 l3c1: l3-cache1 { 3403 compatible = "cache"; 3404 cache-unified; 3405 cache-size = <2097152>; 3406 cache-line-size = <64>; 3407 cache-sets = <2048>; 3408 cache-level = <3>; 3409 }; 3410 3411 l3c2: l3-cache2 { 3412 compatible = "cache"; 3413 cache-unified; 3414 cache-size = <2097152>; 3415 cache-line-size = <64>; 3416 cache-sets = <2048>; 3417 cache-level = <3>; 3418 }; 3419 }; 3420 3421 pmu { 3422 compatible = "arm,cortex-a78-pmu"; 3423 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3424 status = "okay"; 3425 }; 3426 3427 psci { 3428 compatible = "arm,psci-1.0"; 3429 status = "okay"; 3430 method = "smc"; 3431 }; 3432 3433 tcu: serial { 3434 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3435 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3436 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3437 mbox-names = "rx", "tx"; 3438 status = "disabled"; 3439 }; 3440 3441 sound { 3442 status = "disabled"; 3443 3444 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3445 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3446 clock-names = "pll_a", "plla_out0"; 3447 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3448 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3449 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3450 assigned-clock-parents = <0>, 3451 <&bpmp TEGRA234_CLK_PLLA>, 3452 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3453 }; 3454 3455 timer { 3456 compatible = "arm,armv8-timer"; 3457 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3458 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3459 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3460 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3461 interrupt-parent = <&gic>; 3462 always-on; 3463 }; 3464}; 3465