1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_atomic.h" 32 #include "intel_audio.h" 33 #include "intel_audio_regs.h" 34 #include "intel_cdclk.h" 35 #include "intel_crtc.h" 36 #include "intel_de.h" 37 #include "intel_display_types.h" 38 #include "intel_lpe_audio.h" 39 40 /** 41 * DOC: High Definition Audio over HDMI and Display Port 42 * 43 * The graphics and audio drivers together support High Definition Audio over 44 * HDMI and Display Port. The audio programming sequences are divided into audio 45 * codec and controller enable and disable sequences. The graphics driver 46 * handles the audio codec sequences, while the audio driver handles the audio 47 * controller sequences. 48 * 49 * The disable sequences must be performed before disabling the transcoder or 50 * port. The enable sequences may only be performed after enabling the 51 * transcoder and port, and after completed link training. Therefore the audio 52 * enable/disable sequences are part of the modeset sequence. 53 * 54 * The codec and controller sequences could be done either parallel or serial, 55 * but generally the ELDV/PD change in the codec sequence indicates to the audio 56 * driver that the controller sequence should start. Indeed, most of the 57 * co-operation between the graphics and audio drivers is handled via audio 58 * related registers. (The notable exception is the power management, not 59 * covered here.) 60 * 61 * The struct &i915_audio_component is used to interact between the graphics 62 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 63 * defined in graphics driver and called in audio driver. The 64 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 65 */ 66 67 struct intel_audio_funcs { 68 void (*audio_codec_enable)(struct intel_encoder *encoder, 69 const struct intel_crtc_state *crtc_state, 70 const struct drm_connector_state *conn_state); 71 void (*audio_codec_disable)(struct intel_encoder *encoder, 72 const struct intel_crtc_state *old_crtc_state, 73 const struct drm_connector_state *old_conn_state); 74 }; 75 76 /* DP N/M table */ 77 #define LC_810M 810000 78 #define LC_540M 540000 79 #define LC_270M 270000 80 #define LC_162M 162000 81 82 struct dp_aud_n_m { 83 int sample_rate; 84 int clock; 85 u16 m; 86 u16 n; 87 }; 88 89 struct hdmi_aud_ncts { 90 int sample_rate; 91 int clock; 92 int n; 93 int cts; 94 }; 95 96 /* Values according to DP 1.4 Table 2-104 */ 97 static const struct dp_aud_n_m dp_aud_n_m[] = { 98 { 32000, LC_162M, 1024, 10125 }, 99 { 44100, LC_162M, 784, 5625 }, 100 { 48000, LC_162M, 512, 3375 }, 101 { 64000, LC_162M, 2048, 10125 }, 102 { 88200, LC_162M, 1568, 5625 }, 103 { 96000, LC_162M, 1024, 3375 }, 104 { 128000, LC_162M, 4096, 10125 }, 105 { 176400, LC_162M, 3136, 5625 }, 106 { 192000, LC_162M, 2048, 3375 }, 107 { 32000, LC_270M, 1024, 16875 }, 108 { 44100, LC_270M, 784, 9375 }, 109 { 48000, LC_270M, 512, 5625 }, 110 { 64000, LC_270M, 2048, 16875 }, 111 { 88200, LC_270M, 1568, 9375 }, 112 { 96000, LC_270M, 1024, 5625 }, 113 { 128000, LC_270M, 4096, 16875 }, 114 { 176400, LC_270M, 3136, 9375 }, 115 { 192000, LC_270M, 2048, 5625 }, 116 { 32000, LC_540M, 1024, 33750 }, 117 { 44100, LC_540M, 784, 18750 }, 118 { 48000, LC_540M, 512, 11250 }, 119 { 64000, LC_540M, 2048, 33750 }, 120 { 88200, LC_540M, 1568, 18750 }, 121 { 96000, LC_540M, 1024, 11250 }, 122 { 128000, LC_540M, 4096, 33750 }, 123 { 176400, LC_540M, 3136, 18750 }, 124 { 192000, LC_540M, 2048, 11250 }, 125 { 32000, LC_810M, 1024, 50625 }, 126 { 44100, LC_810M, 784, 28125 }, 127 { 48000, LC_810M, 512, 16875 }, 128 { 64000, LC_810M, 2048, 50625 }, 129 { 88200, LC_810M, 1568, 28125 }, 130 { 96000, LC_810M, 1024, 16875 }, 131 { 128000, LC_810M, 4096, 50625 }, 132 { 176400, LC_810M, 3136, 28125 }, 133 { 192000, LC_810M, 2048, 16875 }, 134 }; 135 136 static const struct dp_aud_n_m * 137 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 138 { 139 int i; 140 141 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 142 if (rate == dp_aud_n_m[i].sample_rate && 143 crtc_state->port_clock == dp_aud_n_m[i].clock) 144 return &dp_aud_n_m[i]; 145 } 146 147 return NULL; 148 } 149 150 static const struct { 151 int clock; 152 u32 config; 153 } hdmi_audio_clock[] = { 154 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 155 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 156 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 157 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 158 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 159 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 160 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 161 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 162 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 163 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 164 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 165 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 166 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 167 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 168 }; 169 170 /* HDMI N/CTS table */ 171 #define TMDS_297M 297000 172 #define TMDS_296M 296703 173 #define TMDS_594M 594000 174 #define TMDS_593M 593407 175 176 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 177 { 32000, TMDS_296M, 5824, 421875 }, 178 { 32000, TMDS_297M, 3072, 222750 }, 179 { 32000, TMDS_593M, 5824, 843750 }, 180 { 32000, TMDS_594M, 3072, 445500 }, 181 { 44100, TMDS_296M, 4459, 234375 }, 182 { 44100, TMDS_297M, 4704, 247500 }, 183 { 44100, TMDS_593M, 8918, 937500 }, 184 { 44100, TMDS_594M, 9408, 990000 }, 185 { 88200, TMDS_296M, 8918, 234375 }, 186 { 88200, TMDS_297M, 9408, 247500 }, 187 { 88200, TMDS_593M, 17836, 937500 }, 188 { 88200, TMDS_594M, 18816, 990000 }, 189 { 176400, TMDS_296M, 17836, 234375 }, 190 { 176400, TMDS_297M, 18816, 247500 }, 191 { 176400, TMDS_593M, 35672, 937500 }, 192 { 176400, TMDS_594M, 37632, 990000 }, 193 { 48000, TMDS_296M, 5824, 281250 }, 194 { 48000, TMDS_297M, 5120, 247500 }, 195 { 48000, TMDS_593M, 5824, 562500 }, 196 { 48000, TMDS_594M, 6144, 594000 }, 197 { 96000, TMDS_296M, 11648, 281250 }, 198 { 96000, TMDS_297M, 10240, 247500 }, 199 { 96000, TMDS_593M, 11648, 562500 }, 200 { 96000, TMDS_594M, 12288, 594000 }, 201 { 192000, TMDS_296M, 23296, 281250 }, 202 { 192000, TMDS_297M, 20480, 247500 }, 203 { 192000, TMDS_593M, 23296, 562500 }, 204 { 192000, TMDS_594M, 24576, 594000 }, 205 }; 206 207 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 208 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 209 #define TMDS_371M 371250 210 #define TMDS_370M 370878 211 212 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 213 { 32000, TMDS_370M, 5824, 527344 }, 214 { 32000, TMDS_371M, 6144, 556875 }, 215 { 44100, TMDS_370M, 8918, 585938 }, 216 { 44100, TMDS_371M, 4704, 309375 }, 217 { 88200, TMDS_370M, 17836, 585938 }, 218 { 88200, TMDS_371M, 9408, 309375 }, 219 { 176400, TMDS_370M, 35672, 585938 }, 220 { 176400, TMDS_371M, 18816, 309375 }, 221 { 48000, TMDS_370M, 11648, 703125 }, 222 { 48000, TMDS_371M, 5120, 309375 }, 223 { 96000, TMDS_370M, 23296, 703125 }, 224 { 96000, TMDS_371M, 10240, 309375 }, 225 { 192000, TMDS_370M, 46592, 703125 }, 226 { 192000, TMDS_371M, 20480, 309375 }, 227 }; 228 229 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 230 #define TMDS_445_5M 445500 231 #define TMDS_445M 445054 232 233 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 234 { 32000, TMDS_445M, 5824, 632813 }, 235 { 32000, TMDS_445_5M, 4096, 445500 }, 236 { 44100, TMDS_445M, 8918, 703125 }, 237 { 44100, TMDS_445_5M, 4704, 371250 }, 238 { 88200, TMDS_445M, 17836, 703125 }, 239 { 88200, TMDS_445_5M, 9408, 371250 }, 240 { 176400, TMDS_445M, 35672, 703125 }, 241 { 176400, TMDS_445_5M, 18816, 371250 }, 242 { 48000, TMDS_445M, 5824, 421875 }, 243 { 48000, TMDS_445_5M, 5120, 371250 }, 244 { 96000, TMDS_445M, 11648, 421875 }, 245 { 96000, TMDS_445_5M, 10240, 371250 }, 246 { 192000, TMDS_445M, 23296, 421875 }, 247 { 192000, TMDS_445_5M, 20480, 371250 }, 248 }; 249 250 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 251 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 252 { 253 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 254 const struct drm_display_mode *adjusted_mode = 255 &crtc_state->hw.adjusted_mode; 256 int i; 257 258 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 259 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 260 break; 261 } 262 263 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) 264 i = ARRAY_SIZE(hdmi_audio_clock); 265 266 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 267 drm_dbg_kms(&i915->drm, 268 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 269 adjusted_mode->crtc_clock); 270 i = 1; 271 } 272 273 drm_dbg_kms(&i915->drm, 274 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 275 hdmi_audio_clock[i].clock, 276 hdmi_audio_clock[i].config); 277 278 return hdmi_audio_clock[i].config; 279 } 280 281 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 282 int rate) 283 { 284 const struct hdmi_aud_ncts *hdmi_ncts_table; 285 int i, size; 286 287 if (crtc_state->pipe_bpp == 36) { 288 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 289 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 290 } else if (crtc_state->pipe_bpp == 30) { 291 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 292 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 293 } else { 294 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 295 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 296 } 297 298 for (i = 0; i < size; i++) { 299 if (rate == hdmi_ncts_table[i].sample_rate && 300 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 301 return hdmi_ncts_table[i].n; 302 } 303 } 304 return 0; 305 } 306 307 /* ELD buffer size in dwords */ 308 static int g4x_eld_buffer_size(struct drm_i915_private *i915) 309 { 310 u32 tmp; 311 312 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 313 314 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 315 } 316 317 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 318 const struct intel_crtc_state *old_crtc_state, 319 const struct drm_connector_state *old_conn_state) 320 { 321 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 322 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 323 324 /* Invalidate ELD */ 325 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 326 G4X_ELD_VALID, 0); 327 328 intel_crtc_wait_for_next_vblank(crtc); 329 intel_crtc_wait_for_next_vblank(crtc); 330 } 331 332 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 333 const struct intel_crtc_state *crtc_state, 334 const struct drm_connector_state *conn_state) 335 { 336 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 337 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 338 struct drm_connector *connector = conn_state->connector; 339 const u32 *eld = (const u32 *)connector->eld; 340 int eld_buffer_size, len, i; 341 342 intel_crtc_wait_for_next_vblank(crtc); 343 344 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 345 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 346 347 eld_buffer_size = g4x_eld_buffer_size(i915); 348 len = min(drm_eld_size(connector->eld) / 4, eld_buffer_size); 349 350 for (i = 0; i < len; i++) 351 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]); 352 for (; i < eld_buffer_size; i++) 353 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0); 354 355 drm_WARN_ON(&i915->drm, 356 (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 357 358 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 359 0, G4X_ELD_VALID); 360 } 361 362 static void 363 hsw_dp_audio_config_update(struct intel_encoder *encoder, 364 const struct intel_crtc_state *crtc_state) 365 { 366 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 367 struct i915_audio_component *acomp = i915->display.audio.component; 368 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 369 enum port port = encoder->port; 370 const struct dp_aud_n_m *nm; 371 int rate; 372 u32 tmp; 373 374 rate = acomp ? acomp->aud_sample_rate[port] : 0; 375 nm = audio_config_dp_get_n_m(crtc_state, rate); 376 if (nm) 377 drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m, 378 nm->n); 379 else 380 drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n"); 381 382 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); 383 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 384 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 385 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 386 tmp |= AUD_CONFIG_N_VALUE_INDEX; 387 388 if (nm) { 389 tmp &= ~AUD_CONFIG_N_MASK; 390 tmp |= AUD_CONFIG_N(nm->n); 391 tmp |= AUD_CONFIG_N_PROG_ENABLE; 392 } 393 394 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 395 396 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 397 tmp &= ~AUD_CONFIG_M_MASK; 398 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 399 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 400 401 if (nm) { 402 tmp |= nm->m; 403 tmp |= AUD_M_CTS_M_VALUE_INDEX; 404 tmp |= AUD_M_CTS_M_PROG_ENABLE; 405 } 406 407 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 408 } 409 410 static void 411 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 412 const struct intel_crtc_state *crtc_state) 413 { 414 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 415 struct i915_audio_component *acomp = i915->display.audio.component; 416 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 417 enum port port = encoder->port; 418 int n, rate; 419 u32 tmp; 420 421 rate = acomp ? acomp->aud_sample_rate[port] : 0; 422 423 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); 424 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 425 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 426 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 427 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 428 429 n = audio_config_hdmi_get_n(crtc_state, rate); 430 if (n != 0) { 431 drm_dbg_kms(&i915->drm, "using N %d\n", n); 432 433 tmp &= ~AUD_CONFIG_N_MASK; 434 tmp |= AUD_CONFIG_N(n); 435 tmp |= AUD_CONFIG_N_PROG_ENABLE; 436 } else { 437 drm_dbg_kms(&i915->drm, "using automatic N\n"); 438 } 439 440 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 441 442 /* 443 * Let's disable "Enable CTS or M Prog bit" 444 * and let HW calculate the value 445 */ 446 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 447 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 448 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 449 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 450 } 451 452 static void 453 hsw_audio_config_update(struct intel_encoder *encoder, 454 const struct intel_crtc_state *crtc_state) 455 { 456 if (intel_crtc_has_dp_encoder(crtc_state)) 457 hsw_dp_audio_config_update(encoder, crtc_state); 458 else 459 hsw_hdmi_audio_config_update(encoder, crtc_state); 460 } 461 462 /* ELD buffer size in dwords */ 463 static int hsw_eld_buffer_size(struct drm_i915_private *i915, 464 enum transcoder cpu_transcoder) 465 { 466 u32 tmp; 467 468 tmp = intel_de_read(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 469 470 return REG_FIELD_GET(IBX_ELD_BUFFER_SIZE_MASK, tmp); 471 } 472 473 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 474 const struct intel_crtc_state *old_crtc_state, 475 const struct drm_connector_state *old_conn_state) 476 { 477 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 478 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 479 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 480 481 mutex_lock(&i915->display.audio.mutex); 482 483 /* Disable timestamps */ 484 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 485 AUD_CONFIG_N_VALUE_INDEX | 486 AUD_CONFIG_UPPER_N_MASK | 487 AUD_CONFIG_LOWER_N_MASK, 488 AUD_CONFIG_N_PROG_ENABLE | 489 (intel_crtc_has_dp_encoder(old_crtc_state) ? 490 AUD_CONFIG_N_VALUE_INDEX : 0)); 491 492 /* Invalidate ELD */ 493 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 494 AUDIO_ELD_VALID(cpu_transcoder), 0); 495 496 intel_crtc_wait_for_next_vblank(crtc); 497 intel_crtc_wait_for_next_vblank(crtc); 498 499 /* Disable audio presence detect */ 500 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 501 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 502 503 mutex_unlock(&i915->display.audio.mutex); 504 } 505 506 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 507 const struct intel_crtc_state *crtc_state) 508 { 509 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 510 unsigned int link_clks_available, link_clks_required; 511 unsigned int tu_data, tu_line, link_clks_active; 512 unsigned int h_active, h_total, hblank_delta, pixel_clk; 513 unsigned int fec_coeff, cdclk, vdsc_bpp; 514 unsigned int link_clk, lanes; 515 unsigned int hblank_rise; 516 517 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 518 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 519 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 520 vdsc_bpp = crtc_state->dsc.compressed_bpp; 521 cdclk = i915->display.cdclk.hw.cdclk; 522 /* fec= 0.972261, using rounding multiplier of 1000000 */ 523 fec_coeff = 972261; 524 link_clk = crtc_state->port_clock; 525 lanes = crtc_state->lane_count; 526 527 drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :" 528 "lanes = %u vdsc_bpp = %u cdclk = %u\n", 529 h_active, link_clk, lanes, vdsc_bpp, cdclk); 530 531 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) 532 return 0; 533 534 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 535 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 536 537 if (link_clks_available > link_clks_required) 538 hblank_delta = 32; 539 else 540 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 541 mul_u32_u32(link_clk, cdclk)); 542 543 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), 544 mul_u32_u32(link_clk * lanes, fec_coeff)); 545 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 546 mul_u32_u32(64 * pixel_clk, 1000000)); 547 link_clks_active = (tu_line - 1) * 64 + tu_data; 548 549 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 550 551 return h_active - hblank_rise + hblank_delta; 552 } 553 554 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 555 { 556 unsigned int h_active, h_total, pixel_clk; 557 unsigned int link_clk, lanes; 558 559 h_active = crtc_state->hw.adjusted_mode.hdisplay; 560 h_total = crtc_state->hw.adjusted_mode.htotal; 561 pixel_clk = crtc_state->hw.adjusted_mode.clock; 562 link_clk = crtc_state->port_clock; 563 lanes = crtc_state->lane_count; 564 565 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 566 (pixel_clk * (48 / lanes + 2)); 567 } 568 569 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 570 const struct intel_crtc_state *crtc_state) 571 { 572 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 573 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 574 enum pipe pipe = crtc->pipe; 575 unsigned int hblank_early_prog, samples_room; 576 unsigned int val; 577 578 if (DISPLAY_VER(i915) < 11) 579 return; 580 581 val = intel_de_read(i915, AUD_CONFIG_BE); 582 583 if (DISPLAY_VER(i915) == 11) 584 val |= HBLANK_EARLY_ENABLE_ICL(pipe); 585 else if (DISPLAY_VER(i915) >= 12) 586 val |= HBLANK_EARLY_ENABLE_TGL(pipe); 587 588 if (crtc_state->dsc.compression_enable && 589 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 590 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 591 /* Get hblank early enable value required */ 592 val &= ~HBLANK_START_COUNT_MASK(pipe); 593 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 594 if (hblank_early_prog < 32) 595 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32); 596 else if (hblank_early_prog < 64) 597 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64); 598 else if (hblank_early_prog < 96) 599 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96); 600 else 601 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128); 602 603 /* Get samples room value required */ 604 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe); 605 samples_room = calc_samples_room(crtc_state); 606 if (samples_room < 3) 607 val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room); 608 else /* Program 0 i.e "All Samples available in buffer" */ 609 val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0); 610 } 611 612 intel_de_write(i915, AUD_CONFIG_BE, val); 613 } 614 615 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 616 const struct intel_crtc_state *crtc_state, 617 const struct drm_connector_state *conn_state) 618 { 619 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 620 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 621 struct drm_connector *connector = conn_state->connector; 622 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 623 const u32 *eld = (const u32 *)connector->eld; 624 int eld_buffer_size, len, i; 625 626 mutex_lock(&i915->display.audio.mutex); 627 628 /* Enable Audio WA for 4k DSC usecases */ 629 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 630 enable_audio_dsc_wa(encoder, crtc_state); 631 632 /* Enable audio presence detect */ 633 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 634 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 635 636 intel_crtc_wait_for_next_vblank(crtc); 637 638 /* Invalidate ELD */ 639 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 640 AUDIO_ELD_VALID(cpu_transcoder), 0); 641 642 /* Reset ELD address */ 643 intel_de_rmw(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), 644 IBX_ELD_ADDRESS_MASK, 0); 645 646 eld_buffer_size = hsw_eld_buffer_size(i915, cpu_transcoder); 647 len = min(drm_eld_size(connector->eld) / 4, eld_buffer_size); 648 649 for (i = 0; i < len; i++) 650 intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder), eld[i]); 651 for (; i < eld_buffer_size; i++) 652 intel_de_write(i915, HSW_AUD_EDID_DATA(cpu_transcoder), 0); 653 654 drm_WARN_ON(&i915->drm, 655 (intel_de_read(i915, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)) & 656 IBX_ELD_ADDRESS_MASK) != 0); 657 658 /* ELD valid */ 659 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 660 0, AUDIO_ELD_VALID(cpu_transcoder)); 661 662 /* Enable timestamps */ 663 hsw_audio_config_update(encoder, crtc_state); 664 665 mutex_unlock(&i915->display.audio.mutex); 666 } 667 668 struct ilk_audio_regs { 669 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 670 }; 671 672 static void ilk_audio_regs_init(struct drm_i915_private *i915, 673 enum pipe pipe, 674 struct ilk_audio_regs *regs) 675 { 676 if (HAS_PCH_IBX(i915)) { 677 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 678 regs->aud_config = IBX_AUD_CFG(pipe); 679 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 680 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 681 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 682 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 683 regs->aud_config = VLV_AUD_CFG(pipe); 684 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 685 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 686 } else { 687 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 688 regs->aud_config = CPT_AUD_CFG(pipe); 689 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 690 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 691 } 692 } 693 694 /* ELD buffer size in dwords */ 695 static int ilk_eld_buffer_size(struct drm_i915_private *i915, 696 enum pipe pipe) 697 { 698 struct ilk_audio_regs regs; 699 u32 tmp; 700 701 ilk_audio_regs_init(i915, pipe, ®s); 702 703 tmp = intel_de_read(i915, regs.aud_cntl_st); 704 705 return REG_FIELD_GET(IBX_ELD_BUFFER_SIZE_MASK, tmp); 706 } 707 708 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 709 const struct intel_crtc_state *old_crtc_state, 710 const struct drm_connector_state *old_conn_state) 711 { 712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 713 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 714 enum port port = encoder->port; 715 enum pipe pipe = crtc->pipe; 716 struct ilk_audio_regs regs; 717 718 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 719 return; 720 721 ilk_audio_regs_init(i915, pipe, ®s); 722 723 mutex_lock(&i915->display.audio.mutex); 724 725 /* Disable timestamps */ 726 intel_de_rmw(i915, regs.aud_config, 727 AUD_CONFIG_N_VALUE_INDEX | 728 AUD_CONFIG_UPPER_N_MASK | 729 AUD_CONFIG_LOWER_N_MASK, 730 AUD_CONFIG_N_PROG_ENABLE | 731 (intel_crtc_has_dp_encoder(old_crtc_state) ? 732 AUD_CONFIG_N_VALUE_INDEX : 0)); 733 734 /* Invalidate ELD */ 735 intel_de_rmw(i915, regs.aud_cntrl_st2, 736 IBX_ELD_VALID(port), 0); 737 738 mutex_unlock(&i915->display.audio.mutex); 739 740 intel_crtc_wait_for_next_vblank(crtc); 741 intel_crtc_wait_for_next_vblank(crtc); 742 } 743 744 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 745 const struct intel_crtc_state *crtc_state, 746 const struct drm_connector_state *conn_state) 747 { 748 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 749 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 750 struct drm_connector *connector = conn_state->connector; 751 const u32 *eld = (const u32 *)connector->eld; 752 enum port port = encoder->port; 753 enum pipe pipe = crtc->pipe; 754 int eld_buffer_size, len, i; 755 struct ilk_audio_regs regs; 756 757 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 758 return; 759 760 intel_crtc_wait_for_next_vblank(crtc); 761 762 ilk_audio_regs_init(i915, pipe, ®s); 763 764 mutex_lock(&i915->display.audio.mutex); 765 766 /* Invalidate ELD */ 767 intel_de_rmw(i915, regs.aud_cntrl_st2, 768 IBX_ELD_VALID(port), 0); 769 770 /* Reset ELD address */ 771 intel_de_rmw(i915, regs.aud_cntl_st, 772 IBX_ELD_ADDRESS_MASK, 0); 773 774 eld_buffer_size = ilk_eld_buffer_size(i915, pipe); 775 len = min(drm_eld_size(connector->eld) / 4, eld_buffer_size); 776 777 for (i = 0; i < len; i++) 778 intel_de_write(i915, regs.hdmiw_hdmiedid, eld[i]); 779 for (; i < eld_buffer_size; i++) 780 intel_de_write(i915, regs.hdmiw_hdmiedid, 0); 781 782 drm_WARN_ON(&i915->drm, 783 (intel_de_read(i915, regs.aud_cntl_st) & IBX_ELD_ADDRESS_MASK) != 0); 784 785 /* ELD valid */ 786 intel_de_rmw(i915, regs.aud_cntrl_st2, 787 0, IBX_ELD_VALID(port)); 788 789 /* Enable timestamps */ 790 intel_de_rmw(i915, regs.aud_config, 791 AUD_CONFIG_N_VALUE_INDEX | 792 AUD_CONFIG_N_PROG_ENABLE | 793 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 794 (intel_crtc_has_dp_encoder(crtc_state) ? 795 AUD_CONFIG_N_VALUE_INDEX : 796 audio_config_hdmi_pixel_clock(crtc_state))); 797 798 mutex_unlock(&i915->display.audio.mutex); 799 } 800 801 /** 802 * intel_audio_codec_enable - Enable the audio codec for HD audio 803 * @encoder: encoder on which to enable audio 804 * @crtc_state: pointer to the current crtc state. 805 * @conn_state: pointer to the current connector state. 806 * 807 * The enable sequences may only be performed after enabling the transcoder and 808 * port, and after completed link training. 809 */ 810 void intel_audio_codec_enable(struct intel_encoder *encoder, 811 const struct intel_crtc_state *crtc_state, 812 const struct drm_connector_state *conn_state) 813 { 814 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 815 struct i915_audio_component *acomp = i915->display.audio.component; 816 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 817 struct drm_connector *connector = conn_state->connector; 818 const struct drm_display_mode *adjusted_mode = 819 &crtc_state->hw.adjusted_mode; 820 enum port port = encoder->port; 821 enum pipe pipe = crtc->pipe; 822 823 if (!crtc_state->has_audio) 824 return; 825 826 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on pipe %c, %u bytes ELD\n", 827 connector->base.id, connector->name, 828 encoder->base.base.id, encoder->base.name, 829 pipe_name(pipe), drm_eld_size(connector->eld)); 830 831 /* FIXME precompute the ELD in .compute_config() */ 832 if (!connector->eld[0]) 833 drm_dbg_kms(&i915->drm, 834 "Bogus ELD on [CONNECTOR:%d:%s]\n", 835 connector->base.id, connector->name); 836 837 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 838 839 if (i915->display.funcs.audio) 840 i915->display.funcs.audio->audio_codec_enable(encoder, 841 crtc_state, 842 conn_state); 843 844 mutex_lock(&i915->display.audio.mutex); 845 encoder->audio_connector = connector; 846 847 /* referred in audio callbacks */ 848 i915->display.audio.encoder_map[pipe] = encoder; 849 mutex_unlock(&i915->display.audio.mutex); 850 851 if (acomp && acomp->base.audio_ops && 852 acomp->base.audio_ops->pin_eld_notify) { 853 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 854 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 855 pipe = -1; 856 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 857 (int)port, (int)pipe); 858 } 859 860 intel_lpe_audio_notify(i915, pipe, port, connector->eld, 861 crtc_state->port_clock, 862 intel_crtc_has_dp_encoder(crtc_state)); 863 } 864 865 /** 866 * intel_audio_codec_disable - Disable the audio codec for HD audio 867 * @encoder: encoder on which to disable audio 868 * @old_crtc_state: pointer to the old crtc state. 869 * @old_conn_state: pointer to the old connector state. 870 * 871 * The disable sequences must be performed before disabling the transcoder or 872 * port. 873 */ 874 void intel_audio_codec_disable(struct intel_encoder *encoder, 875 const struct intel_crtc_state *old_crtc_state, 876 const struct drm_connector_state *old_conn_state) 877 { 878 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 879 struct i915_audio_component *acomp = i915->display.audio.component; 880 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 881 struct drm_connector *connector = old_conn_state->connector; 882 enum port port = encoder->port; 883 enum pipe pipe = crtc->pipe; 884 885 if (!old_crtc_state->has_audio) 886 return; 887 888 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on pipe %c\n", 889 connector->base.id, connector->name, 890 encoder->base.base.id, encoder->base.name, pipe_name(pipe)); 891 892 if (i915->display.funcs.audio) 893 i915->display.funcs.audio->audio_codec_disable(encoder, 894 old_crtc_state, 895 old_conn_state); 896 897 mutex_lock(&i915->display.audio.mutex); 898 encoder->audio_connector = NULL; 899 i915->display.audio.encoder_map[pipe] = NULL; 900 mutex_unlock(&i915->display.audio.mutex); 901 902 if (acomp && acomp->base.audio_ops && 903 acomp->base.audio_ops->pin_eld_notify) { 904 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 905 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 906 pipe = -1; 907 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 908 (int)port, (int)pipe); 909 } 910 911 intel_lpe_audio_notify(i915, pipe, port, NULL, 0, false); 912 } 913 914 static const struct intel_audio_funcs g4x_audio_funcs = { 915 .audio_codec_enable = g4x_audio_codec_enable, 916 .audio_codec_disable = g4x_audio_codec_disable, 917 }; 918 919 static const struct intel_audio_funcs ilk_audio_funcs = { 920 .audio_codec_enable = ilk_audio_codec_enable, 921 .audio_codec_disable = ilk_audio_codec_disable, 922 }; 923 924 static const struct intel_audio_funcs hsw_audio_funcs = { 925 .audio_codec_enable = hsw_audio_codec_enable, 926 .audio_codec_disable = hsw_audio_codec_disable, 927 }; 928 929 /** 930 * intel_audio_hooks_init - Set up chip specific audio hooks 931 * @i915: device private 932 */ 933 void intel_audio_hooks_init(struct drm_i915_private *i915) 934 { 935 if (IS_G4X(i915)) 936 i915->display.funcs.audio = &g4x_audio_funcs; 937 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 938 i915->display.funcs.audio = &ilk_audio_funcs; 939 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) 940 i915->display.funcs.audio = &hsw_audio_funcs; 941 else if (HAS_PCH_SPLIT(i915)) 942 i915->display.funcs.audio = &ilk_audio_funcs; 943 } 944 945 struct aud_ts_cdclk_m_n { 946 u8 m; 947 u16 n; 948 }; 949 950 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) 951 { 952 if (DISPLAY_VER(i915) >= 13) 953 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 954 } 955 956 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 957 { 958 if (refclk == 24000) 959 aud_ts->m = 12; 960 else 961 aud_ts->m = 15; 962 963 aud_ts->n = cdclk * aud_ts->m / 24000; 964 } 965 966 void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 967 { 968 struct aud_ts_cdclk_m_n aud_ts; 969 970 if (DISPLAY_VER(i915) >= 13) { 971 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); 972 973 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 974 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 975 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); 976 } 977 } 978 979 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 980 struct intel_crtc *crtc, 981 bool enable) 982 { 983 struct intel_cdclk_state *cdclk_state; 984 int ret; 985 986 /* need to hold at least one crtc lock for the global state */ 987 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 988 if (ret) 989 return ret; 990 991 cdclk_state = intel_atomic_get_cdclk_state(state); 992 if (IS_ERR(cdclk_state)) 993 return PTR_ERR(cdclk_state); 994 995 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 996 997 return drm_atomic_commit(&state->base); 998 } 999 1000 static void glk_force_audio_cdclk(struct drm_i915_private *i915, 1001 bool enable) 1002 { 1003 struct drm_modeset_acquire_ctx ctx; 1004 struct drm_atomic_state *state; 1005 struct intel_crtc *crtc; 1006 int ret; 1007 1008 crtc = intel_first_crtc(i915); 1009 if (!crtc) 1010 return; 1011 1012 drm_modeset_acquire_init(&ctx, 0); 1013 state = drm_atomic_state_alloc(&i915->drm); 1014 if (drm_WARN_ON(&i915->drm, !state)) 1015 return; 1016 1017 state->acquire_ctx = &ctx; 1018 1019 retry: 1020 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 1021 enable); 1022 if (ret == -EDEADLK) { 1023 drm_atomic_state_clear(state); 1024 drm_modeset_backoff(&ctx); 1025 goto retry; 1026 } 1027 1028 drm_WARN_ON(&i915->drm, ret); 1029 1030 drm_atomic_state_put(state); 1031 1032 drm_modeset_drop_locks(&ctx); 1033 drm_modeset_acquire_fini(&ctx); 1034 } 1035 1036 static unsigned long i915_audio_component_get_power(struct device *kdev) 1037 { 1038 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1039 intel_wakeref_t ret; 1040 1041 /* Catch potential impedance mismatches before they occur! */ 1042 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1043 1044 ret = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK); 1045 1046 if (i915->display.audio.power_refcount++ == 0) { 1047 if (DISPLAY_VER(i915) >= 9) { 1048 intel_de_write(i915, AUD_FREQ_CNTRL, 1049 i915->display.audio.freq_cntrl); 1050 drm_dbg_kms(&i915->drm, 1051 "restored AUD_FREQ_CNTRL to 0x%x\n", 1052 i915->display.audio.freq_cntrl); 1053 } 1054 1055 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1056 if (IS_GEMINILAKE(i915)) 1057 glk_force_audio_cdclk(i915, true); 1058 1059 if (DISPLAY_VER(i915) >= 10) 1060 intel_de_rmw(i915, AUD_PIN_BUF_CTL, 1061 0, AUD_PIN_BUF_ENABLE); 1062 } 1063 1064 return ret; 1065 } 1066 1067 static void i915_audio_component_put_power(struct device *kdev, 1068 unsigned long cookie) 1069 { 1070 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1071 1072 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1073 if (--i915->display.audio.power_refcount == 0) 1074 if (IS_GEMINILAKE(i915)) 1075 glk_force_audio_cdclk(i915, false); 1076 1077 intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, cookie); 1078 } 1079 1080 static void i915_audio_component_codec_wake_override(struct device *kdev, 1081 bool enable) 1082 { 1083 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1084 unsigned long cookie; 1085 1086 if (DISPLAY_VER(i915) < 9) 1087 return; 1088 1089 cookie = i915_audio_component_get_power(kdev); 1090 1091 /* 1092 * Enable/disable generating the codec wake signal, overriding the 1093 * internal logic to generate the codec wake to controller. 1094 */ 1095 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1096 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1097 usleep_range(1000, 1500); 1098 1099 if (enable) { 1100 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1101 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1102 usleep_range(1000, 1500); 1103 } 1104 1105 i915_audio_component_put_power(kdev, cookie); 1106 } 1107 1108 /* Get CDCLK in kHz */ 1109 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 1110 { 1111 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1112 1113 if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915))) 1114 return -ENODEV; 1115 1116 return i915->display.cdclk.hw.cdclk; 1117 } 1118 1119 /* 1120 * get the intel_encoder according to the parameter port and pipe 1121 * intel_encoder is saved by the index of pipe 1122 * MST & (pipe >= 0): return the audio.encoder_map[pipe], 1123 * when port is matched 1124 * MST & (pipe < 0): this is invalid 1125 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 1126 * will get the right intel_encoder with port matched 1127 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 1128 */ 1129 static struct intel_encoder *get_saved_enc(struct drm_i915_private *i915, 1130 int port, int pipe) 1131 { 1132 /* MST */ 1133 if (pipe >= 0) { 1134 struct intel_encoder *encoder; 1135 1136 if (drm_WARN_ON(&i915->drm, 1137 pipe >= ARRAY_SIZE(i915->display.audio.encoder_map))) 1138 return NULL; 1139 1140 encoder = i915->display.audio.encoder_map[pipe]; 1141 /* 1142 * when bootup, audio driver may not know it is 1143 * MST or not. So it will poll all the port & pipe 1144 * combinations 1145 */ 1146 if (encoder && encoder->port == port && 1147 encoder->type == INTEL_OUTPUT_DP_MST) 1148 return encoder; 1149 } 1150 1151 /* Non-MST */ 1152 if (pipe > 0) 1153 return NULL; 1154 1155 for_each_pipe(i915, pipe) { 1156 struct intel_encoder *encoder; 1157 1158 encoder = i915->display.audio.encoder_map[pipe]; 1159 1160 if (encoder && encoder->port == port && 1161 encoder->type != INTEL_OUTPUT_DP_MST) 1162 return encoder; 1163 } 1164 1165 return NULL; 1166 } 1167 1168 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1169 int pipe, int rate) 1170 { 1171 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1172 struct i915_audio_component *acomp = i915->display.audio.component; 1173 struct intel_encoder *encoder; 1174 struct intel_crtc *crtc; 1175 unsigned long cookie; 1176 int err = 0; 1177 1178 if (!HAS_DDI(i915)) 1179 return 0; 1180 1181 cookie = i915_audio_component_get_power(kdev); 1182 mutex_lock(&i915->display.audio.mutex); 1183 1184 /* 1. get the pipe */ 1185 encoder = get_saved_enc(i915, port, pipe); 1186 if (!encoder || !encoder->base.crtc) { 1187 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", 1188 port_name(port)); 1189 err = -ENODEV; 1190 goto unlock; 1191 } 1192 1193 crtc = to_intel_crtc(encoder->base.crtc); 1194 1195 /* port must be valid now, otherwise the pipe will be invalid */ 1196 acomp->aud_sample_rate[port] = rate; 1197 1198 hsw_audio_config_update(encoder, crtc->config); 1199 1200 unlock: 1201 mutex_unlock(&i915->display.audio.mutex); 1202 i915_audio_component_put_power(kdev, cookie); 1203 return err; 1204 } 1205 1206 static int i915_audio_component_get_eld(struct device *kdev, int port, 1207 int pipe, bool *enabled, 1208 unsigned char *buf, int max_bytes) 1209 { 1210 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1211 struct intel_encoder *intel_encoder; 1212 const u8 *eld; 1213 int ret = -EINVAL; 1214 1215 mutex_lock(&i915->display.audio.mutex); 1216 1217 intel_encoder = get_saved_enc(i915, port, pipe); 1218 if (!intel_encoder) { 1219 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", 1220 port_name(port)); 1221 mutex_unlock(&i915->display.audio.mutex); 1222 return ret; 1223 } 1224 1225 ret = 0; 1226 *enabled = intel_encoder->audio_connector != NULL; 1227 if (*enabled) { 1228 eld = intel_encoder->audio_connector->eld; 1229 ret = drm_eld_size(eld); 1230 memcpy(buf, eld, min(max_bytes, ret)); 1231 } 1232 1233 mutex_unlock(&i915->display.audio.mutex); 1234 return ret; 1235 } 1236 1237 static const struct drm_audio_component_ops i915_audio_component_ops = { 1238 .owner = THIS_MODULE, 1239 .get_power = i915_audio_component_get_power, 1240 .put_power = i915_audio_component_put_power, 1241 .codec_wake_override = i915_audio_component_codec_wake_override, 1242 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1243 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1244 .get_eld = i915_audio_component_get_eld, 1245 }; 1246 1247 static int i915_audio_component_bind(struct device *i915_kdev, 1248 struct device *hda_kdev, void *data) 1249 { 1250 struct i915_audio_component *acomp = data; 1251 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1252 int i; 1253 1254 if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev)) 1255 return -EEXIST; 1256 1257 if (drm_WARN_ON(&i915->drm, 1258 !device_link_add(hda_kdev, i915_kdev, 1259 DL_FLAG_STATELESS))) 1260 return -ENOMEM; 1261 1262 drm_modeset_lock_all(&i915->drm); 1263 acomp->base.ops = &i915_audio_component_ops; 1264 acomp->base.dev = i915_kdev; 1265 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1266 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1267 acomp->aud_sample_rate[i] = 0; 1268 i915->display.audio.component = acomp; 1269 drm_modeset_unlock_all(&i915->drm); 1270 1271 return 0; 1272 } 1273 1274 static void i915_audio_component_unbind(struct device *i915_kdev, 1275 struct device *hda_kdev, void *data) 1276 { 1277 struct i915_audio_component *acomp = data; 1278 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1279 1280 drm_modeset_lock_all(&i915->drm); 1281 acomp->base.ops = NULL; 1282 acomp->base.dev = NULL; 1283 i915->display.audio.component = NULL; 1284 drm_modeset_unlock_all(&i915->drm); 1285 1286 device_link_remove(hda_kdev, i915_kdev); 1287 1288 if (i915->display.audio.power_refcount) 1289 drm_err(&i915->drm, "audio power refcount %d after unbind\n", 1290 i915->display.audio.power_refcount); 1291 } 1292 1293 static const struct component_ops i915_audio_component_bind_ops = { 1294 .bind = i915_audio_component_bind, 1295 .unbind = i915_audio_component_unbind, 1296 }; 1297 1298 #define AUD_FREQ_TMODE_SHIFT 14 1299 #define AUD_FREQ_4T 0 1300 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1301 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1302 #define AUD_FREQ_BCLK_96M BIT(4) 1303 1304 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1305 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1306 1307 /** 1308 * i915_audio_component_init - initialize and register the audio component 1309 * @i915: i915 device instance 1310 * 1311 * This will register with the component framework a child component which 1312 * will bind dynamically to the snd_hda_intel driver's corresponding master 1313 * component when the latter is registered. During binding the child 1314 * initializes an instance of struct i915_audio_component which it receives 1315 * from the master. The master can then start to use the interface defined by 1316 * this struct. Each side can break the binding at any point by deregistering 1317 * its own component after which each side's component unbind callback is 1318 * called. 1319 * 1320 * We ignore any error during registration and continue with reduced 1321 * functionality (i.e. without HDMI audio). 1322 */ 1323 static void i915_audio_component_init(struct drm_i915_private *i915) 1324 { 1325 u32 aud_freq, aud_freq_init; 1326 int ret; 1327 1328 ret = component_add_typed(i915->drm.dev, 1329 &i915_audio_component_bind_ops, 1330 I915_COMPONENT_AUDIO); 1331 if (ret < 0) { 1332 drm_err(&i915->drm, 1333 "failed to add audio component (%d)\n", ret); 1334 /* continue with reduced functionality */ 1335 return; 1336 } 1337 1338 if (DISPLAY_VER(i915) >= 9) { 1339 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); 1340 1341 if (DISPLAY_VER(i915) >= 12) 1342 aud_freq = AUD_FREQ_GEN12; 1343 else 1344 aud_freq = aud_freq_init; 1345 1346 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1347 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) && 1348 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1349 aud_freq = aud_freq_init; 1350 1351 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1352 aud_freq, aud_freq_init); 1353 1354 i915->display.audio.freq_cntrl = aud_freq; 1355 } 1356 1357 /* init with current cdclk */ 1358 intel_audio_cdclk_change_post(i915); 1359 1360 i915->display.audio.component_registered = true; 1361 } 1362 1363 /** 1364 * i915_audio_component_cleanup - deregister the audio component 1365 * @i915: i915 device instance 1366 * 1367 * Deregisters the audio component, breaking any existing binding to the 1368 * corresponding snd_hda_intel driver's master component. 1369 */ 1370 static void i915_audio_component_cleanup(struct drm_i915_private *i915) 1371 { 1372 if (!i915->display.audio.component_registered) 1373 return; 1374 1375 component_del(i915->drm.dev, &i915_audio_component_bind_ops); 1376 i915->display.audio.component_registered = false; 1377 } 1378 1379 /** 1380 * intel_audio_init() - Initialize the audio driver either using 1381 * component framework or using lpe audio bridge 1382 * @i915: the i915 drm device private data 1383 * 1384 */ 1385 void intel_audio_init(struct drm_i915_private *i915) 1386 { 1387 if (intel_lpe_audio_init(i915) < 0) 1388 i915_audio_component_init(i915); 1389 } 1390 1391 /** 1392 * intel_audio_deinit() - deinitialize the audio driver 1393 * @i915: the i915 drm device private data 1394 * 1395 */ 1396 void intel_audio_deinit(struct drm_i915_private *i915) 1397 { 1398 if (i915->display.audio.lpe.platdev != NULL) 1399 intel_lpe_audio_teardown(i915); 1400 else 1401 i915_audio_component_cleanup(i915); 1402 } 1403